| root@nvidia-desktop:/home/nvidia# cat /sys/kernel/debug/clk/clk_summary | <> | root@stevie:/home/nvidia# cat /sys/kernel/debug/clk/clk_summary |
| clock enable_cnt prepare_cnt rate req_rate accuracy phase | = | clock enable_cnt prepare_cnt rate req_rate accuracy phase |
| ---------------------------------------------------------------------------------------------------------------------- | ---------------------------------------------------------------------------------------------------------------------- | |
| gpcclk 0 0 318750000 318750000 0 0 | gpcclk 0 0 318750000 318750000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| pex1_core_5 1 1 500000000 500000000 0 0 | pex1_core_5 1 1 500000000 500000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| pex0_core_4 0 0 500000000 500000000 0 0 | pex0_core_4 0 0 500000000 500000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| pex0_core_3 0 0 500000000 500000000 0 0 | <> | pex0_core_3 1 1 62500000 62500000 0 0 |
| *[ default_freq 0] | = | *[ default_freq 0] |
| pex0_core_1 0 0 500000000 500000000 0 0 | pex0_core_1 0 0 500000000 500000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| pex0_core_0 0 0 500000000 500000000 0 0 | pex0_core_0 0 0 500000000 500000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2s6_sync_input 0 0 0 0 0 0 | i2s6_sync_input 0 0 0 0 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2s5_sync_input 0 0 0 0 0 0 | i2s5_sync_input 0 0 0 0 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2s4_sync_input 0 0 0 0 0 0 | i2s4_sync_input 0 0 0 0 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2s3_sync_input 0 0 0 0 0 0 | i2s3_sync_input 0 0 0 0 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2s2_sync_input 0 0 0 0 0 0 | i2s2_sync_input 0 0 0 0 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2s1_sync_input 0 0 1536000 1536000 0 0 | <> | i2s1_sync_input 0 0 1411200 1411200 0 0 |
| *[ default_freq 0] | = | *[ default_freq 0] |
| dspk2_sync_clk 0 0 1536000 0 0 0 | <> | dspk2_sync_clk 0 0 1411200 0 0 0 |
| *[ default_freq 0] | = | *[ default_freq 0] |
| dspk1_sync_clk 0 0 1536000 0 0 0 | <> | dspk1_sync_clk 0 0 1411200 0 0 0 |
| *[ default_freq 0] | = | *[ default_freq 0] |
| dmic4_sync_clk 0 0 1536000 0 0 0 | <> | dmic4_sync_clk 0 0 1411200 0 0 0 |
| *[ default_freq 0] | = | *[ default_freq 0] |
| dmic3_sync_clk 0 0 1536000 0 0 0 | <> | dmic3_sync_clk 0 0 1411200 0 0 0 |
| *[ default_freq 0] | = | *[ default_freq 0] |
| dmic2_sync_clk 0 0 1536000 0 0 0 | <> | dmic2_sync_clk 0 0 1411200 0 0 0 |
| *[ default_freq 0] | = | *[ default_freq 0] |
| dmic1_sync_clk 0 0 1536000 0 0 0 | <> | dmic1_sync_clk 0 0 1411200 0 0 0 |
| *[ default_freq 0] | = | *[ default_freq 0] |
| spdifin_input 0 0 0 0 0 0 | spdifin_input 0 0 0 0 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2s6_sync_clk 0 0 0 0 0 0 | i2s6_sync_clk 0 0 0 0 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2s5_sync_clk 0 0 0 0 0 0 | i2s5_sync_clk 0 0 0 0 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2s4_sync_clk 0 0 0 0 0 0 | i2s4_sync_clk 0 0 0 0 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2s3_sync_clk 0 0 0 0 0 0 | i2s3_sync_clk 0 0 0 0 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2s2_sync_clk 0 0 0 0 0 0 | i2s2_sync_clk 0 0 0 0 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2s1_sync_clk 0 0 0 0 0 0 | i2s1_sync_clk 0 0 0 0 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| spe_pll_aon 0 0 0 0 0 0 | spe_pll_aon 0 0 0 0 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| pll_c4 0 0 781000781 781000781 0 0 | <> | |
| *[ default_freq 0] | ||
| sdmmc4 0 0 195250195 200000000 0 0 | ||
| *[ default_freq 0] | ||
| pllc4_vco_div2 0 0 390500390 390500390 0 0 | ||
| *[ default_freq 0] | ||
| pllc4_muxed 0 0 390500390 390500390 0 0 | ||
| *[ default_freq 0] | ||
| pllc4_out2 0 0 156200156 156200156 0 0 | ||
| *[ default_freq 0] | ||
| pllc4_out1 0 0 260333593 260333593 0 0 | ||
| *[ default_freq 0] | ||
| gpu_pwr 0 0 204000000 204000000 0 0 | sor0_pad_clkout 0 0 600000000 600000000 0 0 | |
| *[ default_freq 0] | = | *[ default_freq 0] |
| nafll_gpu 0 0 0 0 0 0 | +- | |
| *[ default_freq 0] | ||
| utmipll 2 2 960000000 960000000 0 0 | ||
| *[ default_freq 0] | ||
| utmipll_clkout480 1 1 480000000 480000000 0 0 | ||
| *[ default_freq 0] | ||
| xusb_ss 1 1 120000000 120000000 0 0 | ||
| *[ default_freq 0] | ||
| xusb_ss_superspeed 1 1 120000000 120000000 0 0 | ||
| *[ default_freq 0] | ||
| utmipll_clkout48 1 1 48000000 48000000 0 0 | ||
| *[ default_freq 0] | ||
| xusb_fs 2 2 48000000 48000000 0 0 | ||
| *[ default_freq 0] | ||
| xusb_fs_host 1 1 48000000 48000000 0 0 | ||
| *[ default_freq 0] | ||
| eqos_rx_input 1 1 0 0 0 0 | = | eqos_rx_input 1 1 0 0 0 0 |
| *[ default_freq 0] | *[ default_freq 0] | |
| eqos_rx 1 1 0 0 0 0 | eqos_rx 1 1 0 0 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| pll_e 1 1 100000000 100000000 0 0 | <> | |
| *[ default_freq 0] | ||
| uphy_pll3 0 0 4992000000 4992000000 0 0 | ||
| *[ default_freq 0] | ||
| pllrefe_vcoout 4 4 625000000 625000000 0 0 | pllrefe_vcoout 9 9 625000000 625000000 0 0 | |
| *[ default_freq 0] | = | *[ default_freq 0] |
| eqos_tx 1 1 25000000 25000000 0 0 | <> | eqos_tx 1 1 125000000 125000000 0 0 |
| *[ default_freq 0] | = | *[ default_freq 0] |
| eqos_ptp_ref 1 1 312500000 312500000 0 0 | eqos_ptp_ref 1 1 312500000 312500000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| eqos_axi 1 1 125000000 125000000 0 0 | eqos_axi 1 1 125000000 125000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| mphy_l0_rx_ls_bit 0 0 625000000 625000000 0 0 | <> | mphy_l0_rx_ls_bit 1 1 625000000 625000000 0 0 |
| *[ default_freq 0] | = | *[ default_freq 0] |
| mphy_l0_tx_ls_3xbit 0 0 625000000 625000000 0 0 | <> | mphy_l0_tx_ls_3xbit 1 1 625000000 625000000 0 0 |
| *[ default_freq 0] | = | *[ default_freq 0] |
| mphy_l0_rx_symb 0 0 31250000 31250000 0 0 | <> | mphy_l0_rx_symb 1 1 31250000 31250000 0 0 |
| *[ default_freq 0] | = | *[ default_freq 0] |
| mphy_l0_tx_symb 0 0 10416666 10416666 0 0 | <> | mphy_l0_tx_symb 1 1 10416666 10416666 0 0 |
| *[ default_freq 0] | = | *[ default_freq 0] |
| mphy_core_pll_fixed 0 0 208333333 208333333 0 0 | <> | mphy_core_pll_fixed 3 3 208333333 208333333 0 0 |
| *[ default_freq 0] | = | *[ default_freq 0] |
| mphy_l1_rx_ana 0 0 208333333 208333333 0 0 | <> | mphy_l1_rx_ana 1 1 208333333 208333333 0 0 |
| *[ default_freq 0] | = | *[ default_freq 0] |
| mphy_l0_rx_ana 0 0 208333333 208333333 0 0 | <> | mphy_l0_rx_ana 1 1 208333333 208333333 0 0 |
| *[ default_freq 0] | = | *[ default_freq 0] |
| 32khz_out0 0 0 32768 32768 0 0 | <> | |
| *[ default_freq 0] | ||
| sor0_pad_clkout 0 0 600000000 600000000 0 0 | ||
| *[ default_freq 0] | ||
| sor2_pad_clkout 6 6 148500000 148500000 0 0 | sor2_pad_clkout 4 4 533250000 533250000 0 0 | |
| *[ default_freq 0] | = | *[ default_freq 0] |
| sor2_out 5 5 148500000 148351000 0 0 | <> | sor2_out 3 3 533250000 148351000 0 0 |
| *[ default_freq 0] | = | *[ default_freq 0] |
| pll_disphub 1 1 358400000 358400000 0 0 | <> | 32khz_out0 0 0 32768 32768 0 0 |
| *[ default_freq 0] | ||
| nvdisplayhub 2 2 18863157 18731250 0 0 | ||
| *[ default_freq 0] | ||
| pll_d4 0 0 1536000000 1536000000 0 0 | ||
| *[ default_freq 0] | ||
| pll_d3 2 2 148500000 148500000 0 0 | ||
| *[ default_freq 0] | ||
| sor2_ref 1 1 148500000 148500000 0 0 | ||
| *[ default_freq 0] | ||
| nvdisplay_p0 3 3 148500000 148500000 0 0 | ||
| *[ default_freq 0] | ||
| nvdisplay_disp 2 2 148500000 148350937 0 0 | ||
| *[ default_freq 0] | ||
| pll_d2 0 0 768000000 768000000 0 0 | ||
| *[ default_freq 0] | ||
| pll_d 0 0 1190400000 1190400000 0 0 | ||
| *[ default_freq 0] | = | *[ default_freq 0] |
| dla1_falcon 0 0 844800000 844800000 0 0 | dla1_falcon 0 0 844800000 844800000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| dla1_core 0 0 1395200000 1395200000 0 0 | dla1_core 0 0 1395200000 1395200000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| dla0_falcon 0 0 844800000 844800000 0 0 | dla0_falcon 0 0 844800000 844800000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| dla0_core 0 0 1395200000 1395200000 0 0 | dla0_core 0 0 1395200000 1395200000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| pva1_vps1 0 0 1088000000 1088000000 0 0 | pva1_vps1 0 0 1088000000 1088000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| pva1_vps0 0 0 1088000000 1088000000 0 0 | pva1_vps0 0 0 1088000000 1088000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| pva1_axi 0 0 844800000 844800000 0 0 | pva1_axi 0 0 844800000 844800000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| pva0_vps1 0 0 1088000000 1088000000 0 0 | pva0_vps1 0 0 1088000000 1088000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| pva0_vps0 0 0 1088000000 1088000000 0 0 | pva0_vps0 0 0 1088000000 1088000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| pva0_axi 0 0 844800000 844800000 0 0 | pva0_axi 0 0 844800000 844800000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| <> | osc_div 5 5 38400000 38400000 0 0 | |
| *[ default_freq 0] | ||
| pll_aon 0 0 38400000 38400000 0 0 | ||
| *[ default_freq 0] | ||
| pll_c4 0 0 781000781 781000781 0 0 | ||
| *[ default_freq 0] | ||
| sdmmc4 0 0 195250195 200000000 0 0 | ||
| *[ default_freq 0] | ||
| pllc4_vco_div2 0 0 390500390 390500390 0 0 | ||
| *[ default_freq 0] | ||
| pllc4_muxed 0 0 390500390 390500390 0 0 | ||
| *[ default_freq 0] | ||
| pllc4_out2 0 0 156200156 156200156 0 0 | ||
| *[ default_freq 0] | ||
| pllc4_out1 0 0 260333593 260333593 0 0 | ||
| *[ default_freq 0] | ||
| utmipll 2 2 38400000 38400000 0 0 | ||
| *[ default_freq 0] | ||
| utmipll_clkout480 1 1 480000000 480000000 0 0 | ||
| *[ default_freq 0] | ||
| xusb_ss 1 1 120000000 120000000 0 0 | ||
| *[ default_freq 0] | ||
| xusb_ss_superspeed 1 1 120000000 120000000 0 0 | ||
| *[ default_freq 0] | ||
| utmipll_clkout48 1 1 48000000 48000000 0 0 | ||
| *[ default_freq 0] | ||
| xusb_fs 2 2 48000000 48000000 0 0 | ||
| *[ default_freq 0] | ||
| xusb_fs_host 1 1 48000000 48000000 0 0 | ||
| *[ default_freq 0] | ||
| pll_e 1 1 100000000 100000000 0 0 | ||
| *[ default_freq 0] | ||
| uphy_pll3 0 0 4992000000 4992000000 0 0 | ||
| *[ default_freq 0] | ||
| pll_disphub 1 1 358400000 358400000 0 0 | ||
| *[ default_freq 0] | ||
| nvdisplayhub 2 2 71680000 67041412 0 0 | ||
| *[ default_freq 0] | ||
| pll_d4 0 0 1536000000 1536000000 0 0 | ||
| *[ default_freq 0] | ||
| pll_d3 2 2 533250000 533250000 0 0 | ||
| *[ default_freq 0] | ||
| sor2_ref 1 1 266625000 266625000 0 0 | ||
| *[ default_freq 0] | ||
| nvdisplay_p0 3 3 533250000 533250000 0 0 | ||
| *[ default_freq 0] | ||
| nvdisplay_disp 2 2 533250000 148350937 0 0 | ||
| *[ default_freq 0] | ||
| pll_d2 0 0 768000000 768000000 0 0 | ||
| *[ default_freq 0] | ||
| pll_d 0 0 1190400000 1190400000 0 0 | ||
| *[ default_freq 0] | ||
| pll_nvcsi 0 0 1200000000 1200000000 0 0 | pll_nvcsi 0 0 1200000000 1200000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nvcsi 0 0 400000000 400000000 0 0 | nvcsi 0 0 400000000 400000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| pll_c 0 0 204000000 204000000 0 0 | pll_c 0 0 204000000 204000000 0 0 | |
| *[ default_freq 0] | ||
| can2 0 0 102000000 102000000 0 0 | ||
| *[ default_freq 0] | ||
| can1 0 0 102000000 102000000 0 0 | ||
| *[ default_freq 0] | *[ default_freq 0] | |
| pll_a1 0 0 600000000 600000000 0 0 | pll_a1 0 0 600000000 600000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| plla1_out1 0 0 150000000 150000000 0 0 | plla1_out1 0 0 150000000 150000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| ape 0 0 150000000 150000000 0 0 | ape 0 0 150000000 150000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| apb2ape 0 0 150000000 150000000 0 0 | apb2ape 0 0 150000000 150000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| pll_a 1 1 245759960 245760000 0 0 | pll_a 1 1 270950390 270950400 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| plla_out0 1 1 49151992 49152000 0 0 | plla_out0 1 1 45158398 45158400 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| dspk2 0 0 12287998 12288000 0 0 | dspk2 0 0 11289599 12288000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| dspk1 0 0 12287998 12288000 0 0 | dspk1 0 0 11289599 12288000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| dmic4 0 0 3071999 3072000 0 0 | dmic4 0 0 3010559 3072000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| dmic3 0 0 3071999 3072000 0 0 | dmic3 0 0 3010559 3072000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| dmic2 0 0 3071999 3072000 0 0 | dmic2 0 0 3010559 3072000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| dmic1 0 0 3071999 3072000 0 0 | dmic1 0 0 3010559 3072000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2s6 0 0 2137043 1536000 0 0 | i2s6 0 0 2150399 1536000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2s5 0 0 2137043 1536000 0 0 | i2s5 0 0 2150399 1536000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2s4 0 0 2137043 1536000 0 0 | i2s4 0 0 2150399 1536000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2s3 0 0 2137043 1536000 0 0 | i2s3 0 0 2150399 1536000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2s2 0 0 2137043 1536000 0 0 | i2s2 0 0 2150399 1536000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2s1 0 0 1535999 1536000 0 0 | i2s1 0 0 1411199 1411200 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| aud_mclk 1 1 12287998 12288000 0 0 | aud_mclk 1 1 11289599 11289600 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| clk_32k 0 0 32768 32768 0 0 | = | clk_32k 0 0 32768 32768 0 0 |
| *[ default_freq 0] | *[ default_freq 0] | |
| emc 0 0 408000000 408000000 0 0 | <> | emc 0 0 665600000 600000000 0 0 |
| *[ default_freq 0] | = | *[ default_freq 0] |
| pll_p 2 2 408000000 408000000 0 0 | pll_p 2 2 408000000 408000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| -+ | pllp_out5 0 0 408000000 408000000 0 0 | |
| *[ default_freq 0] | ||
| gpu_pwr 0 0 408000000 408000000 0 0 | ||
| *[ default_freq 0] | ||
| nafll_gpu 0 0 0 0 0 0 | ||
| *[ default_freq 0] | ||
| pllp_div17 1 1 24000000 24000000 0 0 | = | pllp_div17 1 1 24000000 24000000 0 0 |
| *[ default_freq 0] | *[ default_freq 0] | |
| sor_safe 5 5 24000000 24000000 0 0 | <> | sor_safe 3 3 24000000 24000000 0 0 |
| *[ default_freq 0] | = | *[ default_freq 0] |
| sor0_out 0 0 24000000 24000000 0 0 | sor0_out 0 0 24000000 24000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| dpaux 0 0 24000000 24000000 0 0 | dpaux 0 0 24000000 24000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| dpaux2 0 0 24000000 24000000 0 0 | dpaux2 0 0 24000000 24000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| dpaux3 0 0 24000000 24000000 0 0 | dpaux3 0 0 24000000 24000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| pllp_out0 15 15 408000000 408000000 0 0 | <> | pllp_out0 16 16 408000000 408000000 0 0 |
| *[ default_freq 0] | = | *[ default_freq 0] |
| i2c9 1 1 136000000 136000000 0 0 | i2c9 1 1 136000000 136000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| ahub 0 0 81600000 81600000 0 0 | ahub 0 0 81600000 81600000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| sdmmc1 0 0 3187500 400000 0 0 | sdmmc1 0 0 3187500 400000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| sdmmc_legacy_tm 0 0 12000000 12000000 0 0 | sdmmc_legacy_tm 0 0 12000000 12000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| xusb_core_dev 0 0 102000000 102000000 0 0 | xusb_core_dev 0 0 102000000 102000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| xusb_falcon 3 3 408000000 408000000 0 0 | xusb_falcon 3 3 408000000 408000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| xusb_falcon_ss 1 1 408000000 408000000 0 0 | xusb_falcon_ss 1 1 408000000 408000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| xusb_falcon_host 1 1 408000000 408000000 0 0 | xusb_falcon_host 1 1 408000000 408000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| xusb_core_mux 3 3 102000000 102000000 0 0 | xusb_core_mux 3 3 102000000 102000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| xusb_core_host 1 1 102000000 102000000 0 0 | xusb_core_host 1 1 102000000 102000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| xusb_core_ss 1 1 102000000 102000000 0 0 | xusb_core_ss 1 1 102000000 102000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| axi_cbb 1 1 204000000 204000000 0 0 | axi_cbb 1 1 204000000 204000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| -+ | spi2 0 0 68000000 68000000 0 0 | |
| *[ default_freq 0] | ||
| spi1 0 0 68000000 68000000 0 0 | = | spi1 0 0 68000000 68000000 0 0 |
| *[ default_freq 0] | *[ default_freq 0] | |
| ufshc 2 2 204000000 204000000 0 0 | <> | ufshc 1 1 204000000 204000000 0 0 |
| *[ default_freq 0] | = | *[ default_freq 0] |
| uartg 0 0 408000000 38400000 0 0 | uartg 0 0 408000000 38400000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| uarte 0 0 204000000 204000000 0 0 | uarte 0 0 204000000 204000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| uartb 0 0 204000000 19200000 0 0 | uartb 0 0 204000000 19200000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| uarta 0 0 204000000 204000000 0 0 | uarta 0 0 204000000 204000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| hda2codec_2x 2 2 48000000 48000000 0 0 | hda2codec_2x 2 2 48000000 48000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| hda 2 2 102000000 102000000 0 0 | hda 2 2 102000000 102000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| vi_const 0 0 408000000 408000000 0 0 | vi_const 0 0 408000000 408000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nvcsilp 0 0 204000000 204000000 0 0 | nvcsilp 0 0 204000000 204000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| pwm8 0 0 408000000 408000000 0 0 | pwm8 0 0 408000000 408000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| pwm5 0 0 408000000 408000000 0 0 | pwm5 0 0 408000000 408000000 0 0 | |
| -+ | *[ default_freq 0] | |
| pwm4 1 1 5666666 5646848 0 0 | ||
| *[ default_freq 0] | = | *[ default_freq 0] |
| pwm1 0 0 408000000 408000000 0 0 | pwm1 0 0 408000000 408000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| host1x 1 1 204000000 204000000 0 0 | host1x 1 1 204000000 204000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| uart_fst_mipi_cal 0 0 68000000 68000000 0 0 | uart_fst_mipi_cal 0 0 68000000 68000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2c8 1 1 136000000 146400000 0 0 | i2c8 1 1 136000000 146400000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2c7 1 1 136000000 136000000 0 0 | i2c7 1 1 136000000 136000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2c6 1 1 136000000 136000000 0 0 | i2c6 1 1 136000000 136000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2c4 1 1 136000000 136000000 0 0 | i2c4 1 1 136000000 136000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2c3 1 1 136000000 146400000 0 0 | i2c3 1 1 136000000 146400000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2c2 1 1 136000000 136000000 0 0 | i2c2 1 1 136000000 136000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| i2c1 1 1 136000000 146400000 0 0 | i2c1 1 1 136000000 146400000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| clk_m 9 9 19200000 19200000 0 0 | clk_m 9 9 19200000 19200000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| rce_cpu_nic 2 2 19200000 19200000 0 0 | rce_cpu_nic 2 2 19200000 19200000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| rce_nic 1 1 4800000 19200000 0 0 | rce_nic 1 1 4800000 19200000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| ufsdev_ref 2 2 19200000 19200000 0 0 | <> | sor0_ref 0 0 19200000 19200000 0 0 |
| *[ default_freq 0] | = | *[ default_freq 0] |
| cec 1 1 19200000 19200000 0 0 | <> | ufsdev_ref 1 1 19200000 19200000 0 0 |
| *[ default_freq 0] | ||
| sor0_ref 0 0 19200000 19200000 0 0 | ||
| *[ default_freq 0] | = | *[ default_freq 0] |
| hda2hdmicodec 2 2 19200000 19200000 0 0 | hda2hdmicodec 2 2 19200000 19200000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nvdisplay_p3 1 1 19200000 19200000 0 0 | nvdisplay_p3 1 1 19200000 19200000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nvdisplay_p2 1 1 19200000 19200000 0 0 | nvdisplay_p2 1 1 19200000 19200000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nvdisplay_p1 2 2 19200000 19200000 0 0 | nvdisplay_p1 2 2 19200000 19200000 0 0 | |
| -+ | *[ default_freq 0] | |
| cec 1 1 19200000 19200000 0 0 | ||
| *[ default_freq 0] | = | *[ default_freq 0] |
| kfuse 0 0 19200000 19200000 0 0 | kfuse 0 0 19200000 19200000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| tach 1 1 1010526 1010526 0 0 | tach 1 1 1010526 1010526 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| actmon 2 2 19200000 19200000 0 0 | actmon 2 2 19200000 19200000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| mipi_cal 0 0 19200000 19200000 0 0 | mipi_cal 0 0 19200000 19200000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| osc 2 2 38400000 38400000 0 0 | osc 2 2 38400000 38400000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nafll_isp 0 0 1011200000 1011200000 0 0 | nafll_isp 0 0 1011200000 1011200000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| isp 0 0 1190400000 1190400000 0 0 | isp 0 0 1190400000 1190400000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nafll_pva_core 0 0 115200000 844800000 0 0 | nafll_pva_core 0 0 115200000 844800000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nafll_pva_vps 0 0 115200000 1088000000 0 0 | nafll_pva_vps 0 0 115200000 1088000000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nafll_dla_falcon 0 0 115200000 844800000 0 0 | nafll_dla_falcon 0 0 115200000 844800000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nafll_dla 0 0 115200000 1395200000 0 0 | nafll_dla 0 0 115200000 1395200000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| can2 0 0 38400000 38400000 0 0 | +- | |
| *[ default_freq 0] | ||
| can1 0 0 38400000 38400000 0 0 | ||
| *[ default_freq 0] | ||
| nafll_cvnas 0 0 115200000 1356800000 0 0 | = | nafll_cvnas 0 0 115200000 1356800000 0 0 |
| *[ default_freq 0] | *[ default_freq 0] | |
| cvnas 0 0 115200000 1356800000 0 0 | cvnas 0 0 115200000 1356800000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nafll_rce 0 0 601600000 601600000 0 0 | nafll_rce 0 0 601600000 601600000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nafll_se 0 0 0 0 0 0 | nafll_se 0 0 0 0 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| se 0 0 601600000 601600000 0 0 | se 0 0 601600000 601600000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nafll_cluster0 0 0 998400000 998400000 0 0 | +- | |
| *[ default_freq 0] | ||
| spi2 0 0 38400000 38400000 0 0 | ||
| *[ default_freq 0] | ||
| mphy_flsm 0 0 38400000 38400000 0 0 | = | mphy_flsm 0 0 38400000 38400000 0 0 |
| *[ default_freq 0] | *[ default_freq 0] | |
| mphy_tx_1mhz_ref 0 0 1010526 1010526 0 0 | <> | mphy_tx_1mhz_ref 1 1 1010526 1010526 0 0 |
| *[ default_freq 0] | = | *[ default_freq 0] |
| nafll_vi 0 0 665600000 665600000 0 0 | nafll_vi 0 0 665600000 665600000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| vi 0 0 998400000 998400000 0 0 | vi 0 0 998400000 998400000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nafll_nvenc1 0 0 115200000 115200000 0 0 | nafll_nvenc1 0 0 115200000 115200000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nvenc1 0 0 1075200000 1075200000 0 0 | nvenc1 0 0 1075200000 1075200000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nafll_nvenc 0 0 115200000 115200000 0 0 | nafll_nvenc 0 0 115200000 115200000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nvenc 0 0 1075200000 1075200000 0 0 | nvenc 0 0 1075200000 1075200000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nafll_nvjpg 0 0 0 0 0 0 | nafll_nvjpg 0 0 0 0 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nvjpg 0 0 716800000 716800000 0 0 | nvjpg 0 0 716800000 716800000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nafll_vic 0 0 115200000 115200000 0 0 | nafll_vic 0 0 115200000 115200000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| vic 0 0 115200000 115200000 0 0 | vic 0 0 115200000 115200000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nafll_nvdec1 0 0 0 0 0 0 | nafll_nvdec1 0 0 0 0 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nvdec1 0 0 1190400000 1190400000 0 0 | nvdec1 0 0 1190400000 1190400000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nafll_nvdec 0 0 0 0 0 0 | nafll_nvdec 0 0 0 0 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nvdec 0 0 1190400000 1190400000 0 0 | nvdec 0 0 1190400000 1190400000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nafll_tsecb 0 0 0 0 0 0 | nafll_tsecb 0 0 0 0 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| tsecb 0 0 1036800000 1036800000 0 0 | tsecb 0 0 1036800000 1036800000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| nafll_tsec 0 0 0 0 0 0 | nafll_tsec 0 0 0 0 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| tsec 0 0 1036800000 1036800000 0 0 | tsec 0 0 1036800000 1036800000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| pwm4 1 1 6400000 5646848 0 0 | +- | |
| *[ default_freq 0] | ||
| usb2_trk 0 0 9600000 9600000 0 0 | = | usb2_trk 0 0 9600000 9600000 0 0 |
| *[ default_freq 0] | *[ default_freq 0] | |
| fuse_serial 1 1 38400000 38400000 0 0 | fuse_serial 1 1 38400000 38400000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| fuse 1 1 38400000 38400000 0 0 | fuse 1 1 38400000 38400000 0 0 | |
| *[ default_freq 0] | *[ default_freq 0] | |
| root@nvidia-desktop:/home/nvidia# cat /sys/kernel/debug/regmap/7-000a/registers | <> | root@stevie:/home/nvidia# cat /sys/kernel/debug/regmap/7-000a/registers |
| 000: a011 | = | 000: a011 |
| 002: 0060 | 002: 0060 | |
| 004: 0008 | <> | 004: 0004 |
| 006: 0130 | = | 006: 0130 |
| 00a: 0010 | 00a: 0010 | |
| 00e: 020c | 00e: 020c | |
| 010: 3c3c | 010: 3c3c | |
| 014: 015f | 014: 015f | |
| 020: 0000 | 020: 0000 | |
| 022: 1818 | 022: 1818 | |
| 024: 0022 | <> | 024: 0132 |
| 026: 0000 | = | 026: 0000 |
| 028: 0041 | 028: 0041 | |
| 02a: 0200 | 02a: 0200 | |
| 02c: 0304 | 02c: 0304 | |
| 02e: 0f0f | 02e: 0f0f | |
| 030: 4860 | 030: 4860 | |
| 032: 5000 | 032: 5000 | |
| 034: 0800 | 034: 0800 | |
| 036: 0017 | 036: 0017 | |
| 03a: 0000 | 03a: 0000 | |
| 03c: 0000 | 03c: 0000 | |
| 100: 0000 | 100: 0000 | |
| 102: 0000 | 102: 0000 | |
| 104: 0040 | 104: 0040 | |
| 106: 051f | 106: 051f | |
| 108: 0000 | 108: 0000 | |
| 10a: 0040 | 10a: 0040 | |
| 10c: 0000 | 10c: 0000 | |
| 10e: 0000 | 10e: 0000 | |
| 110: 0000 | 110: 0000 | |
| 116: 002f | 116: 002f | |
| 118: 002f | 118: 002f | |
| 11a: 002f | 11a: 002f | |
| 11c: 002f | 11c: 002f | |
| 11e: 002f | 11e: 002f | |
| 120: 8000 | 120: 8000 | |
| 122: 0000 | 122: 0000 | |
| 124: 0510 | 124: 0510 | |
| 126: 1473 | 126: 1473 | |
| 128: 0028 | 128: 0028 | |
| 12a: 0050 | 12a: 0050 | |
| 12c: 0000 | 12c: 0000 | |
| 12e: 0000 | 12e: 0000 | |
| 130: 0000 | 130: 0000 | |
| 132: 0000 | 132: 0000 | |
| 134: 0000 | 134: 0000 | |
| 136: 0000 | 136: 0000 | |
| 138: 0000 | 138: 0000 | |
| 13a: 0000 | 13a: 0000 | |
| root@nvidia-desktop:/home/nvidia# | <> | root@stevie:/home/nvidia# |