[ 8.644552] dp lt: state 0 (Reset), pending_lt_evt 0 [ 8.645736] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 8.645873] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 8.645876] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 8.646107] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 8.646114] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 8.646119] dp lt: tx_pu: 0x20 [ 8.646704] tegradc tegradc.1: dp: irq event received [ 8.647004] dp lt: CR not done [ 8.647226] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 8.647228] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 8.647229] dp lt: CR retry [ 8.647231] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 8.647233] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 8.647243] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 8.647250] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 8.647255] dp lt: tx_pu: 0x30 [ 8.647930] dp lt: CR not done [ 8.648153] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 8.648154] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 8.648155] dp lt: CR retry [ 8.648157] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 8.648160] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 8.648170] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 8.648177] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 8.648181] dp lt: tx_pu: 0x30 [ 8.648856] dp lt: CR done [ 8.648858] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 8.648860] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 8.650778] dp lt: CE done [ 8.650780] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 8.725967] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 8.725969] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 8.725971] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 8.767737] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 8.767745] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 8.767749] dp lt: tx_pu: 0x30 [ 8.768959] tegradc tegradc.1: dp: irq event received [ 8.771422] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 8.771444] dp lt: fast link training fail [ 8.771446] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 8.771449] dp lt: state 0 (Reset), pending_lt_evt 0 [ 8.772633] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 8.772770] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 8.772772] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 8.773002] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 8.773009] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 8.773013] dp lt: tx_pu: 0x20 [ 8.773596] tegradc tegradc.1: dp: irq event received [ 8.773898] dp lt: CR not done [ 8.774131] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 8.774133] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 8.774134] dp lt: CR retry [ 8.774136] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 8.774139] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 8.774148] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 8.774155] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 8.774159] dp lt: tx_pu: 0x30 [ 8.774835] dp lt: CR not done [ 8.775058] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 8.775059] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 8.775060] dp lt: CR retry [ 8.775062] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 8.775064] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 8.775074] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 8.775081] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 8.775085] dp lt: tx_pu: 0x30 [ 8.775761] dp lt: CR done [ 8.775763] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 8.775766] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 8.777680] dp lt: CE done [ 8.777683] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 8.853974] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 8.853976] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 8.853978] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 8.894639] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 8.894646] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 8.894651] dp lt: tx_pu: 0x30 [ 8.895861] tegradc tegradc.1: dp: irq event received [ 8.898324] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 8.898346] dp lt: fast link training fail [ 8.898348] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 8.898351] dp lt: state 0 (Reset), pending_lt_evt 0 [ 8.899536] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 8.899674] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 8.899676] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 8.899907] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 8.899914] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 8.899918] dp lt: tx_pu: 0x20 [ 8.900504] tegradc tegradc.1: dp: irq event received [ 8.900803] dp lt: CR not done [ 8.901025] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 8.901027] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 8.901028] dp lt: CR retry [ 8.901030] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 8.901033] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 8.901042] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 8.901050] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 8.901054] dp lt: tx_pu: 0x30 [ 8.901730] dp lt: CR not done [ 8.901955] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 8.901956] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 8.901957] dp lt: CR retry [ 8.901959] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 8.901962] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 8.901971] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 8.901978] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 8.901982] dp lt: tx_pu: 0x30 [ 8.902658] dp lt: CR done [ 8.902660] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 8.902662] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 8.904576] dp lt: CE done [ 8.904579] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 8.977968] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 8.977970] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 8.977973] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 9.021527] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.021535] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.021539] dp lt: tx_pu: 0x30 [ 9.022750] tegradc tegradc.1: dp: irq event received [ 9.025211] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 9.025233] dp lt: fast link training fail [ 9.025235] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 9.025238] dp lt: state 0 (Reset), pending_lt_evt 0 [ 9.026424] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 9.026561] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 9.026564] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 9.026794] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 9.026802] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 9.026806] dp lt: tx_pu: 0x20 [ 9.027390] tegradc tegradc.1: dp: irq event received [ 9.027691] dp lt: CR not done [ 9.027914] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.027916] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.027917] dp lt: CR retry [ 9.027919] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 9.027921] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 9.027931] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.027938] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.027943] dp lt: tx_pu: 0x30 [ 9.028618] dp lt: CR not done [ 9.028841] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.028842] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.028843] dp lt: CR retry [ 9.028845] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 9.028848] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 9.028858] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.028865] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.028869] dp lt: tx_pu: 0x30 [ 9.029543] dp lt: CR done [ 9.029545] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 9.029548] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 9.031467] dp lt: CE done [ 9.031469] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 9.105967] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 9.105969] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 9.105972] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 9.148429] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.148437] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.148441] dp lt: tx_pu: 0x30 [ 9.149642] tegradc tegradc.1: dp: irq event received [ 9.152106] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 9.152128] dp lt: fast link training fail [ 9.152130] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 9.152133] dp lt: state 0 (Reset), pending_lt_evt 0 [ 9.153318] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 9.153454] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 9.153456] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 9.153687] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 9.153694] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 9.153698] dp lt: tx_pu: 0x20 [ 9.154285] tegradc tegradc.1: dp: irq event received [ 9.154585] dp lt: CR not done [ 9.154808] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.154810] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.154811] dp lt: CR retry [ 9.154813] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 9.154816] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 9.154825] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.154832] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.154836] dp lt: tx_pu: 0x30 [ 9.155512] dp lt: CR not done [ 9.155734] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.155736] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.155737] dp lt: CR retry [ 9.155739] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 9.155741] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 9.155751] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.155758] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.155762] dp lt: tx_pu: 0x30 [ 9.156438] dp lt: CR done [ 9.156440] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 9.156442] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 9.158358] dp lt: CE done [ 9.158361] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 9.229968] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 9.229971] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 9.229973] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 9.275314] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.275322] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.275326] dp lt: tx_pu: 0x30 [ 9.276537] tegradc tegradc.1: dp: irq event received [ 9.279000] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 9.279022] dp lt: fast link training fail [ 9.279025] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 9.279028] dp lt: state 0 (Reset), pending_lt_evt 0 [ 9.280212] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 9.280348] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 9.280351] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 9.280581] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 9.280588] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 9.280592] dp lt: tx_pu: 0x20 [ 9.281177] tegradc tegradc.1: dp: irq event received [ 9.281477] dp lt: CR not done [ 9.281700] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.281702] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.281703] dp lt: CR retry [ 9.281705] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 9.281708] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 9.281717] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.281725] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.281729] dp lt: tx_pu: 0x30 [ 9.282406] dp lt: CR not done [ 9.282629] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.282631] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.282632] dp lt: CR retry [ 9.282634] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 9.282637] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 9.282646] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.282653] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.282657] dp lt: tx_pu: 0x30 [ 9.283332] dp lt: CR done [ 9.283334] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 9.283337] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 9.285252] dp lt: CE done [ 9.285254] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 9.357967] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 9.357969] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 9.357971] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 9.402213] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.402221] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.402225] dp lt: tx_pu: 0x30 [ 9.403435] tegradc tegradc.1: dp: irq event received [ 9.405897] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 9.405929] dp lt: fast link training fail [ 9.405931] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 9.405934] dp lt: state 0 (Reset), pending_lt_evt 0 [ 9.407120] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 9.407257] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 9.407259] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 9.407490] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 9.407497] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 9.407501] dp lt: tx_pu: 0x20 [ 9.408090] tegradc tegradc.1: dp: irq event received [ 9.408386] dp lt: CR not done [ 9.408609] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.408610] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.408611] dp lt: CR retry [ 9.408613] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 9.408616] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 9.408626] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.408633] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.408637] dp lt: tx_pu: 0x30 [ 9.409312] dp lt: CR not done [ 9.409535] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.409537] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.409538] dp lt: CR retry [ 9.409540] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 9.409542] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 9.409552] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.409560] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.409564] dp lt: tx_pu: 0x30 [ 9.410242] dp lt: CR done [ 9.410244] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 9.410247] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 9.412162] dp lt: CE done [ 9.412164] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 9.485967] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 9.485969] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 9.485971] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 9.529127] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.529134] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.529139] dp lt: tx_pu: 0x30 [ 9.530351] tegradc tegradc.1: dp: irq event received [ 9.532812] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 9.532835] dp lt: fast link training fail [ 9.532837] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 9.532840] dp lt: state 0 (Reset), pending_lt_evt 0 [ 9.534026] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 9.534162] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 9.534165] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 9.534396] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 9.534404] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 9.534408] dp lt: tx_pu: 0x20 [ 9.534992] tegradc tegradc.1: dp: irq event received [ 9.535293] dp lt: CR not done [ 9.535517] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.535519] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.535520] dp lt: CR retry [ 9.535522] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 9.535524] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 9.535534] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.535542] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.535546] dp lt: tx_pu: 0x30 [ 9.536222] dp lt: CR not done [ 9.536444] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.536446] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.536447] dp lt: CR retry [ 9.536449] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 9.536451] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 9.536461] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.536468] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.536472] dp lt: tx_pu: 0x30 [ 9.537147] dp lt: CR done [ 9.537149] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 9.537152] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 9.539066] dp lt: CE done [ 9.539069] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 9.617971] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 9.617973] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 9.617975] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 9.656015] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.656023] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.656027] dp lt: tx_pu: 0x30 [ 9.657236] tegradc tegradc.1: dp: irq event received [ 9.659698] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 9.659720] dp lt: fast link training fail [ 9.659723] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 9.659726] dp lt: state 0 (Reset), pending_lt_evt 0 [ 9.660910] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 9.661047] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 9.661050] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 9.661280] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 9.661288] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 9.661292] dp lt: tx_pu: 0x20 [ 9.661880] tegradc tegradc.1: dp: irq event received [ 9.662179] dp lt: CR not done [ 9.662402] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.662404] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.662405] dp lt: CR retry [ 9.662407] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 9.662410] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 9.662420] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.662427] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.662431] dp lt: tx_pu: 0x30 [ 9.663107] dp lt: CR not done [ 9.663330] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.663331] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.663332] dp lt: CR retry [ 9.663334] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 9.663337] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 9.663346] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.663353] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.663357] dp lt: tx_pu: 0x30 [ 9.664034] dp lt: CR done [ 9.664036] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 9.664039] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 9.665963] dp lt: CE done [ 9.665966] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 9.737967] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 9.737970] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 9.737972] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 9.782914] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.782922] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.782927] dp lt: tx_pu: 0x30 [ 9.784137] tegradc tegradc.1: dp: irq event received [ 9.786599] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 9.786621] dp lt: fast link training fail [ 9.786624] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 9.786627] dp lt: state 0 (Reset), pending_lt_evt 0 [ 9.787811] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 9.787948] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 9.787951] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 9.788181] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 9.788188] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 9.788193] dp lt: tx_pu: 0x20 [ 9.788778] tegradc tegradc.1: dp: irq event received [ 9.789076] dp lt: CR not done [ 9.789299] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.789301] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.789302] dp lt: CR retry [ 9.789304] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 9.789307] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 9.789317] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.789324] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.789328] dp lt: tx_pu: 0x30 [ 9.790005] dp lt: CR not done [ 9.790228] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.790230] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.790231] dp lt: CR retry [ 9.790233] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 9.790235] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 9.790245] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.790253] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.790257] dp lt: tx_pu: 0x30 [ 9.790932] dp lt: CR done [ 9.790934] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 9.790937] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 9.792852] dp lt: CE done [ 9.792855] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 9.865968] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 9.865970] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 9.865973] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 9.909815] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.909822] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.909826] dp lt: tx_pu: 0x30 [ 9.911039] tegradc tegradc.1: dp: irq event received [ 9.913500] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 9.913522] dp lt: fast link training fail [ 9.913524] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 9.913527] dp lt: state 0 (Reset), pending_lt_evt 0 [ 9.914714] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 9.914851] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 9.914854] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 9.915084] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 9.915091] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 9.915096] dp lt: tx_pu: 0x20 [ 9.915678] tegradc tegradc.1: dp: irq event received [ 9.915981] dp lt: CR not done [ 9.916204] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.916205] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.916206] dp lt: CR retry [ 9.916208] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 9.916211] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 9.916221] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.916228] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.916232] dp lt: tx_pu: 0x30 [ 9.916907] dp lt: CR not done [ 9.917129] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.917131] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.917132] dp lt: CR retry [ 9.917134] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 9.917136] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 9.917146] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 9.917153] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 9.917157] dp lt: tx_pu: 0x30 [ 9.917833] dp lt: CR done [ 9.917836] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 9.917838] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 9.919753] dp lt: CE done [ 9.919756] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 9.993967] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 9.993969] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 9.993972] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 10.036703] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.036711] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.036715] dp lt: tx_pu: 0x30 [ 10.037915] tegradc tegradc.1: dp: irq event received [ 10.040375] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 10.040397] dp lt: fast link training fail [ 10.040400] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 10.040403] dp lt: state 0 (Reset), pending_lt_evt 0 [ 10.041587] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 10.041724] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 10.041727] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 10.041960] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 10.041967] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 10.041972] dp lt: tx_pu: 0x20 [ 10.042552] tegradc tegradc.1: dp: irq event received [ 10.042856] dp lt: CR not done [ 10.043079] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.043081] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.043082] dp lt: CR retry [ 10.043084] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 10.043087] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 10.043097] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.043104] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.043108] dp lt: tx_pu: 0x30 [ 10.043782] dp lt: CR not done [ 10.044005] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.044007] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.044008] dp lt: CR retry [ 10.044010] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 10.044012] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 10.044022] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.044029] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.044033] dp lt: tx_pu: 0x30 [ 10.044708] dp lt: CR done [ 10.044710] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 10.044713] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 10.046629] dp lt: CE done [ 10.046631] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 10.117974] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 10.117976] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 10.117978] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 10.163592] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.163600] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.163604] dp lt: tx_pu: 0x30 [ 10.164815] tegradc tegradc.1: dp: irq event received [ 10.167276] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 10.167298] dp lt: fast link training fail [ 10.167300] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 10.167303] dp lt: state 0 (Reset), pending_lt_evt 0 [ 10.168487] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 10.168624] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 10.168627] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 10.168857] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 10.168864] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 10.168868] dp lt: tx_pu: 0x20 [ 10.169450] tegradc tegradc.1: dp: irq event received [ 10.169752] dp lt: CR not done [ 10.169978] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.169979] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.169980] dp lt: CR retry [ 10.169982] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 10.169985] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 10.169995] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.170002] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.170006] dp lt: tx_pu: 0x30 [ 10.170682] dp lt: CR not done [ 10.170905] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.170906] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.170907] dp lt: CR retry [ 10.170909] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 10.170911] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 10.170922] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.170929] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.170933] dp lt: tx_pu: 0x30 [ 10.171609] dp lt: CR done [ 10.171611] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 10.171614] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 10.173528] dp lt: CE done [ 10.173530] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 10.249972] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 10.249974] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 10.249977] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 10.290479] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.290487] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.290492] dp lt: tx_pu: 0x30 [ 10.291692] tegradc tegradc.1: dp: irq event received [ 10.294156] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 10.294178] dp lt: fast link training fail [ 10.294181] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 10.294184] dp lt: state 0 (Reset), pending_lt_evt 0 [ 10.295367] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 10.295504] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 10.295507] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 10.295737] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 10.295745] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 10.295749] dp lt: tx_pu: 0x20 [ 10.296330] tegradc tegradc.1: dp: irq event received [ 10.296634] dp lt: CR not done [ 10.296857] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.296859] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.296860] dp lt: CR retry [ 10.296862] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 10.296865] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 10.296875] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.296882] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.296886] dp lt: tx_pu: 0x30 [ 10.297562] dp lt: CR not done [ 10.297784] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.297786] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.297787] dp lt: CR retry [ 10.297789] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 10.297792] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 10.297801] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.297809] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.297813] dp lt: tx_pu: 0x30 [ 10.298490] dp lt: CR done [ 10.298492] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 10.298495] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 10.300410] dp lt: CE done [ 10.300412] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 10.373967] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 10.373970] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 10.373972] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 10.417367] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.417375] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.417379] dp lt: tx_pu: 0x30 [ 10.418592] tegradc tegradc.1: dp: irq event received [ 10.421055] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 10.421078] dp lt: fast link training fail [ 10.421080] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 10.421083] dp lt: state 0 (Reset), pending_lt_evt 0 [ 10.422269] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 10.422406] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 10.422408] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 10.422639] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 10.422647] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 10.422651] dp lt: tx_pu: 0x20 [ 10.423327] dp lt: CR not done [ 10.423549] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.423551] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.423552] dp lt: CR retry [ 10.423554] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 10.423557] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 10.423566] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.423574] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.423578] dp lt: tx_pu: 0x30 [ 10.424254] dp lt: CR not done [ 10.424476] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.424478] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.424479] dp lt: CR retry [ 10.424480] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 10.424483] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 10.424493] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.424500] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.424504] dp lt: tx_pu: 0x30 [ 10.425179] dp lt: CR done [ 10.425183] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 10.425186] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 10.427104] dp lt: CE done [ 10.427107] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 10.497970] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 10.497973] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 10.497975] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 10.544057] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.544064] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.544069] dp lt: tx_pu: 0x30 [ 10.545278] tegradc tegradc.1: dp: irq event received [ 10.547740] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 10.547762] dp lt: fast link training fail [ 10.547764] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 10.547768] dp lt: state 0 (Reset), pending_lt_evt 0 [ 10.548951] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 10.549088] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 10.549091] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 10.549320] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 10.549330] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 10.549334] dp lt: tx_pu: 0x20 [ 10.549918] tegradc tegradc.1: dp: irq event received [ 10.550219] dp lt: CR not done [ 10.550442] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.550443] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.550444] dp lt: CR retry [ 10.550446] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 10.550449] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 10.550459] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.550466] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.550470] dp lt: tx_pu: 0x30 [ 10.551145] dp lt: CR not done [ 10.551368] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.551369] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.551370] dp lt: CR retry [ 10.551372] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 10.551375] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 10.551384] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.551392] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.551396] dp lt: tx_pu: 0x30 [ 10.552072] dp lt: CR done [ 10.552074] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 10.552077] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 10.553990] dp lt: CE done [ 10.553993] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 10.625975] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 10.625977] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 10.625980] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 10.670951] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.670958] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.670963] dp lt: tx_pu: 0x30 [ 10.672173] tegradc tegradc.1: dp: irq event received [ 10.674637] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 10.674659] dp lt: fast link training fail [ 10.674662] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 10.674665] dp lt: state 0 (Reset), pending_lt_evt 0 [ 10.675849] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 10.675985] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 10.675988] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 10.676218] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 10.676225] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 10.676230] dp lt: tx_pu: 0x20 [ 10.676816] tegradc tegradc.1: dp: irq event received [ 10.677115] dp lt: CR not done [ 10.677338] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.677339] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.677340] dp lt: CR retry [ 10.677342] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 10.677345] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 10.677355] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.677362] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.677366] dp lt: tx_pu: 0x30 [ 10.678044] dp lt: CR not done [ 10.678267] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.678268] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.678269] dp lt: CR retry [ 10.678271] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 10.678274] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 10.678283] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.678291] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.678295] dp lt: tx_pu: 0x30 [ 10.678970] dp lt: CR done [ 10.678972] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 10.678975] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 10.680889] dp lt: CE done [ 10.680891] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 10.757971] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 10.757973] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 10.757976] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 10.797846] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.797854] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.797858] dp lt: tx_pu: 0x30 [ 10.799077] tegradc tegradc.1: dp: irq event received [ 10.801539] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 10.801561] dp lt: fast link training fail [ 10.801563] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 10.801566] dp lt: state 0 (Reset), pending_lt_evt 0 [ 10.802751] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 10.802888] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 10.802891] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 10.803122] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 10.803129] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 10.803134] dp lt: tx_pu: 0x20 [ 10.803719] tegradc tegradc.1: dp: irq event received [ 10.804019] dp lt: CR not done [ 10.804242] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.804244] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.804245] dp lt: CR retry [ 10.804247] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 10.804250] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 10.804260] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.804267] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.804271] dp lt: tx_pu: 0x30 [ 10.804946] dp lt: CR not done [ 10.805169] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.805171] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.805172] dp lt: CR retry [ 10.805173] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 10.805176] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 10.805185] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.805193] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.805197] dp lt: tx_pu: 0x30 [ 10.805872] dp lt: CR done [ 10.805874] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 10.805877] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 10.807793] dp lt: CE done [ 10.807795] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 10.881967] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 10.881969] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 10.881971] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 10.924744] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.924752] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.924756] dp lt: tx_pu: 0x30 [ 10.925967] tegradc tegradc.1: dp: irq event received [ 10.928428] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 10.928450] dp lt: fast link training fail [ 10.928453] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 10.928456] dp lt: state 0 (Reset), pending_lt_evt 0 [ 10.929640] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 10.929776] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 10.929779] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 10.930012] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 10.930020] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 10.930024] dp lt: tx_pu: 0x20 [ 10.930603] tegradc tegradc.1: dp: irq event received [ 10.930909] dp lt: CR not done [ 10.931132] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.931134] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.931135] dp lt: CR retry [ 10.931137] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 10.931140] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 10.931150] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.931157] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.931161] dp lt: tx_pu: 0x30 [ 10.931836] dp lt: CR not done [ 10.932058] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.932060] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.932061] dp lt: CR retry [ 10.932063] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 10.932065] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 10.932075] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 10.932082] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 10.932086] dp lt: tx_pu: 0x30 [ 10.932762] dp lt: CR done [ 10.932764] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 10.932767] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 10.934688] dp lt: CE done [ 10.934690] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 11.013971] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 11.013973] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 11.013976] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 11.051644] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.051651] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.051656] dp lt: tx_pu: 0x30 [ 11.052864] tegradc tegradc.1: dp: irq event received [ 11.055326] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 11.055349] dp lt: fast link training fail [ 11.055351] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 11.055354] dp lt: state 0 (Reset), pending_lt_evt 0 [ 11.056537] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 11.056674] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 11.056677] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 11.056907] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 11.056914] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 11.056919] dp lt: tx_pu: 0x20 [ 11.057505] tegradc tegradc.1: dp: irq event received [ 11.057804] dp lt: CR not done [ 11.058030] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.058031] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.058032] dp lt: CR retry [ 11.058034] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 11.058037] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 11.058047] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.058054] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.058058] dp lt: tx_pu: 0x30 [ 11.058734] dp lt: CR not done [ 11.058957] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.058958] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.058959] dp lt: CR retry [ 11.058961] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 11.058964] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 11.058973] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.058980] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.058984] dp lt: tx_pu: 0x30 [ 11.059660] dp lt: CR done [ 11.059662] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 11.059665] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 11.061579] dp lt: CE done [ 11.061582] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 11.121976] tegra-xusb 70090000.xusb: entering ELPG [ 11.122978] tegra-pmc: PMC tegra_pmc_utmi_phy_enable_sleepwalk : port 1, speed 0 [ 11.123164] tegra-pmc: PMC tegra_pmc_utmi_phy_enable_sleepwalk : port 2, speed 0 [ 11.124703] tegra-xusb 70090000.xusb: entering ELPG done [ 11.137971] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 11.137973] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 11.137976] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 11.178528] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.178536] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.178541] dp lt: tx_pu: 0x30 [ 11.179751] tegradc tegradc.1: dp: irq event received [ 11.182217] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 11.182240] dp lt: fast link training fail [ 11.182242] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 11.182245] dp lt: state 0 (Reset), pending_lt_evt 0 [ 11.183429] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 11.183566] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 11.183569] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 11.183799] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 11.183806] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 11.183810] dp lt: tx_pu: 0x20 [ 11.184398] tegradc tegradc.1: dp: irq event received [ 11.184695] dp lt: CR not done [ 11.184918] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.184920] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.184921] dp lt: CR retry [ 11.184923] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 11.184925] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 11.184935] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.184943] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.184947] dp lt: tx_pu: 0x30 [ 11.185621] dp lt: CR not done [ 11.185845] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.185846] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.185847] dp lt: CR retry [ 11.185849] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 11.185852] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 11.185861] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.185868] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.185873] dp lt: tx_pu: 0x30 [ 11.186558] dp lt: CR done [ 11.186560] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 11.186563] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 11.188478] dp lt: CE done [ 11.188480] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 11.265970] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 11.265972] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 11.265975] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 11.305442] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.305449] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.305454] dp lt: tx_pu: 0x30 [ 11.306667] tegradc tegradc.1: dp: irq event received [ 11.309129] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 11.309151] dp lt: fast link training fail [ 11.309154] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 11.309157] dp lt: state 0 (Reset), pending_lt_evt 0 [ 11.310351] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 11.310488] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 11.310491] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 11.310721] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 11.310728] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 11.310732] dp lt: tx_pu: 0x20 [ 11.311318] tegradc tegradc.1: dp: irq event received [ 11.311618] dp lt: CR not done [ 11.311841] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.311843] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.311844] dp lt: CR retry [ 11.311846] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 11.311848] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 11.311858] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.311865] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.311869] dp lt: tx_pu: 0x30 [ 11.312545] dp lt: CR not done [ 11.312768] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.312769] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.312770] dp lt: CR retry [ 11.312772] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 11.312774] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 11.312784] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.312792] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.312796] dp lt: tx_pu: 0x30 [ 11.313472] dp lt: CR done [ 11.313474] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 11.313476] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 11.315393] dp lt: CE done [ 11.315396] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 11.393970] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 11.393973] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 11.393975] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 11.432352] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.432359] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.432364] dp lt: tx_pu: 0x30 [ 11.433575] tegradc tegradc.1: dp: irq event received [ 11.436037] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 11.436059] dp lt: fast link training fail [ 11.436062] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 11.436065] dp lt: state 0 (Reset), pending_lt_evt 0 [ 11.437250] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 11.437387] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 11.437390] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 11.437621] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 11.437628] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 11.437632] dp lt: tx_pu: 0x20 [ 11.438216] tegradc tegradc.1: dp: irq event received [ 11.438519] dp lt: CR not done [ 11.438742] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.438744] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.438745] dp lt: CR retry [ 11.438747] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 11.438750] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 11.438759] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.438767] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.438771] dp lt: tx_pu: 0x30 [ 11.439446] dp lt: CR not done [ 11.439670] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.439672] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.439673] dp lt: CR retry [ 11.439674] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 11.439677] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 11.439687] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.439694] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.439698] dp lt: tx_pu: 0x30 [ 11.440373] dp lt: CR done [ 11.440375] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 11.440378] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 11.442295] dp lt: CE done [ 11.442298] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 11.513974] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 11.513976] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 11.513979] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 11.559253] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.559261] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.559265] dp lt: tx_pu: 0x30 [ 11.560465] tegradc tegradc.1: dp: irq event received [ 11.562930] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 11.562953] dp lt: fast link training fail [ 11.562955] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 11.562958] dp lt: state 0 (Reset), pending_lt_evt 0 [ 11.564143] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 11.564280] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 11.564283] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 11.564513] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 11.564520] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 11.564524] dp lt: tx_pu: 0x20 [ 11.565109] tegradc tegradc.1: dp: irq event received [ 11.565411] dp lt: CR not done [ 11.565634] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.565636] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.565637] dp lt: CR retry [ 11.565639] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 11.565642] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 11.565651] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.565659] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.565663] dp lt: tx_pu: 0x30 [ 11.566340] dp lt: CR not done [ 11.566562] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.566564] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.566565] dp lt: CR retry [ 11.566567] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 11.566570] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 11.566580] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.566588] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.566592] dp lt: tx_pu: 0x30 [ 11.567268] dp lt: CR done [ 11.567270] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 11.567273] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 11.569187] dp lt: CE done [ 11.569190] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 11.645972] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 11.645974] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 11.645977] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 11.686140] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.686148] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.686152] dp lt: tx_pu: 0x30 [ 11.687365] tegradc tegradc.1: dp: irq event received [ 11.689830] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 11.689852] dp lt: fast link training fail [ 11.689854] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 11.689857] dp lt: state 0 (Reset), pending_lt_evt 0 [ 11.691044] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 11.691181] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 11.691183] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 11.691414] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 11.691421] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 11.691426] dp lt: tx_pu: 0x20 [ 11.692010] tegradc tegradc.1: dp: irq event received [ 11.692310] dp lt: CR not done [ 11.692532] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.692534] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.692535] dp lt: CR retry [ 11.692537] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 11.692540] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 11.692550] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.692557] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.692561] dp lt: tx_pu: 0x30 [ 11.693236] dp lt: CR not done [ 11.693459] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.693460] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.693461] dp lt: CR retry [ 11.693463] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 11.693466] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 11.693476] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.693483] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.693487] dp lt: tx_pu: 0x30 [ 11.694165] dp lt: CR done [ 11.694167] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 11.694170] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 11.696083] dp lt: CE done [ 11.696086] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 11.765976] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 11.765979] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 11.765981] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 11.813032] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.813040] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.813045] dp lt: tx_pu: 0x30 [ 11.814255] tegradc tegradc.1: dp: irq event received [ 11.816718] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 11.816741] dp lt: fast link training fail [ 11.816743] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 11.816746] dp lt: state 0 (Reset), pending_lt_evt 0 [ 11.817934] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 11.818071] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 11.818074] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 11.818304] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 11.818311] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 11.818316] dp lt: tx_pu: 0x20 [ 11.818904] tegradc tegradc.1: dp: irq event received [ 11.819202] dp lt: CR not done [ 11.819425] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.819427] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.819428] dp lt: CR retry [ 11.819430] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 11.819432] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 11.819442] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.819450] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.819454] dp lt: tx_pu: 0x30 [ 11.820130] dp lt: CR not done [ 11.820353] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.820355] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.820356] dp lt: CR retry [ 11.820357] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 11.820360] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 11.820370] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.820377] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.820381] dp lt: tx_pu: 0x30 [ 11.821057] dp lt: CR done [ 11.821059] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 11.821062] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 11.822979] dp lt: CE done [ 11.822981] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 11.897967] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 11.897969] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 11.897972] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 11.939941] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.939948] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.939953] dp lt: tx_pu: 0x30 [ 11.941162] tegradc tegradc.1: dp: irq event received [ 11.943624] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 11.943646] dp lt: fast link training fail [ 11.943648] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 11.943652] dp lt: state 0 (Reset), pending_lt_evt 0 [ 11.944835] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 11.944972] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 11.944974] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 11.945205] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 11.945213] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 11.945217] dp lt: tx_pu: 0x20 [ 11.945804] tegradc tegradc.1: dp: irq event received [ 11.946105] dp lt: CR not done [ 11.946328] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.946330] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.946331] dp lt: CR retry [ 11.946333] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 11.946336] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 11.946346] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.946353] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.946357] dp lt: tx_pu: 0x30 [ 11.947033] dp lt: CR not done [ 11.947257] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.947258] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.947259] dp lt: CR retry [ 11.947261] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 11.947263] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 11.947273] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 11.947281] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 11.947285] dp lt: tx_pu: 0x30 [ 11.947960] dp lt: CR done [ 11.947962] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 11.947965] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 11.949880] dp lt: CE done [ 11.949883] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 12.025971] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 12.025974] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 12.025976] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 12.066838] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.066845] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.066850] dp lt: tx_pu: 0x30 [ 12.068059] tegradc tegradc.1: dp: irq event received [ 12.070525] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 12.070548] dp lt: fast link training fail [ 12.070550] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 12.070553] dp lt: state 0 (Reset), pending_lt_evt 0 [ 12.071738] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 12.071874] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 12.071877] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 12.072107] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 12.072115] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 12.072120] dp lt: tx_pu: 0x20 [ 12.072707] tegradc tegradc.1: dp: irq event received [ 12.073005] dp lt: CR not done [ 12.073228] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.073229] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.073230] dp lt: CR retry [ 12.073232] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 12.073235] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 12.073245] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.073252] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.073257] dp lt: tx_pu: 0x30 [ 12.073934] dp lt: CR not done [ 12.074157] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.074159] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.074160] dp lt: CR retry [ 12.074162] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 12.074164] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 12.074174] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.074181] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.074185] dp lt: tx_pu: 0x30 [ 12.074861] dp lt: CR done [ 12.074863] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 12.074866] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 12.076780] dp lt: CE done [ 12.076783] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 12.145973] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 12.145975] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 12.145978] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 12.193744] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.193752] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.193756] dp lt: tx_pu: 0x30 [ 12.194967] tegradc tegradc.1: dp: irq event received [ 12.197428] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 12.197450] dp lt: fast link training fail [ 12.197452] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 12.197456] dp lt: state 0 (Reset), pending_lt_evt 0 [ 12.198641] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 12.198778] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 12.198781] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 12.199011] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 12.199018] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 12.199023] dp lt: tx_pu: 0x20 [ 12.199608] tegradc tegradc.1: dp: irq event received [ 12.199908] dp lt: CR not done [ 12.200131] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.200133] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.200134] dp lt: CR retry [ 12.200136] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 12.200138] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 12.200148] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.200155] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.200159] dp lt: tx_pu: 0x30 [ 12.200835] dp lt: CR not done [ 12.201058] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.201059] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.201060] dp lt: CR retry [ 12.201062] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 12.201064] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 12.201074] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.201081] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.201086] dp lt: tx_pu: 0x30 [ 12.201761] dp lt: CR done [ 12.201763] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 12.201765] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 12.203683] dp lt: CE done [ 12.203685] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 12.277967] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 12.277969] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 12.277971] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 12.320631] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.320638] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.320643] dp lt: tx_pu: 0x30 [ 12.321853] tegradc tegradc.1: dp: irq event received [ 12.324314] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 12.324336] dp lt: fast link training fail [ 12.324338] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 12.324341] dp lt: state 0 (Reset), pending_lt_evt 0 [ 12.325524] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 12.325660] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 12.325663] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 12.325892] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 12.325900] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 12.325913] dp lt: tx_pu: 0x20 [ 12.326492] tegradc tegradc.1: dp: irq event received [ 12.326796] dp lt: CR not done [ 12.327018] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.327020] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.327021] dp lt: CR retry [ 12.327023] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 12.327025] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 12.327035] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.327042] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.327046] dp lt: tx_pu: 0x30 [ 12.327719] dp lt: CR not done [ 12.327941] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.327943] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.327944] dp lt: CR retry [ 12.327945] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 12.327948] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 12.327958] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.327965] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.327969] dp lt: tx_pu: 0x30 [ 12.328642] dp lt: CR done [ 12.328644] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 12.328647] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 12.330558] dp lt: CE done [ 12.330561] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 12.401974] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 12.401976] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 12.401979] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 12.447514] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.447522] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.447526] dp lt: tx_pu: 0x30 [ 12.448736] tegradc tegradc.1: dp: irq event received [ 12.451201] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 12.451223] dp lt: fast link training fail [ 12.451225] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 12.451228] dp lt: state 0 (Reset), pending_lt_evt 0 [ 12.452414] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 12.452550] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 12.452553] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 12.452783] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 12.452791] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 12.452795] dp lt: tx_pu: 0x20 [ 12.453378] tegradc tegradc.1: dp: irq event received [ 12.453679] dp lt: CR not done [ 12.453902] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.453913] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.453914] dp lt: CR retry [ 12.453916] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 12.453918] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 12.453928] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.453935] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.453939] dp lt: tx_pu: 0x30 [ 12.454615] dp lt: CR not done [ 12.454839] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.454840] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.454841] dp lt: CR retry [ 12.454843] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 12.454846] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 12.454855] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.454862] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.454866] dp lt: tx_pu: 0x30 [ 12.455541] dp lt: CR done [ 12.455543] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 12.455546] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 12.457460] dp lt: CE done [ 12.457463] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 12.529967] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 12.529969] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 12.529971] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 12.574425] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.574433] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.574437] dp lt: tx_pu: 0x30 [ 12.575649] tegradc tegradc.1: dp: irq event received [ 12.578115] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 12.578137] dp lt: fast link training fail [ 12.578139] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 12.578142] dp lt: state 0 (Reset), pending_lt_evt 0 [ 12.579328] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 12.579466] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 12.579468] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 12.579699] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 12.579706] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 12.579710] dp lt: tx_pu: 0x20 [ 12.580293] tegradc tegradc.1: dp: irq event received [ 12.580596] dp lt: CR not done [ 12.580818] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.580820] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.580821] dp lt: CR retry [ 12.580823] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 12.580826] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 12.580835] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.580843] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.580847] dp lt: tx_pu: 0x30 [ 12.581523] dp lt: CR not done [ 12.581745] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.581747] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.581748] dp lt: CR retry [ 12.581750] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 12.581752] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 12.581762] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.581769] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.581773] dp lt: tx_pu: 0x30 [ 12.582450] dp lt: CR done [ 12.582452] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 12.582455] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 12.584368] dp lt: CE done [ 12.584370] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 12.661971] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 12.661973] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 12.661975] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 12.701332] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.701340] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.701344] dp lt: tx_pu: 0x30 [ 12.702556] tegradc tegradc.1: dp: irq event received [ 12.705016] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 12.705038] dp lt: fast link training fail [ 12.705040] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 12.705043] dp lt: state 0 (Reset), pending_lt_evt 0 [ 12.706230] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 12.706367] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 12.706370] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 12.706601] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 12.706608] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 12.706613] dp lt: tx_pu: 0x20 [ 12.707193] tegradc tegradc.1: dp: irq event received [ 12.707498] dp lt: CR not done [ 12.707721] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.707723] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.707724] dp lt: CR retry [ 12.707726] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 12.707728] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 12.707738] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.707745] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.707750] dp lt: tx_pu: 0x30 [ 12.708425] dp lt: CR not done [ 12.708648] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.708650] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.708651] dp lt: CR retry [ 12.708653] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 12.708655] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 12.708664] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.708672] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.708676] dp lt: tx_pu: 0x30 [ 12.709351] dp lt: CR done [ 12.709353] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 12.709356] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 12.711272] dp lt: CE done [ 12.711275] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 12.789971] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 12.789973] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 12.789976] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 12.828226] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.828233] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.828238] dp lt: tx_pu: 0x30 [ 12.829490] tegradc tegradc.1: dp: irq event received [ 12.831899] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 12.831922] dp lt: fast link training fail [ 12.831924] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 12.831927] dp lt: state 0 (Reset), pending_lt_evt 0 [ 12.833113] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 12.833249] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 12.833252] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 12.833482] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 12.833489] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 12.833494] dp lt: tx_pu: 0x20 [ 12.834081] tegradc tegradc.1: dp: irq event received [ 12.834380] dp lt: CR not done [ 12.834603] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.834605] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.834606] dp lt: CR retry [ 12.834608] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 12.834611] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 12.834620] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.834628] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.834632] dp lt: tx_pu: 0x30 [ 12.835307] dp lt: CR not done [ 12.835530] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.835532] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.835533] dp lt: CR retry [ 12.835534] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 12.835537] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 12.835547] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.835554] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.835558] dp lt: tx_pu: 0x30 [ 12.836233] dp lt: CR done [ 12.836236] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 12.836238] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 12.838152] dp lt: CE done [ 12.838155] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 12.909976] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 12.909978] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 12.909981] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 12.955115] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.955123] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.955128] dp lt: tx_pu: 0x30 [ 12.956338] tegradc tegradc.1: dp: irq event received [ 12.958802] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 12.958824] dp lt: fast link training fail [ 12.958826] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 12.958829] dp lt: state 0 (Reset), pending_lt_evt 0 [ 12.960013] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 12.960151] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 12.960153] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 12.960384] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 12.960391] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 12.960395] dp lt: tx_pu: 0x20 [ 12.960979] tegradc tegradc.1: dp: irq event received [ 12.961279] dp lt: CR not done [ 12.961502] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.961504] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.961505] dp lt: CR retry [ 12.961507] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 12.961509] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 12.961519] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.961526] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.961530] dp lt: tx_pu: 0x30 [ 12.962208] dp lt: CR not done [ 12.962430] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.962432] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.962433] dp lt: CR retry [ 12.962435] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 12.962437] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 12.962447] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 12.962454] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 12.962458] dp lt: tx_pu: 0x30 [ 12.963134] dp lt: CR done [ 12.963136] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 12.963139] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 12.965055] dp lt: CE done [ 12.965057] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 13.037969] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 13.037971] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 13.037973] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 13.082015] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.082023] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.082028] dp lt: tx_pu: 0x30 [ 13.083227] tegradc tegradc.1: dp: irq event received [ 13.085689] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 13.085712] dp lt: fast link training fail [ 13.085714] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 13.085717] dp lt: state 0 (Reset), pending_lt_evt 0 [ 13.086902] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 13.087040] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 13.087043] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.087273] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 13.087280] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 13.087285] dp lt: tx_pu: 0x20 [ 13.087870] tegradc tegradc.1: dp: irq event received [ 13.088169] dp lt: CR not done [ 13.088392] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.088394] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.088395] dp lt: CR retry [ 13.088397] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 13.088399] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.088409] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.088416] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.088420] dp lt: tx_pu: 0x30 [ 13.089095] dp lt: CR not done [ 13.089318] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.089319] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.089320] dp lt: CR retry [ 13.089322] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 13.089324] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.089334] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.089342] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.089345] dp lt: tx_pu: 0x30 [ 13.090025] dp lt: CR done [ 13.090027] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 13.090030] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 13.091944] dp lt: CE done [ 13.091946] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 13.169970] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 13.169972] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 13.169974] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 13.208894] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.208902] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.208906] dp lt: tx_pu: 0x30 [ 13.210115] tegradc tegradc.1: dp: irq event received [ 13.212577] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 13.212599] dp lt: fast link training fail [ 13.212602] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 13.212605] dp lt: state 0 (Reset), pending_lt_evt 0 [ 13.213789] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 13.213928] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 13.213931] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.214161] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 13.214169] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 13.214173] dp lt: tx_pu: 0x20 [ 13.214753] tegradc tegradc.1: dp: irq event received [ 13.215057] dp lt: CR not done [ 13.215281] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.215282] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.215283] dp lt: CR retry [ 13.215285] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 13.215288] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.215297] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.215304] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.215309] dp lt: tx_pu: 0x30 [ 13.215984] dp lt: CR not done [ 13.216207] dp lt: new config: lane 0: vs level: 2, pe level: 0, pc2 level: 0 [ 13.216208] dp lt: new config: lane 1: vs level: 2, pe level: 0, pc2 level: 0 [ 13.216209] dp lt: CR retry [ 13.216211] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 13.216213] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.216223] dp lt: config: lane 0: vs level: 2, pe level: 0, pc2 level: 0 [ 13.216230] dp lt: config: lane 1: vs level: 2, pe level: 0, pc2 level: 0 [ 13.216234] dp lt: tx_pu: 0x40 [ 13.216909] dp lt: CR not done [ 13.217132] dp lt: new config: lane 0: vs level: 2, pe level: 0, pc2 level: 0 [ 13.217133] dp lt: new config: lane 1: vs level: 2, pe level: 0, pc2 level: 0 [ 13.217134] dp lt: CR retry [ 13.217136] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 13.217139] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.217148] dp lt: config: lane 0: vs level: 2, pe level: 0, pc2 level: 0 [ 13.217156] dp lt: config: lane 1: vs level: 2, pe level: 0, pc2 level: 0 [ 13.217160] dp lt: tx_pu: 0x40 [ 13.217835] dp lt: CR done [ 13.217837] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 13.217840] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 13.219758] dp lt: CE done [ 13.219760] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 13.293968] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 13.293970] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 13.293973] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 13.336717] dp lt: config: lane 0: vs level: 2, pe level: 0, pc2 level: 0 [ 13.336724] dp lt: config: lane 1: vs level: 2, pe level: 0, pc2 level: 0 [ 13.336729] dp lt: tx_pu: 0x40 [ 13.337940] tegradc tegradc.1: dp: irq event received [ 13.340404] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 13.340426] dp lt: fast link training fail [ 13.340428] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 13.340431] dp lt: state 0 (Reset), pending_lt_evt 0 [ 13.341616] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 13.341752] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 13.341755] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.341987] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 13.341994] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 13.341999] dp lt: tx_pu: 0x20 [ 13.342584] tegradc tegradc.1: dp: irq event received [ 13.342883] dp lt: CR not done [ 13.343106] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.343108] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.343109] dp lt: CR retry [ 13.343110] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 13.343113] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.343123] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.343130] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.343134] dp lt: tx_pu: 0x30 [ 13.343810] dp lt: CR not done [ 13.344032] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.344034] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.344035] dp lt: CR retry [ 13.344037] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 13.344039] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.344049] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.344056] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.344060] dp lt: tx_pu: 0x30 [ 13.344736] dp lt: CR done [ 13.344738] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 13.344740] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 13.346656] dp lt: CE done [ 13.346659] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 13.417974] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 13.417976] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 13.417978] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 13.463619] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.463627] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.463631] dp lt: tx_pu: 0x30 [ 13.464842] tegradc tegradc.1: dp: irq event received [ 13.467313] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 13.467335] dp lt: fast link training fail [ 13.467337] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 13.467340] dp lt: state 0 (Reset), pending_lt_evt 0 [ 13.468525] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 13.468662] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 13.468665] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.468895] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 13.468902] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 13.468906] dp lt: tx_pu: 0x20 [ 13.469494] tegradc tegradc.1: dp: irq event received [ 13.469792] dp lt: CR not done [ 13.470016] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.470018] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.470019] dp lt: CR retry [ 13.470021] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 13.470024] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.470033] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.470041] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.470045] dp lt: tx_pu: 0x30 [ 13.470721] dp lt: CR not done [ 13.470943] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.470945] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.470946] dp lt: CR retry [ 13.470948] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 13.470950] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.470960] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.470967] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.470971] dp lt: tx_pu: 0x30 [ 13.471647] dp lt: CR done [ 13.471649] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 13.471651] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 13.473566] dp lt: CE done [ 13.473569] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 13.549971] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 13.549973] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 13.549975] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 13.590517] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.590524] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.590529] dp lt: tx_pu: 0x30 [ 13.591739] tegradc tegradc.1: dp: irq event received [ 13.594204] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 13.594226] dp lt: fast link training fail [ 13.594228] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 13.594231] dp lt: state 0 (Reset), pending_lt_evt 0 [ 13.595415] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 13.595552] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 13.595555] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.595785] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 13.595792] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 13.595797] dp lt: tx_pu: 0x20 [ 13.596382] tegradc tegradc.1: dp: irq event received [ 13.596681] dp lt: CR not done [ 13.596904] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.596906] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.596907] dp lt: CR retry [ 13.596908] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 13.596911] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.596921] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.596928] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.596932] dp lt: tx_pu: 0x30 [ 13.597607] dp lt: CR not done [ 13.597830] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.597832] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.597833] dp lt: CR retry [ 13.597835] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 13.597837] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.597847] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.597854] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.597858] dp lt: tx_pu: 0x30 [ 13.598535] dp lt: CR done [ 13.598538] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 13.598540] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 13.600454] dp lt: CE done [ 13.600456] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 13.673969] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 13.673971] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 13.673973] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 13.717410] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.717418] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.717422] dp lt: tx_pu: 0x30 [ 13.718636] tegradc tegradc.1: dp: irq event received [ 13.721099] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 13.721122] dp lt: fast link training fail [ 13.721124] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 13.721127] dp lt: state 0 (Reset), pending_lt_evt 0 [ 13.722313] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 13.722450] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 13.722453] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.722683] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 13.722690] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 13.722695] dp lt: tx_pu: 0x20 [ 13.723283] tegradc tegradc.1: dp: irq event received [ 13.723579] dp lt: CR not done [ 13.723803] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.723805] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.723806] dp lt: CR retry [ 13.723808] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 13.723810] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.723820] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.723827] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.723832] dp lt: tx_pu: 0x30 [ 13.724507] dp lt: CR not done [ 13.724730] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.724731] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.724732] dp lt: CR retry [ 13.724734] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 13.724737] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.724746] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.724754] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.724758] dp lt: tx_pu: 0x30 [ 13.725433] dp lt: CR done [ 13.725436] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 13.725438] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 13.727354] dp lt: CE done [ 13.727357] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 13.801968] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 13.801970] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 13.801972] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 13.844306] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.844314] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.844318] dp lt: tx_pu: 0x30 [ 13.845528] tegradc tegradc.1: dp: irq event received [ 13.847990] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 13.848012] dp lt: fast link training fail [ 13.848014] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 13.848017] dp lt: state 0 (Reset), pending_lt_evt 0 [ 13.849202] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 13.849339] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 13.849342] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.849571] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 13.849578] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 13.849582] dp lt: tx_pu: 0x20 [ 13.850171] tegradc tegradc.1: dp: irq event received [ 13.850469] dp lt: CR not done [ 13.850693] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.850694] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.850695] dp lt: CR retry [ 13.850697] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 13.850700] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.850710] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.850717] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.850721] dp lt: tx_pu: 0x30 [ 13.851397] dp lt: CR not done [ 13.851619] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.851621] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.851622] dp lt: CR retry [ 13.851623] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 13.851626] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.851636] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.851643] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.851647] dp lt: tx_pu: 0x30 [ 13.852325] dp lt: CR done [ 13.852327] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 13.852330] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 13.854245] dp lt: CE done [ 13.854248] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 13.925974] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 13.925977] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 13.925979] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 13.971205] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.971212] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.971217] dp lt: tx_pu: 0x30 [ 13.972416] tegradc tegradc.1: dp: irq event received [ 13.974880] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 13.974902] dp lt: fast link training fail [ 13.974904] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 13.974907] dp lt: state 0 (Reset), pending_lt_evt 0 [ 13.976092] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 13.976229] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 13.976232] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.976461] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 13.976468] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 13.976473] dp lt: tx_pu: 0x20 [ 13.977062] tegradc tegradc.1: dp: irq event received [ 13.977357] dp lt: CR not done [ 13.977580] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.977581] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.977582] dp lt: CR retry [ 13.977584] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 13.977587] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.977597] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.977604] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.977608] dp lt: tx_pu: 0x30 [ 13.978286] dp lt: CR not done [ 13.978509] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.978510] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.978511] dp lt: CR retry [ 13.978513] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 13.978516] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 13.978525] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 13.978532] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 13.978537] dp lt: tx_pu: 0x30 [ 13.979213] dp lt: CR done [ 13.979215] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 13.979217] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 13.981131] dp lt: CE done [ 13.981133] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 14.053976] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 14.053978] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 14.053980] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 14.098088] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.098096] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.098100] dp lt: tx_pu: 0x30 [ 14.099310] tegradc tegradc.1: dp: irq event received [ 14.101772] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 14.101794] dp lt: fast link training fail [ 14.101796] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 14.101799] dp lt: state 0 (Reset), pending_lt_evt 0 [ 14.102984] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 14.103120] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 14.103123] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 14.103353] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 14.103360] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 14.103365] dp lt: tx_pu: 0x20 [ 14.103948] tegradc tegradc.1: dp: irq event received [ 14.104249] dp lt: CR not done [ 14.104472] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.104474] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.104475] dp lt: CR retry [ 14.104477] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 14.104479] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 14.104489] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.104496] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.104500] dp lt: tx_pu: 0x30 [ 14.105175] dp lt: CR not done [ 14.105398] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.105399] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.105400] dp lt: CR retry [ 14.105402] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 14.105405] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 14.105414] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.105422] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.105426] dp lt: tx_pu: 0x30 [ 14.106104] dp lt: CR done [ 14.106106] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 14.106109] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 14.108024] dp lt: CE done [ 14.108026] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 14.185971] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 14.185973] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 14.185975] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 14.224980] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.224987] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.224992] dp lt: tx_pu: 0x30 [ 14.226203] tegradc tegradc.1: dp: irq event received [ 14.228664] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 14.228686] dp lt: fast link training fail [ 14.228688] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 14.228691] dp lt: state 0 (Reset), pending_lt_evt 0 [ 14.229876] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 14.230013] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 14.230016] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 14.230246] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 14.230254] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 14.230258] dp lt: tx_pu: 0x20 [ 14.230844] tegradc tegradc.1: dp: irq event received [ 14.231144] dp lt: CR not done [ 14.231367] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.231369] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.231370] dp lt: CR retry [ 14.231372] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 14.231374] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 14.231385] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.231392] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.231396] dp lt: tx_pu: 0x30 [ 14.232071] dp lt: CR not done [ 14.232294] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.232296] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.232297] dp lt: CR retry [ 14.232299] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 14.232301] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 14.232310] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.232318] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.232322] dp lt: tx_pu: 0x30 [ 14.232997] dp lt: CR done [ 14.232999] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 14.233002] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 14.234919] dp lt: CE done [ 14.234922] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 14.309968] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 14.309970] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 14.309972] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 14.351870] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.351878] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.351882] dp lt: tx_pu: 0x30 [ 14.353093] tegradc tegradc.1: dp: irq event received [ 14.355555] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 14.355577] dp lt: fast link training fail [ 14.355579] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 14.355582] dp lt: state 0 (Reset), pending_lt_evt 0 [ 14.356766] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 14.356903] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 14.356906] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 14.357137] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 14.357144] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 14.357148] dp lt: tx_pu: 0x20 [ 14.357736] tegradc tegradc.1: dp: irq event received [ 14.358036] dp lt: CR not done [ 14.358259] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.358261] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.358262] dp lt: CR retry [ 14.358264] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 14.358266] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 14.358276] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.358283] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.358287] dp lt: tx_pu: 0x30 [ 14.358963] dp lt: CR not done [ 14.359186] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.359188] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.359189] dp lt: CR retry [ 14.359190] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 14.359193] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 14.359203] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.359210] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.359214] dp lt: tx_pu: 0x30 [ 14.359889] dp lt: CR done [ 14.359891] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 14.359894] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 14.361808] dp lt: CE done [ 14.361810] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 14.433968] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 14.433971] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 14.433973] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 14.478766] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.478773] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.478778] dp lt: tx_pu: 0x30 [ 14.479986] tegradc tegradc.1: dp: irq event received [ 14.482457] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 14.482480] dp lt: fast link training fail [ 14.482482] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 14.482485] dp lt: state 0 (Reset), pending_lt_evt 0 [ 14.483670] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 14.483807] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 14.483809] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 14.484040] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 14.484047] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 14.484052] dp lt: tx_pu: 0x20 [ 14.484638] tegradc tegradc.1: dp: irq event received [ 14.484937] dp lt: CR not done [ 14.485160] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.485162] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.485163] dp lt: CR retry [ 14.485165] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 14.485167] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 14.485177] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.485185] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.485189] dp lt: tx_pu: 0x30 [ 14.485865] dp lt: CR not done [ 14.486089] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.486091] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.486092] dp lt: CR retry [ 14.486094] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 14.486096] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 14.486106] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.486113] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.486117] dp lt: tx_pu: 0x30 [ 14.486793] dp lt: CR done [ 14.486795] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 14.486797] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 14.488714] dp lt: CE done [ 14.488716] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 14.561968] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 14.561970] dp lt: switching from state 5 (link training pass) to state 1 (fast link training) [ 14.561972] dp lt: state 1 (fast link training), pending_lt_evt 0 [ 14.605669] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.605677] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.605681] dp lt: tx_pu: 0x30 [ 14.606894] tegradc tegradc.1: dp: irq event received [ 14.609355] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 14.609378] dp lt: fast link training fail [ 14.609380] dp lt: switching from state 1 (fast link training) to state 0 (Reset) [ 14.609383] dp lt: state 0 (Reset), pending_lt_evt 0 [ 14.610569] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 14.610705] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 14.610708] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 14.610938] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 14.610945] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 14.610950] dp lt: tx_pu: 0x20 [ 14.611533] tegradc tegradc.1: dp: irq event received [ 14.611835] dp lt: CR not done [ 14.612058] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.612059] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.612060] dp lt: CR retry [ 14.612062] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 14.612065] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 14.612074] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.612082] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.612086] dp lt: tx_pu: 0x30 [ 14.612761] dp lt: CR not done [ 14.612984] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.612986] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.612987] dp lt: CR retry [ 14.612988] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 14.612991] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 14.613001] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.613008] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 14.613012] dp lt: tx_pu: 0x30 [ 14.613687] dp lt: CR done [ 14.613689] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 14.613692] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 14.614865] dp lt: CE not done [ 14.615088] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.615090] dp lt: new config: lane 1: vs level: 1, pe level: 1, pc2 level: 0 [ 14.615097] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.615104] dp lt: config: lane 1: vs level: 1, pe level: 1, pc2 level: 0 [ 14.615108] dp lt: tx_pu: 0x40 [ 14.615356] dp lt: CE retry [ 14.615358] dp lt: switching from state 3 (channel equalization) to state 3 (channel equalization) [ 14.615360] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 14.616313] dp lt: CE not done [ 14.616535] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.616536] dp lt: new config: lane 1: vs level: 1, pe level: 2, pc2 level: 0 [ 14.616544] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.616551] dp lt: config: lane 1: vs level: 1, pe level: 2, pc2 level: 0 [ 14.616555] dp lt: tx_pu: 0x60 [ 14.616803] dp lt: CE retry [ 14.616805] dp lt: switching from state 3 (channel equalization) to state 3 (channel equalization) [ 14.616807] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 14.617759] dp lt: CE not done [ 14.617983] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.617984] dp lt: new config: lane 1: vs level: 1, pe level: 3, pc2 level: 0 [ 14.617992] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.617999] dp lt: config: lane 1: vs level: 1, pe level: 3, pc2 level: 0 [ 14.618003] dp lt: tx_pu: 0x30 [ 14.618250] dp lt: CE retry [ 14.618252] dp lt: switching from state 3 (channel equalization) to state 3 (channel equalization) [ 14.618255] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 14.619206] dp lt: CE not done [ 14.619429] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.619431] dp lt: new config: lane 1: vs level: 1, pe level: 3, pc2 level: 0 [ 14.619438] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.619445] dp lt: config: lane 1: vs level: 1, pe level: 3, pc2 level: 0 [ 14.619449] dp lt: tx_pu: 0x30 [ 14.619698] dp lt: CE retry [ 14.619700] dp lt: switching from state 3 (channel equalization) to state 3 (channel equalization) [ 14.619702] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 14.620654] dp lt: CE not done [ 14.620877] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.620879] dp lt: new config: lane 1: vs level: 1, pe level: 3, pc2 level: 0 [ 14.620886] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.620893] dp lt: config: lane 1: vs level: 1, pe level: 3, pc2 level: 0 [ 14.620897] dp lt: tx_pu: 0x30 [ 14.621144] dp lt: CE retry [ 14.621146] dp lt: switching from state 3 (channel equalization) to state 3 (channel equalization) [ 14.621149] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 14.622103] dp lt: CE not done [ 14.622325] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.622327] dp lt: new config: lane 1: vs level: 1, pe level: 3, pc2 level: 0 [ 14.622334] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 14.622341] dp lt: config: lane 1: vs level: 1, pe level: 3, pc2 level: 0 [ 14.622345] dp lt: tx_pu: 0x30 [ 14.622593] dp lt: CE retry [ 14.622595] dp lt: switching from state 3 (channel equalization) to state 3 (channel equalization) [ 14.622598] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 14.623549] dp lt: CE not done [ 14.623551] dp lt: CE retry limit 5 reached [ 14.623553] dp lt: switching from state 3 (channel equalization) to state 7 (reduce lane count) [ 14.623555] dp lt: state 7 (reduce lane count), pending_lt_evt 0 [ 14.623559] dp lt: lane count already lowest [ 14.624963] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 14.624986] dp lt: switching from state 7 (reduce lane count) to state 4 (link training fail/disable) [ 14.685929] dp lt: state 4 (link training fail/disable), pending_lt_evt 1 [ 14.685930] dp lt: switching from state 4 (link training fail/disable) to state 0 (Reset) [ 14.685933] dp lt: state 0 (Reset), pending_lt_evt 0 [ 14.685937] dp lt: cur_hpd: 1, link cfg valid: 0 [ 14.687121] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree [ 14.687143] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable) [ 22.179662] Found dev node: /dev/mmcblk0p1 [ 22.423825] EXT4-fs (mmcblk0p1): 9 orphan inodes deleted [ 22.429165] EXT4-fs (mmcblk0p1): recovery complete [ 22.452280] EXT4-fs (mmcblk0p1): mounted filesystem with ordered data mode. Opts: (null) [ 22.461139] Rootfs mounted over mmcblk0p1 [ 22.479532] Switching from initrd to actual rootfs [ 22.560432] systemd[1]: System time before build time, advancing clock. [ 22.581145] ip_tables: (C) 2000-2006 Netfilter Core Team [ 22.597471] cgroup: cgroup2: unknown option "nsdelegate" [ 22.611637] systemd[1]: systemd 237 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD -IDN2 +IDN -PCRE2 default-hierarchy=hybrid) [ 22.633779] systemd[1]: Detected architecture arm64. [ 22.668854] systemd[1]: Set hostname to . [ 22.738218] systemd[1]: File /lib/systemd/system/systemd-journald.service:36 configures an IP firewall (IPAddressDeny=any), but the local system does not support BPF/cgroup based firewalling. [ 22.755444] systemd[1]: Proceeding WITHOUT firewalling in effect! (This warning is only shown for the first loaded unit using IP firewalling.) [ 22.861953] systemd[1]: Created slice User and Session Slice. [ 22.869876] systemd[1]: Set up automount Arbitrary Executable File Formats File System Automount Point. [ 22.880280] systemd[1]: Created slice System Slice. [ 22.885332] systemd[1]: Reached target Slices. [ 22.890116] systemd[1]: Listening on Journal Socket. [ 22.949700] EXT4-fs (mmcblk0p1): re-mounted. Opts: (null) [ 23.019997] nvgpu: 57000000.gpu gm20b_init_clk_setup_sw:1268 [INFO] GPCPLL initial settings: NA mode, M=1, N=34, P=3 (id = 1) [ 23.730577] using random self ethernet address [ 23.741326] using random host ethernet address [ 24.517191] using random self ethernet address [ 24.534369] using random host ethernet address Ubuntu 18.04.3 LTS nano-desktop ttyS0 nano-desktop login: