/* * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * */ / { aliases { spi0 = &spi0; spi1 = &spi1; spi2 = &spi2; spi6 = &qspi0; spi7 = &qspi1; }; spi0: spi@3210000 { compatible = "nvidia,tegra186-spi"; reg = <0x0 0x03210000 0x0 0x10000>; interrupts = <0 36 0x04>; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu TEGRA_SID_GPCDMA_0>; dma-coherent; dmas = <&gpcdma 15>, <&gpcdma 15>; dma-names = "rx", "tx"; spi-max-frequency = <65000000>; nvidia,clk-parents = "pll_p", "clk_m"; clocks = <&bpmp_clks TEGRA194_CLK_SPI1>, <&bpmp_clks TEGRA194_CLK_PLLP_OUT0>, <&bpmp_clks TEGRA194_CLK_CLK_M>; clock-names = "spi", "pll_p", "clk_m"; resets = <&bpmp_resets TEGRA194_RESET_SPI1>; reset-names = "spi"; status = "okay"; // "disabled"; }; spi1: spi@c260000 { compatible = "nvidia,tegra186-spi"; reg = <0x0 0x0c260000 0x0 0x10000>; interrupts = <0 37 0x04>; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu TEGRA_SID_GPCDMA_0>; dma-coherent; dmas = <&gpcdma 16>, <&gpcdma 16>; dma-names = "rx", "tx"; spi-max-frequency = <65000000>; nvidia,clk-parents = "pll_p", "osc"; clocks = <&bpmp_clks TEGRA194_CLK_SPI2>, <&bpmp_clks TEGRA194_CLK_PLLAON>, <&bpmp_clks TEGRA194_CLK_OSC>; clock-names = "spi", "pll_p", "osc"; resets = <&bpmp_resets TEGRA194_RESET_SPI2>; reset-names = "spi"; status = "okay"; // "disabled"; }; spi2: spi@3230000 { compatible = "nvidia,tegra186-spi"; reg = <0x0 0x03230000 0x0 0x10000>; interrupts = <0 38 0x04>; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu TEGRA_SID_GPCDMA_0>; dma-coherent; dmas = <&gpcdma 17>, <&gpcdma 17>; dma-names = "rx", "tx"; spi-max-frequency = <65000000>; nvidia,clk-parents = "pll_p", "clk_m"; clocks = <&bpmp_clks TEGRA194_CLK_SPI3>, <&bpmp_clks TEGRA194_CLK_PLLP_OUT0>, <&bpmp_clks TEGRA194_CLK_CLK_M>; clock-names = "spi", "pll_p", "clk_m"; resets = <&bpmp_resets TEGRA194_RESET_SPI3>; reset-names = "spi"; status = "disabled"; }; qspi0: spi@3270000 { compatible = "nvidia,tegra186-qspi"; reg = <0x0 0x3270000 0x0 0x10000>; interrupts = < 0 35 0x04 >; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu TEGRA_SID_GPCDMA_0>; dma-coherent; dmas = <&gpcdma 5>, <&gpcdma 5>; dma-names = "rx", "tx"; spi-max-frequency = <204000000>; nvidia,clk-parents = "pllc", "pll_p"; clocks = <&bpmp_clks TEGRA194_CLK_QSPI0>, <&bpmp_clks TEGRA194_CLK_QSPI0_PM>, <&bpmp_clks TEGRA194_CLK_PLLC>, <&bpmp_clks TEGRA194_CLK_PLLP_OUT0>; clock-names = "qspi", "qspi_out", "pllc", "pll_p"; resets = <&bpmp_resets TEGRA194_RESET_QSPI0>; reset-names = "qspi"; status = "disabled"; }; qspi1: spi@3300000 { compatible = "nvidia,tegra186-qspi"; reg = <0x0 0x3300000 0x0 0x10000>; interrupts = < 0 39 0x04 >; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu TEGRA_SID_GPCDMA_0>; dma-coherent; dmas = <&gpcdma 6>, <&gpcdma 6>; dma-names = "rx", "tx"; spi-max-frequency = <204000000>; nvidia,clk-parents = "pllc", "pll_p"; clocks = <&bpmp_clks TEGRA194_CLK_QSPI1>, <&bpmp_clks TEGRA194_CLK_QSPI1_PM>, <&bpmp_clks TEGRA194_CLK_PLLC>, <&bpmp_clks TEGRA194_CLK_PLLP_OUT0>; clock-names = "qspi", "qspi_out", "pllc", "pll_p"; resets = <&bpmp_resets TEGRA194_RESET_QSPI1>; reset-names = "qspi"; status = "disabled"; }; };