# 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/tegra194-p2888-0001-p2822-0000.dts" # 1 "" # 1 "" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/tegra194-p2888-0001-p2822-0000.dts" # 21 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/tegra194-p2888-0001-p2822-0000.dts" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0001-p2822-0000-common.dtsi" 1 # 16 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0001-p2822-0000-common.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/tegra/kernel-include/dt-bindings/extcon-ids.h" 1 # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0001-p2822-0000-common.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-include/dt-bindings/gpio/tegra194-gpio.h" 1 # 13 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-include/dt-bindings/gpio/tegra194-gpio.h" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/tegra/kernel-include/dt-bindings/gpio/gpio.h" 1 # 14 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-include/dt-bindings/gpio/tegra194-gpio.h" 2 # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0001-p2822-0000-common.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0000-a00.dtsi" 1 # 16 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0000-a00.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-cvm-p2888-0000-a00.dtsi" 1 # 16 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-cvm-p2888-0000-a00.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/tegra/kernel-include/dt-bindings/types.h" 1 # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-cvm-p2888-0000-a00.dtsi" 2 /dts-v1/; /memreserve/ 0x80000000 0x00010000; # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-cvm.dtsi" 1 # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-cvm.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 1 # 19 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/tegra/kernel-include/dt-bindings/version.h" 1 # 20 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-include/dt-bindings/clock/tegra194-clock.h" 1 # 21 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-include/dt-bindings/reset/tegra194-reset.h" 1 # 22 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/tegra/kernel-include/dt-bindings/display/tegra-dc.h" 1 # 23 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-include/dt-bindings/interrupt/tegra194-irq.h" 1 # 24 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/tegra/kernel-include/dt-bindings/interrupt-controller/arm-gic.h" 1 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/tegra/kernel-include/dt-bindings/interrupt-controller/irq.h" 1 # 9 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/tegra/kernel-include/dt-bindings/interrupt-controller/arm-gic.h" 2 # 25 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-include/dt-bindings/soc/tegra194-powergate.h" 1 # 26 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/tegra/kernel-include/dt-bindings/memory/tegra-swgroup.h" 1 # 29 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-include/dt-bindings/memory/tegra194-swgroup.h" 1 # 30 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-sata.dtsi" 1 # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-sata.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/tegra/kernel-include/dt-bindings/pinctrl/pinctrl-tegra.h" 1 # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-sata.dtsi" 2 / { tegra_sata: ahci-sata@3507000 { compatible = "nvidia,tegra194-ahci-sata"; reg = <0x0 0x03507000 0x0 0x00002000>, <0x0 0x03501000 0x0 0x00006000>, <0x0 0x03500000 0x0 0x00001000>, <0x0 0x03A90000 0x0 0x00010000>; reg-names = "sata-ahci", "sata-config", "sata-ipfs", "sata-aux"; interrupts = <0 197 0x04>; dma-coherent; iommus = <&smmu 0x1d>; power-domains = <&bpmp 11U>; clocks = <&bpmp_clks 115U>, <&bpmp_clks 116U>, <&bpmp_clks 102U>; clock-names = "sata", "sata-oob", "pllp"; resets = <&bpmp_resets 78U>, <&bpmp_resets 79U>; reset-names = "sata", "sata-cold"; nvidia,disable-features = "devslp", "dipm"; nvidia,link-flags = "max_power"; status = "disabled"; }; }; # 32 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-power-domain.dtsi" 1 # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-power-domain.dtsi" / { power-domain { compatible = "tegra-power-domains"; status = "disabled"; disa_pd: disa-pd { compatible = "nvidia,tegra194-disa-pd"; #power-domain-cells = <0>; partition-id = <2U>; }; disb_pd: disb-pd { compatible = "nvidia,tegra194-disb-pd"; #power-domain-cells = <0>; partition-id = <3U>; }; disc_pd: disc-pd { compatible = "nvidia,tegra194-disc-pd"; #power-domain-cells = <0>; partition-id = <4U>; }; xusba_pd: xusba-pd { compatible = "nvidia,tegra194-xusba-pd"; #power-domain-cells = <0>; partition-id = <14U>; }; xusbb_pd: xusbb-pd { compatible = "nvidia,tegra194-xusbb-pd"; #power-domain-cells = <0>; partition-id = <15U>; }; xusbc_pd: xusbc-pd { compatible = "nvidia,tegra194-xusbc-pd"; #power-domain-cells = <0>; partition-id = <16U>; }; }; }; # 33 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-trusty.dtsi" 1 # 19 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-trusty.dtsi" / { trusty { compatible = "android,trusty-smc-v1"; ranges; #address-cells = <2>; #size-cells = <2>; status = "disabled"; irq { compatible = "android,trusty-irq-v1"; interrupt-templates = <&IPI 0>, <&intc 1 1 0>, <&intc 1 0 0>; interrupt-ranges = < 0 15 0>, <16 31 1>, <32 500 2>; }; fiq { compatible = "android,trusty-fiq-v1"; }; virtio { compatible = "android,trusty-virtio-v1"; }; log { compatible = "android,trusty-log-v1"; }; }; IPI: interrupt-controller { compatible = "android,CustomIPI"; #interrupt-cells = <1>; interrupt-controller; status = "disabled"; }; }; # 34 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-pcie.dtsi" 1 # 20 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-pcie.dtsi" / { pinmux@2430000 { pex_rst_c5_out_state: pex_rst_c5_out { pex_rst { nvidia,pins = "pex_l5_rst_n_pgg1"; nvidia,schmitt = <0>; nvidia,lpdr = <1>; nvidia,enable-input = <0>; nvidia,io-high-voltage = <1>; nvidia,tristate = <0>; nvidia,pull = <0>; }; }; pex_rst_c5_in_state: pex_rst_c5_in { pex_rst { nvidia,pins = "pex_l5_rst_n_pgg1"; nvidia,schmitt = <0>; nvidia,lpdr = <1>; nvidia,enable-input = <1>; nvidia,io-high-voltage = <1>; nvidia,tristate = <1>; nvidia,pull = <0>; }; }; clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { clkreq { nvidia,pins = "pex_l5_clkreq_n_pgg0"; nvidia,schmitt = <0>; nvidia,lpdr = <1>; nvidia,enable-input = <1>; nvidia,io-high-voltage = <1>; nvidia,tristate = <0>; nvidia,pull = <0>; }; }; }; hsio_p2u { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; p2u_0: p2u@03e10000 { compatible = "nvidia,phy-p2u"; reg = <0x0 0x03e10000 0x0 0x00010000>; reg-names = "base"; interrupts = <0 336 0x04>; interrupt-names = "intr"; nvidia,uphy-id = <0>; #phy-cells = <0>; }; p2u_1: p2u@03e20000 { compatible = "nvidia,phy-p2u"; reg = <0x0 0x03e20000 0x0 0x00010000>; reg-names = "base"; interrupts = <0 337 0x04>; interrupt-names = "intr"; nvidia,uphy-id = <1>; #phy-cells = <0>; }; p2u_2: p2u@03e30000 { compatible = "nvidia,phy-p2u"; reg = <0x0 0x03e30000 0x0 0x00010000>; reg-names = "base"; interrupts = <0 338 0x04>; interrupt-names = "intr"; nvidia,uphy-id = <2>; #phy-cells = <0>; }; p2u_3: p2u@03e40000 { compatible = "nvidia,phy-p2u"; reg = <0x0 0x03e40000 0x0 0x00010000>; reg-names = "base"; interrupts = <0 339 0x04>; interrupt-names = "intr"; nvidia,uphy-id = <3>; #phy-cells = <0>; }; p2u_4: p2u@03e50000 { compatible = "nvidia,phy-p2u"; reg = <0x0 0x03e50000 0x0 0x00010000>; reg-names = "base"; interrupts = <0 340 0x04>; interrupt-names = "intr"; nvidia,uphy-id = <4>; #phy-cells = <0>; }; p2u_5: p2u@03e60000 { compatible = "nvidia,phy-p2u"; reg = <0x0 0x03e60000 0x0 0x00010000>; reg-names = "base"; interrupts = <0 341 0x04>; interrupt-names = "intr"; nvidia,uphy-id = <5>; #phy-cells = <0>; }; p2u_6: p2u@03e70000 { compatible = "nvidia,phy-p2u"; reg = <0x0 0x03e70000 0x0 0x00010000>; reg-names = "base"; interrupts = <0 342 0x04>; interrupt-names = "intr"; nvidia,uphy-id = <6>; #phy-cells = <0>; }; p2u_7: p2u@03e80000 { compatible = "nvidia,phy-p2u"; reg = <0x0 0x03e80000 0x0 0x00010000>; reg-names = "base"; interrupts = <0 343 0x04>; interrupt-names = "intr"; nvidia,uphy-id = <7>; #phy-cells = <0>; }; p2u_8: p2u@03e90000 { compatible = "nvidia,phy-p2u"; reg = <0x0 0x03e90000 0x0 0x00010000>; reg-names = "base"; interrupts = <0 344 0x04>; interrupt-names = "intr"; nvidia,uphy-id = <8>; #phy-cells = <0>; }; p2u_9: p2u@03ea0000 { compatible = "nvidia,phy-p2u"; reg = <0x0 0x03ea0000 0x0 0x00010000>; reg-names = "base"; interrupts = <0 345 0x04>; interrupt-names = "intr"; nvidia,uphy-id = <9>; #phy-cells = <0>; }; p2u_10: p2u@03f30000 { compatible = "nvidia,phy-p2u"; reg = <0x0 0x03f30000 0x0 0x00010000>; reg-names = "base"; interrupts = <0 221 0x04>; interrupt-names = "intr"; nvidia,uphy-id = <10>; #phy-cells = <0>; }; p2u_11: p2u@03f40000 { compatible = "nvidia,phy-p2u"; reg = <0x0 0x03f40000 0x0 0x00010000>; reg-names = "base"; interrupts = <0 222 0x04>; interrupt-names = "intr"; nvidia,uphy-id = <11>; #phy-cells = <0>; }; }; nvhs_p2u { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; p2u_12: p2u@03eb0000 { compatible = "nvidia,phy-p2u"; reg = <0x0 0x03eb0000 0x0 0x00010000>; reg-names = "base"; interrupts = <0 346 0x04>; interrupt-names = "intr"; nvidia,uphy-id = <12>; #phy-cells = <0>; }; p2u_13: p2u@03ec0000 { compatible = "nvidia,phy-p2u"; reg = <0x0 0x03ec0000 0x0 0x00010000>; reg-names = "base"; interrupts = <0 347 0x04>; interrupt-names = "intr"; nvidia,uphy-id = <13>; #phy-cells = <0>; }; p2u_14: p2u@03ed0000 { compatible = "nvidia,phy-p2u"; reg = <0x0 0x03ed0000 0x0 0x00010000>; reg-names = "base"; interrupts = <0 348 0x04>; interrupt-names = "intr"; nvidia,uphy-id = <14>; #phy-cells = <0>; }; p2u_15: p2u@03ee0000 { compatible = "nvidia,phy-p2u"; reg = <0x0 0x03ee0000 0x0 0x00010000>; reg-names = "base"; interrupts = <0 349 0x04>; interrupt-names = "intr"; nvidia,uphy-id = <15>; #phy-cells = <0>; }; p2u_16: p2u@03ef0000 { compatible = "nvidia,phy-p2u"; reg = <0x0 0x03ef0000 0x0 0x00010000>; reg-names = "base"; interrupts = <0 350 0x04>; interrupt-names = "intr"; nvidia,uphy-id = <16>; #phy-cells = <0>; }; p2u_17: p2u@03f00000 { compatible = "nvidia,phy-p2u"; reg = <0x0 0x03f00000 0x0 0x00010000>; reg-names = "base"; interrupts = <0 351 0x04>; interrupt-names = "intr"; nvidia,uphy-id = <17>; #phy-cells = <0>; }; p2u_18: p2u@03f10000 { compatible = "nvidia,phy-p2u"; reg = <0x0 0x03f10000 0x0 0x00010000>; reg-names = "base"; interrupts = <0 203 0x04>; interrupt-names = "intr"; nvidia,uphy-id = <18>; #phy-cells = <0>; }; p2u_19: p2u@03f20000 { compatible = "nvidia,phy-p2u"; reg = <0x0 0x03f20000 0x0 0x00010000>; reg-names = "base"; interrupts = <0 220 0x04>; interrupt-names = "intr"; nvidia,uphy-id = <19>; #phy-cells = <0>; }; }; pcie_ep@14180000 { compatible = "nvidia,tegra194-pcie-ep"; power-domains = <&bpmp 21U>; reg = <0x00 0x14180000 0x0 0x00020000 0x00 0x38000000 0x0 0x02000000 0x00 0x38000000 0x0 0x00040000 0x00 0x38040000 0x0 0x00040000 0x18 0x00000000 0x4 0x00000000>; reg-names = "appl", "window1", "config", "atu_dma", "window2"; #address-cells = <3>; #size-cells = <2>; status = "disabled"; clocks = <&bpmp_clks 220U>; clock-names = "core_clk"; resets = <&bpmp_resets 121U>, <&bpmp_resets 116U>; reset-names = "core_apb_rst", "core_rst"; interrupts = <0 72 0x04>; interrupt-names = "intr"; nvidia,max-speed = <4>; nvidia,bar0-size = <0x100000>; nvidia,device-id = /bits/ 16 <0x1AD4>; nvidia,controller-id = <&bpmp 0x0>; num-lanes = <8>; nvidia,aux-clk-freq = <0x13>; nvidia,aspm-cmrt = <0x3C>; nvidia,aspm-pwr-on-t = <0x14>; nvidia,aspm-l0s-entrance-latency = <0x3>; nvidia,aspm-l1-entrance-latency = <0x5>; num-ib-windows = <2>; num-ob-windows = <8>; nvidia,margin-port-cap = <0x194>; nvidia,margin-lane-cntrl = <0x198>; nvidia,cfg-link-cap-l1sub = <0x1c4>; nvidia,event-cntr-ctrl = <0x1d8>; nvidia,event-cntr-data = <0x1dc>; nvidia,dvfs-tbl = < 204000000 204000000 204000000 408000000 204000000 204000000 408000000 666000000 204000000 408000000 666000000 1066000000 408000000 666000000 1066000000 2133000000 >; iommus = <&smmu 0x56>; dma-coherent; }; pcie_ep@14160000 { compatible = "nvidia,tegra194-pcie-ep"; power-domains = <&bpmp 18U>; reg = <0x00 0x14160000 0x0 0x00020000 0x00 0x36000000 0x0 0x02000000 0x00 0x36000000 0x0 0x00040000 0x00 0x36040000 0x0 0x00040000 0x14 0x00000000 0x4 0x00000000>; reg-names = "appl", "window1", "config", "atu_dma", "window2"; #address-cells = <3>; #size-cells = <2>; status = "disabled"; clocks = <&bpmp_clks 224U>; clock-names = "core_clk"; resets = <&bpmp_resets 125U>, <&bpmp_resets 120U>; reset-names = "core_apb_rst", "core_rst"; interrupts = <0 51 0x04>; interrupt-names = "intr"; nvidia,max-speed = <4>; nvidia,bar0-size = <0x100000>; nvidia,device-id = /bits/ 16 <0x1AD5>; nvidia,controller-id = <&bpmp 0x4>; num-lanes = <4>; nvidia,aux-clk-freq = <0x13>; nvidia,aspm-cmrt = <0x3C>; nvidia,aspm-pwr-on-t = <0x14>; nvidia,aspm-l0s-entrance-latency = <0x3>; nvidia,aspm-l1-entrance-latency = <0x5>; num-ib-windows = <2>; num-ob-windows = <8>; nvidia,margin-port-cap = <0x190>; nvidia,margin-lane-cntrl = <0x194>; nvidia,cfg-link-cap-l1sub = <0x1b0>; nvidia,event-cntr-ctrl = <0x1c4>; nvidia,event-cntr-data = <0x1c8>; nvidia,dvfs-tbl = < 204000000 204000000 204000000 408000000 204000000 204000000 408000000 800000000 204000000 408000000 800000000 1600000000 0 0 0 0 >; iommus = <&smmu 0x5A>; dma-coherent; }; pcie_ep@141a0000 { compatible = "nvidia,tegra194-pcie-ep"; power-domains = <&bpmp 17U>; reg = <0x00 0x141a0000 0x0 0x00020000 0x00 0x3a000000 0x0 0x02000000 0x00 0x3a000000 0x0 0x00040000 0x00 0x3a040000 0x0 0x00040000 0x1c 0x00000000 0x4 0x00000000>; reg-names = "appl", "window1", "config", "atu_dma", "window2"; #address-cells = <3>; #size-cells = <2>; status = "disabled"; clocks = <&bpmp_clks 225U>; clock-names = "core_clk"; resets = <&bpmp_resets 130U>, <&bpmp_resets 129U>; reset-names = "core_apb_rst", "core_rst"; interrupts = <0 53 0x04>; interrupt-names = "intr"; pinctrl-names = "pex_rst", "clkreq"; pinctrl-0 = <&pex_rst_c5_in_state>; pinctrl-1 = <&clkreq_c5_bi_dir_state>; nvidia,max-speed = <4>; nvidia,bar0-size = <0x100000>; nvidia,device-id = /bits/ 16 <0x1AD4>; nvidia,controller-id = <&bpmp 0x5>; num-lanes = <8>; nvidia,tsa-config = <0x0200b004>; nvidia,aux-clk-freq = <0x13>; nvidia,aspm-cmrt = <0x3C>; nvidia,aspm-pwr-on-t = <0x14>; nvidia,aspm-l0s-entrance-latency = <0x3>; nvidia,aspm-l1-entrance-latency = <0x5>; nvidia,host1x = <&host1x>; num-ib-windows = <2>; num-ob-windows = <8>; nvidia,margin-port-cap = <0x194>; nvidia,margin-lane-cntrl = <0x198>; nvidia,cfg-link-cap-l1sub = <0x1c4>; nvidia,event-cntr-ctrl = <0x1d8>; nvidia,event-cntr-data = <0x1dc>; nvidia,dvfs-tbl = < 204000000 204000000 204000000 408000000 204000000 204000000 408000000 666000000 204000000 408000000 666000000 1066000000 408000000 666000000 1066000000 2133000000 >; iommus = <&smmu 0x5B>; dma-coherent; }; pcie@14180000 { compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; power-domains = <&bpmp 21U>; reg = <0x00 0x14180000 0x0 0x00020000 0x00 0x38000000 0x0 0x00040000 0x00 0x38040000 0x0 0x00040000>; reg-names = "appl", "config", "atu_dma"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; num-lanes = <8>; linux,pci-domain = <0>; clocks = <&bpmp_clks 220U>, <&bpmp_clks 319U>; clock-names = "core_clk", "core_clk_m"; resets = <&bpmp_resets 121U>, <&bpmp_resets 116U>; reset-names = "core_apb_rst", "core_rst"; interrupts = <0 72 0x04>, <0 73 0x04>; interrupt-names = "intr", "msi"; iommus = <&smmu 0x56>; dma-coherent; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 0 72 0x04>; nvidia,dvfs-tbl = < 204000000 204000000 204000000 408000000 204000000 204000000 408000000 666000000 204000000 408000000 666000000 1066000000 408000000 666000000 1066000000 2133000000 >; nvidia,max-speed = <4>; nvidia,disable-aspm-states = <0xf>; nvidia,controller-id = <&bpmp 0x0>; nvidia,disable-l1-cpm; nvidia,aux-clk-freq = <0x13>; nvidia,preset-init = <0x5>; nvidia,aspm-cmrt = <0x3C>; nvidia,aspm-pwr-on-t = <0x14>; nvidia,aspm-l0s-entrance-latency = <0x3>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 0x82000000 0x0 0x40000000 0x1B 0x40000000 0x0 0xC0000000 0xc3000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>; nvidia,cfg-link-cap-l1sub = <0x1c4>; nvidia,cap-pl16g-status = <0x174>; nvidia,cap-pl16g-cap-off = <0x188>; nvidia,event-cntr-ctrl = <0x1d8>; nvidia,event-cntr-data = <0x1dc>; nvidia,margin-port-cap = <0x194>; nvidia,margin-lane-cntrl = <0x198>; nvidia,dl-feature-cap = <0x30c>; }; pcie@14100000 { compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; power-domains = <&bpmp 19U>; reg = <0x00 0x14100000 0x0 0x00020000 0x00 0x30000000 0x0 0x00040000 0x00 0x30040000 0x0 0x00040000>; reg-names = "appl", "config", "atu_dma"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; num-lanes = <1>; linux,pci-domain = <1>; clocks = <&bpmp_clks 221U>, <&bpmp_clks 320U>; clock-names = "core_clk", "core_clk_m"; resets = <&bpmp_resets 122U>, <&bpmp_resets 117U>; reset-names = "core_apb_rst", "core_rst"; interrupts = <0 45 0x04>, <0 46 0x04>; interrupt-names = "intr", "msi"; iommus = <&smmu 0x57>; dma-coherent; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 0 45 0x04>; nvidia,dvfs-tbl = < 204000000 408000000 800000000 1333000000 0 0 0 0 0 0 0 0 0 0 0 0 >; nvidia,max-speed = <4>; nvidia,disable-aspm-states = <0xf>; nvidia,controller-id = <&bpmp 0x1>; nvidia,host1x = <&host1x>; nvidia,disable-l1-cpm; nvidia,aux-clk-freq = <0x13>; nvidia,preset-init = <0x5>; nvidia,aspm-cmrt = <0x3C>; nvidia,aspm-pwr-on-t = <0x14>; nvidia,aspm-l0s-entrance-latency = <0x3>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000 0xc3000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>; nvidia,cfg-link-cap-l1sub = <0x194>; nvidia,cap-pl16g-status = <0x164>; nvidia,cap-pl16g-cap-off = <0x178>; nvidia,event-cntr-ctrl = <0x1a8>; nvidia,event-cntr-data = <0x1ac>; nvidia,margin-port-cap = <0x180>; nvidia,margin-lane-cntrl = <0x184>; nvidia,dl-feature-cap = <0x2dc>; }; pcie@14120000 { compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; power-domains = <&bpmp 19U>; reg = <0x00 0x14120000 0x0 0x00020000 0x00 0x32000000 0x0 0x00040000 0x00 0x32040000 0x0 0x00040000>; reg-names = "appl", "config", "atu_dma"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; num-lanes = <1>; linux,pci-domain = <2>; clocks = <&bpmp_clks 222U>, <&bpmp_clks 321U>; clock-names = "core_clk", "core_clk_m"; resets = <&bpmp_resets 123U>, <&bpmp_resets 118U>; reset-names = "core_apb_rst", "core_rst"; interrupts = <0 47 0x04>, <0 48 0x04>; interrupt-names = "intr", "msi"; iommus = <&smmu 0x58>; dma-coherent; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 0 47 0x04>; nvidia,dvfs-tbl = < 204000000 408000000 800000000 1333000000 0 0 0 0 0 0 0 0 0 0 0 0 >; nvidia,max-speed = <4>; nvidia,disable-aspm-states = <0xf>; nvidia,controller-id = <&bpmp 0x2>; nvidia,disable-l1-cpm; nvidia,aux-clk-freq = <0x13>; nvidia,preset-init = <0x5>; nvidia,aspm-cmrt = <0x3C>; nvidia,aspm-pwr-on-t = <0x14>; nvidia,aspm-l0s-entrance-latency = <0x3>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000 0xc3000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>; nvidia,cfg-link-cap-l1sub = <0x194>; nvidia,cap-pl16g-status = <0x164>; nvidia,cap-pl16g-cap-off = <0x178>; nvidia,event-cntr-ctrl = <0x1a8>; nvidia,event-cntr-data = <0x1ac>; nvidia,margin-port-cap = <0x180>; nvidia,margin-lane-cntrl = <0x184>; nvidia,dl-feature-cap = <0x2dc>; }; pcie@14140000 { compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; power-domains = <&bpmp 19U>; reg = <0x00 0x14140000 0x0 0x00020000 0x00 0x34000000 0x0 0x00040000 0x00 0x34040000 0x0 0x00040000>; reg-names = "appl", "config", "atu_dma"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; num-lanes = <1>; linux,pci-domain = <3>; clocks = <&bpmp_clks 223U>, <&bpmp_clks 322U>; clock-names = "core_clk", "core_clk_m"; resets = <&bpmp_resets 124U>, <&bpmp_resets 119U>; reset-names = "core_apb_rst", "core_rst"; interrupts = <0 49 0x04>, <0 50 0x04>; interrupt-names = "intr", "msi"; iommus = <&smmu 0x59>; dma-coherent; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 0 49 0x04>; nvidia,dvfs-tbl = < 204000000 408000000 800000000 1333000000 0 0 0 0 0 0 0 0 0 0 0 0 >; nvidia,max-speed = <4>; nvidia,disable-aspm-states = <0xf>; nvidia,controller-id = <&bpmp 0x3>; nvidia,disable-l1-cpm; nvidia,aux-clk-freq = <0x13>; nvidia,preset-init = <0x5>; nvidia,aspm-cmrt = <0x3C>; nvidia,aspm-pwr-on-t = <0x14>; nvidia,aspm-l0s-entrance-latency = <0x3>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 0x82000000 0x0 0x40000000 0x12 0xB0000000 0x0 0x10000000 0xc3000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>; nvidia,cfg-link-cap-l1sub = <0x194>; nvidia,cap-pl16g-status = <0x164>; nvidia,cap-pl16g-cap-off = <0x178>; nvidia,event-cntr-ctrl = <0x1a8>; nvidia,event-cntr-data = <0x1ac>; nvidia,margin-port-cap = <0x180>; nvidia,margin-lane-cntrl = <0x184>; nvidia,dl-feature-cap = <0x2dc>; }; pcie@14160000 { compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; power-domains = <&bpmp 18U>; reg = <0x00 0x14160000 0x0 0x00020000 0x00 0x36000000 0x0 0x00040000 0x00 0x36040000 0x0 0x00040000>; reg-names = "appl", "config", "atu_dma"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; num-lanes = <4>; linux,pci-domain = <4>; clocks = <&bpmp_clks 224U>, <&bpmp_clks 323U>; clock-names = "core_clk", "core_clk_m"; resets = <&bpmp_resets 125U>, <&bpmp_resets 120U>; reset-names = "core_apb_rst", "core_rst"; interrupts = <0 51 0x04>, <0 52 0x04>; interrupt-names = "intr", "msi"; iommus = <&smmu 0x5A>; dma-coherent; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 0 51 0x04>; nvidia,dvfs-tbl = < 204000000 204000000 204000000 408000000 204000000 204000000 408000000 800000000 204000000 408000000 800000000 1600000000 0 0 0 0 >; nvidia,max-speed = <4>; nvidia,disable-aspm-states = <0xf>; nvidia,controller-id = <&bpmp 0x4>; nvidia,disable-l1-cpm; nvidia,aux-clk-freq = <0x13>; nvidia,preset-init = <0x5>; nvidia,aspm-cmrt = <0x3C>; nvidia,aspm-pwr-on-t = <0x14>; nvidia,aspm-l0s-entrance-latency = <0x3>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xC0000000 0xc3000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>; nvidia,cfg-link-cap-l1sub = <0x1b0>; nvidia,cap-pl16g-status = <0x174>; nvidia,cap-pl16g-cap-off = <0x188>; nvidia,event-cntr-ctrl = <0x1c4>; nvidia,event-cntr-data = <0x1c8>; nvidia,margin-port-cap = <0x190>; nvidia,margin-lane-cntrl = <0x194>; nvidia,dl-feature-cap = <0x2f8>; }; pcie@141a0000 { compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; power-domains = <&bpmp 17U>; reg = <0x00 0x141a0000 0x0 0x00020000 0x00 0x3a000000 0x0 0x00040000 0x00 0x3a040000 0x0 0x00040000>; reg-names = "appl", "config", "atu_dma"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; num-lanes = <8>; linux,pci-domain = <5>; clocks = <&bpmp_clks 225U>, <&bpmp_clks 324U>; clock-names = "core_clk", "core_clk_m"; resets = <&bpmp_resets 130U>, <&bpmp_resets 129U>; reset-names = "core_apb_rst", "core_rst"; interrupts = <0 53 0x04>, <0 54 0x04>; interrupt-names = "intr", "msi"; pinctrl-names = "pex_rst", "clkreq"; pinctrl-0 = <&pex_rst_c5_out_state>; pinctrl-1 = <&clkreq_c5_bi_dir_state>; iommus = <&smmu 0x5B>; dma-coherent; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &intc 0 53 0x04>; nvidia,dvfs-tbl = < 204000000 204000000 204000000 408000000 204000000 204000000 408000000 666000000 204000000 408000000 666000000 1066000000 408000000 666000000 1066000000 2133000000 >; nvidia,max-speed = <4>; nvidia,disable-aspm-states = <0xf>; nvidia,controller-id = <&bpmp 0x5>; nvidia,tsa-config = <0x0200b004>; nvidia,disable-l1-cpm; nvidia,aux-clk-freq = <0x13>; nvidia,preset-init = <0x5>; nvidia,aspm-cmrt = <0x3C>; nvidia,aspm-pwr-on-t = <0x14>; nvidia,aspm-l0s-entrance-latency = <0x3>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xC0000000 0xc3000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>; nvidia,cfg-link-cap-l1sub = <0x1c4>; nvidia,cap-pl16g-status = <0x174>; nvidia,cap-pl16g-cap-off = <0x188>; nvidia,event-cntr-ctrl = <0x1d8>; nvidia,event-cntr-data = <0x1dc>; nvidia,margin-port-cap = <0x194>; nvidia,margin-lane-cntrl = <0x198>; nvidia,dl-feature-cap = <0x30c>; }; }; # 35 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-eqos.dtsi" 1 # 39 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-eqos.dtsi" / { pinmux@2430000 { eqos_txrx_tri_state_idle: eqos_idle { eqos { nvidia,pins = "eqos_td3_pe4","eqos_td2_pe3", "eqos_td1_pe2","eqos_td0_pe1", "eqos_txc_pe0","eqos_tx_ctl_pe5", "eqos_rd3_pf1","eqos_rd2_pf0", "eqos_rd1_pe7","eqos_rd0_pe6", "eqos_rxc_pf3","eqos_rx_ctl_pf2"; nvidia,tristate = <1>; }; }; eqos_txrx_tri_state_default: eqos_default { eqos { nvidia,pins = "eqos_td3_pe4","eqos_td2_pe3", "eqos_td1_pe2","eqos_td0_pe1", "eqos_txc_pe0","eqos_tx_ctl_pe5", "eqos_rd3_pf1","eqos_rd2_pf0", "eqos_rd1_pe7","eqos_rd0_pe6", "eqos_rxc_pf3","eqos_rx_ctl_pf2"; nvidia,tristate = <0>; }; }; }; ether_qos@2490000 { compatible = "nvidia,eqos"; reg = <0x0 0x02490000 0x0 0x10000>; reg-names = "eqos_base"; interrupts = <0 194 0x4>, <0 195 0x4>, <0 190 0x4>, <0 186 0x4>, <0 191 0x4>, <0 187 0x4>, <0 192 0x4>, <0 188 0x4>, <0 193 0x4>, <0 189 0x4>; clocks = <&bpmp_clks 288U>, <&bpmp_clks 32U>, <&bpmp_clks 34U>, <&bpmp_clks 33U>, <&bpmp_clks 35U>, <&bpmp_clks 8U>; clock-names = "pllrefe_vcoout", "eqos_axi", "eqos_rx", "eqos_ptp_ref", "eqos_tx", "axi_cbb"; resets = <&bpmp_resets 17U>; reset-names = "eqos_rst"; nvidia,local-mac-address = <0x00 0x00 0x00 0x00 0x00 0x00>; iommus = <&smmu 0x14>; iommu-group-id = <0x2>; dma-coherent; nvidia,csr_clock_speed = <0x19>; nvidia,iso_bw = <81920>; nvidia,rx_riwt = <60>; nvidia,rx_frames = <16>; nvidia,slot_intvl_val = <0x07C>; status = "disabled"; pinctrl-names = "idle", "default"; pinctrl-0 = <&eqos_txrx_tri_state_idle>; pinctrl-1 = <&eqos_txrx_tri_state_default>; eqos_cool_dev: eqos-cool-dev { cooling-min-state = <0>; cooling-max-state = <5>; #cooling-cells = <2>; }; }; }; # 36 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-uart.dtsi" 1 # 16 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-uart.dtsi" / { aliases { serial0 = &uarta; serial1 = &uartb; serial2 = &uartc; serial3 = &uartd; serial4 = &uarte; serial5 = &uartf; serial6 = &uartg; serial7 = &uarth; }; uarta: serial@3100000 { compatible = "nvidia,tegra186-hsuart"; iommus = <&smmu 0x20>; dma-coherent; reg = <0x0 0x03100000 0x0 0x10000>; reg-shift = <2>; interrupts = <0 112 0x04>; nvidia,memory-clients = <14>; dmas = <&gpcdma 8>, <&gpcdma 8>; dma-names = "rx", "tx"; clocks = <&bpmp_clks 155U>, <&bpmp_clks 102U>; clock-names = "serial", "parent"; resets = <&bpmp_resets 100U>; reset-names = "serial"; status = "disabled"; }; uartb: serial@3110000 { compatible = "nvidia,tegra186-hsuart"; iommus = <&smmu 0x20>; dma-coherent; reg = <0x0 0x03110000 0x0 0x10000>; reg-shift = <2>; interrupts = <0 113 0x04>; nvidia,memory-clients = <14>; dmas = <&gpcdma 9>, <&gpcdma 9>; dma-names = "rx", "tx"; clocks = <&bpmp_clks 156U>, <&bpmp_clks 102U>; clock-names = "serial", "parent"; resets = <&bpmp_resets 101U>; reset-names = "serial"; status = "disabled"; }; uartc: serial@c280000 { compatible = "nvidia,tegra186-hsuart"; iommus = <&smmu 0x20>; dma-coherent; reg = <0x0 0xc280000 0x0 0x10000>; reg-shift = <2>; interrupts = <0 114 0x04>; nvidia,memory-clients = <14>; dmas = <&gpcdma 3>, <&gpcdma 3>; dma-names = "rx", "tx"; clocks = <&bpmp_clks 157U>, <&bpmp_clks 102U>; clock-names = "serial", "parent"; resets = <&bpmp_resets 102U>; reset-names = "serial"; status = "disabled"; }; uartd: serial@3130000 { compatible = "nvidia,tegra186-hsuart"; iommus = <&smmu 0x20>; dma-coherent; reg = <0x0 0x03130000 0x0 0x10000>; reg-shift = <2>; interrupts = <0 115 0x04>; nvidia,memory-clients = <14>; dmas = <&gpcdma 19>, <&gpcdma 19>; dma-names = "rx", "tx"; clocks = <&bpmp_clks 158U>, <&bpmp_clks 102U>; clock-names = "serial", "parent"; resets = <&bpmp_resets 103U>; reset-names = "serial"; status = "disabled"; }; uarte: serial@3140000 { compatible = "nvidia,tegra186-hsuart"; iommus = <&smmu 0x20>; dma-coherent; reg = <0x0 0x03140000 0x0 0x10000>; reg-shift = <2>; interrupts = <0 116 0x04>; nvidia,memory-clients = <14>; dmas = <&gpcdma 20>, <&gpcdma 20>; dma-names = "rx", "tx"; clocks = <&bpmp_clks 159U>, <&bpmp_clks 102U>; clock-names = "serial", "parent"; resets = <&bpmp_resets 104U>; reset-names = "serial"; status = "disabled"; }; uartf: serial@3150000 { compatible = "nvidia,tegra186-hsuart"; iommus = <&smmu 0x20>; dma-coherent; reg = <0x0 0x03150000 0x0 0x10000>; reg-shift = <2>; interrupts = <0 117 0x04>; nvidia,memory-clients = <14>; dmas = <&gpcdma 12>, <&gpcdma 12>; dma-names = "rx", "tx"; clocks = <&bpmp_clks 160U>, <&bpmp_clks 102U>; clock-names = "serial", "parent"; resets = <&bpmp_resets 105U>; reset-names = "serial"; status = "disabled"; }; uartg: serial@c290000 { compatible = "nvidia,tegra186-hsuart"; iommus = <&smmu 0x20>; dma-coherent; reg = <0x0 0xc290000 0x0 0x10000>; reg-shift = <2>; interrupts = <0 118 0x04>; nvidia,memory-clients = <14>; dmas = <&gpcdma 2>, <&gpcdma 2>; dma-names = "rx", "tx"; clocks = <&bpmp_clks 161U>, <&bpmp_clks 102U>; clock-names = "serial", "parent"; resets = <&bpmp_resets 106U>; reset-names = "serial"; status = "disabled"; }; uarth: serial@3170000 { compatible = "nvidia,tegra186-hsuart"; iommus = <&smmu 0x20>; dma-coherent; reg = <0x0 0x3170000 0x0 0x10000>; reg-shift = <2>; interrupts = <0 207 0x04>; nvidia,memory-clients = <14>; dmas = <&gpcdma 13>, <&gpcdma 13>; dma-names = "rx", "tx"; clocks = <&bpmp_clks 190U>, <&bpmp_clks 102U>; clock-names = "serial", "parent"; resets = <&bpmp_resets 107U>; reset-names = "serial"; status = "disabled"; }; combined-uart { compatible = "nvidia,tegra186-combined-uart"; reg = <0x0 0x3c10000 0x0 0x4 0x0 0xc168000 0x0 0x4 0x0 0x3c00000 0x0 0x1000>; interrupts = <0 120 0x04>; status = "disabled"; }; }; # 37 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-sdhci.dtsi" 1 # 20 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-sdhci.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-pin-drive-sdmmc-common.dtsi" 1 # 15 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-pin-drive-sdmmc-common.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/tegra/kernel-include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h" 1 # 16 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-pin-drive-sdmmc-common.dtsi" 2 / { pmc@c360000 { sdmmc1_e_33V_enable: sdmmc1_e_33V_enable { sdmmc1 { pins = "sdmmc1-hv"; nvidia,power-source-voltage = <1>; }; }; sdmmc1_e_33V_disable: sdmmc1_e_33V_disable { sdmmc1 { pins = "sdmmc1-hv"; nvidia,power-source-voltage = <0>; }; }; sdmmc3_e_33V_enable: sdmmc3_e_33V_enable { sdmmc3 { pins = "sdmmc3-hv"; nvidia,power-source-voltage = <1>; }; }; sdmmc3_e_33V_disable: sdmmc3_e_33V_disable { sdmmc3 { pins = "sdmmc3-hv"; nvidia,power-source-voltage = <0>; }; }; }; }; # 21 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-sdhci.dtsi" 2 / { aliases { sdhci3 = &sdmmc4; sdhci2 = &sdmmc3; sdhci0 = &sdmmc1; }; sdmmc4: sdhci@3460000 { compatible = "nvidia,tegra194-sdhci"; reg = <0x0 0x3460000 0x0 0x00020000>; interrupts = < 0 65 0x04>; iommus = <&smmu 0x17>; dma-coherent; max-clk-limit = <200000000>; ddr-clk-limit = <51000000>; bus-width = <8>; only-1-8-v; ignore-pm-notify; keep-power-in-suspend; non-removable; cap-mmc-highspeed; cap-sd-highspeed; mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; nvidia,min-tap-delay = <96>; nvidia,max-tap-delay = <139>; nvidia,en-periodic-cflush; nvidia,periodic-cflush-to = <10>; resets = <&bpmp_resets 85U>; reset-names = "sdhci"; pll_source = "pll_p", "pll_c4_out0_lj"; nvidia,set-parent-clk; nvidia,parent_clk_list = "pll_p", "pll_p", "NULL", "NULL", "NULL", "NULL", "NULL", "NULL", "pll_p", "pll_c4_out0_lj", "pll_c4_out0_lj"; clocks = <&bpmp_clks 123U>, <&bpmp_clks 102U>, <&bpmp_clks 237U>, <&bpmp_clks 219U>; clock-names = "sdmmc", "pll_p", "pll_c4_out0_lj", "sdmmc_legacy_tm"; status = "disabled"; }; sdmmc3: sdhci@3440000 { compatible = "nvidia,tegra194-sdhci"; reg = <0x0 0x3440000 0x0 0x00020000>; interrupts = < 0 64 0x04>; iommus = <&smmu 0x18>; dma-coherent; max-clk-limit = <208000000>; bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; sd-uhs-sdr104; sd-uhs-sdr50; sd-uhs-sdr25; sd-uhs-sdr12; mmc-ddr-1_8v; mmc-hs200-1_8v; cd-inverted; nvidia,min-tap-delay = <96>; nvidia,max-tap-delay = <139>; nvidia,vqmmc-always-on; pwrdet-support; pinctrl-names = "sdmmc_e_33v_enable", "sdmmc_e_33v_disable"; pinctrl-0 = <&sdmmc3_e_33V_enable>; pinctrl-1 = <&sdmmc3_e_33V_disable>; ignore-pm-notify; resets = <&bpmp_resets 84U>; reset-names = "sdhci"; pll_source = "pll_p", "pll_c4_muxed"; nvidia,set-parent-clk; nvidia,parent_clk_list = "pll_p", "pll_p", "pll_p", "pll_p", "pll_p", "pll_c4_muxed", "pll_c4_muxed", "pll_c4_muxed", "pll_c4_muxed", "pll_c4_muxed", "NULL"; clocks = <&bpmp_clks 122U>, <&bpmp_clks 102U>, <&bpmp_clks 241U>, <&bpmp_clks 219U>; clock-names = "sdmmc", "pll_p", "pll_c4_muxed", "sdmmc_legacy_tm"; uhs-mask = <0x08>; nvidia,en-periodic-calib; status = "disabled"; }; sdmmc1: sdhci@3400000 { compatible = "nvidia,tegra194-sdhci"; reg = <0x0 0x3400000 0x0 0x00020000>; interrupts = < 0 62 0x04>; iommus = <&smmu 0x1a>; dma-coherent; max-clk-limit = <208000000>; bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; sd-uhs-sdr104; sd-uhs-sdr50; sd-uhs-sdr25; sd-uhs-sdr12; mmc-ddr-1_8v; mmc-hs200-1_8v; nvidia,vqmmc-always-on; cd-inverted; nvidia,min-tap-delay = <96>; nvidia,max-tap-delay = <139>; pwrdet-support; pinctrl-names = "sdmmc_e_33v_enable", "sdmmc_e_33v_disable"; pinctrl-0 = <&sdmmc1_e_33V_enable>; pinctrl-1 = <&sdmmc1_e_33V_disable>; ignore-pm-notify; resets = <&bpmp_resets 82U>; reset-names = "sdhci"; pll_source = "pll_p", "pll_c4_muxed"; nvidia,set-parent-clk; nvidia,parent_clk_list = "pll_p", "pll_p", "pll_p", "pll_p", "pll_p", "pll_c4_muxed", "pll_c4_muxed", "pll_c4_muxed", "pll_c4_muxed", "pll_c4_muxed", "NULL"; clocks = <&bpmp_clks 120U>, <&bpmp_clks 102U>, <&bpmp_clks 241U>, <&bpmp_clks 219U>; clock-names = "sdmmc", "pll_p", "pll_c4_muxed", "sdmmc_legacy_tm"; uhs-mask = <0x08>; nvidia,en-periodic-calib; status = "disabled"; }; }; # 38 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-ufshc.dtsi" 1 # 16 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-ufshc.dtsi" / { pmc@c360000 { ufs_dpd_enable: dpd-enable { ufs { pins = "ufs"; low-power-enable; }; }; ufs_dpd_disable: dpd-disable { ufs { pins = "ufs"; low-power-disable; }; }; }; tegra_ufs: ufshci@2450000 { compatible = "tegra,ufs_variant"; reg = <0x0 0x02450000 0x0 0x4000>; interrupts = < 0 44 0x04 >; iommus = <&smmu 0x15>; dma-coherent; clocks = <&bpmp_clks 73U>, <&bpmp_clks 78U>, <&bpmp_clks 80U> , <&bpmp_clks 74U>, <&bpmp_clks 76U>, <&bpmp_clks 77U>, <&bpmp_clks 75U>, <&bpmp_clks 79U>, <&bpmp_clks 164U>, <&bpmp_clks 163U>, <&bpmp_clks 102U>, <&bpmp_clks 14U>, <&bpmp_clks 151U>, <&bpmp_clks 121U>; clock-names = "mphy_core_pll_fixed", "mphy_l0_tx_symb", "mphy_tx_1mhz_ref", "mphy_l0_rx_ana", "mphy_l0_rx_symb", "mphy_l0_tx_ls_3xbit", "mphy_l0_rx_ls_bit", "mphy_l1_rx_ana", "ufshc", "ufsdev_ref", "pll_p", "clk_m", "mphy_force_ls_mode", "uphy_pll3"; resets = <&bpmp_resets 39U>, <&bpmp_resets 40U>, <&bpmp_resets 41U>, <&bpmp_resets 42U>, <&bpmp_resets 38U>, <&bpmp_resets 108U>, <&bpmp_resets 109U>, <&bpmp_resets 110U>; reset-names = "mphy-l0-rx-rst", "mphy-l0-tx-rst", "mphy-l1-rx-rst", "mphy-l1-tx-rst", "mphy-clk-ctl-rst", "ufs-rst", "ufs-axi-m-rst", "ufshc-lp-rst"; nvidia,enable-x2-config; nvidia,enable-scramble; nvidia,mask-fast-auto-mode; nvidia,max-hs-gear = <3>; nvidia,max-pwm-gear = <4>; vcc-max-microamp = <0>; vccq-max-microamp = <0>; vccq2-max-microamp = <0>; nvidia,configure-uphy-pll3; pinctrl-names = "ufs_dpd_enable", "ufs_dpd_disable"; pinctrl-0 = <&ufs_dpd_enable>; pinctrl-1 = <&ufs_dpd_disable>; status = "disabled"; ufs_variant { compatible = "tegra,ufs_variant"; }; }; }; # 39 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-spi.dtsi" 1 # 19 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-spi.dtsi" / { aliases { spi0 = &spi0; spi1 = &spi1; spi2 = &spi2; spi6 = &qspi0; spi7 = &qspi1; }; spi0: spi@3210000 { compatible = "nvidia,tegra186-spi"; reg = <0x0 0x03210000 0x0 0x10000>; interrupts = <0 36 0x04>; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x20>; dma-coherent; dmas = <&gpcdma 15>, <&gpcdma 15>; dma-names = "rx", "tx"; spi-max-frequency = <65000000>; nvidia,clk-parents = "pll_p", "clk_m"; clocks = <&bpmp_clks 135U>, <&bpmp_clks 102U>, <&bpmp_clks 14U>; clock-names = "spi", "pll_p", "clk_m"; resets = <&bpmp_resets 91U>; reset-names = "spi"; status = "disabled"; }; spi1: spi@c260000 { compatible = "nvidia,tegra186-spi"; reg = <0x0 0x0c260000 0x0 0x10000>; interrupts = <0 37 0x04>; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x20>; dma-coherent; dmas = <&gpcdma 16>, <&gpcdma 16>; dma-names = "rx", "tx"; spi-max-frequency = <65000000>; nvidia,clk-parents = "pll_p", "osc"; clocks = <&bpmp_clks 136U>, <&bpmp_clks 94U>, <&bpmp_clks 91U>; clock-names = "spi", "pll_p", "osc"; resets = <&bpmp_resets 92U>; reset-names = "spi"; status = "disabled"; }; spi2: spi@3230000 { compatible = "nvidia,tegra186-spi"; reg = <0x0 0x03230000 0x0 0x10000>; interrupts = <0 38 0x04>; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x20>; dma-coherent; dmas = <&gpcdma 17>, <&gpcdma 17>; dma-names = "rx", "tx"; spi-max-frequency = <65000000>; nvidia,clk-parents = "pll_p", "clk_m"; clocks = <&bpmp_clks 137U>, <&bpmp_clks 102U>, <&bpmp_clks 14U>; clock-names = "spi", "pll_p", "clk_m"; resets = <&bpmp_resets 93U>; reset-names = "spi"; status = "disabled"; }; qspi0: spi@3270000 { compatible = "nvidia,tegra186-qspi"; reg = <0x0 0x3270000 0x0 0x10000>; interrupts = < 0 35 0x04 >; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x20>; dma-coherent; dmas = <&gpcdma 5>, <&gpcdma 5>; dma-names = "rx", "tx"; spi-max-frequency = <204000000>; nvidia,clk-parents = "pllc", "pll_p"; clocks = <&bpmp_clks 192U>, <&bpmp_clks 194U>, <&bpmp_clks 314U>, <&bpmp_clks 102U>; clock-names = "qspi", "qspi_out", "pllc", "pll_p"; resets = <&bpmp_resets 76U>; reset-names = "qspi"; status = "disabled"; }; qspi1: spi@3300000 { compatible = "nvidia,tegra186-qspi"; reg = <0x0 0x3300000 0x0 0x10000>; interrupts = < 0 39 0x04 >; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x20>; dma-coherent; dmas = <&gpcdma 6>, <&gpcdma 6>; dma-names = "rx", "tx"; spi-max-frequency = <204000000>; nvidia,clk-parents = "pllc", "pll_p"; clocks = <&bpmp_clks 193U>, <&bpmp_clks 195U>, <&bpmp_clks 314U>, <&bpmp_clks 102U>; clock-names = "qspi", "qspi_out", "pllc", "pll_p"; resets = <&bpmp_resets 77U>; reset-names = "qspi"; status = "disabled"; }; }; # 40 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-pwm.dtsi" 1 # 19 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-pwm.dtsi" / { tegra_pwm1: pwm@3280000 { compatible = "nvidia,tegra194-pwm"; reg = <0x0 0x3280000 0x0 0x10000>; nvidia,hw-instance-id = <0x0>; clocks = <&bpmp_clks 105U>; clock-names = "pwm"; #pwm-cells = <2>; resets = <&bpmp_resets 68U>; reset-names = "pwm"; status = "disabled"; }; tegra_pwm2: pwm@3290000 { compatible = "nvidia,tegra194-pwm"; reg = <0x0 0x3290000 0x0 0x10000>; nvidia,hw-instance-id = <0x1>; clocks = <&bpmp_clks 106U>; clock-names = "pwm"; #pwm-cells = <2>; resets = <&bpmp_resets 69U>; reset-names = "pwm"; status = "disabled"; }; tegra_pwm3: pwm@32a0000 { compatible = "nvidia,tegra194-pwm"; reg = <0x0 0x32a0000 0x0 0x10000>; nvidia,hw-instance-id = <0x2>; clocks = <&bpmp_clks 107U>; clock-names = "pwm"; #pwm-cells = <2>; resets = <&bpmp_resets 70U>; reset-names = "pwm"; status = "disabled"; }; tegra_pwm4: pwm@c340000 { compatible = "nvidia,tegra194-pwm"; reg = <0x0 0xc340000 0x0 0x10000>; nvidia,hw-instance-id = <0x3>; clocks = <&bpmp_clks 108U>; clock-names = "pwm"; #pwm-cells = <2>; resets = <&bpmp_resets 71U>; reset-names = "pwm"; status = "disabled"; }; tegra_pwm5: pwm@32c0000 { compatible = "nvidia,tegra194-pwm"; reg = <0x0 0x32c0000 0x0 0x10000>; nvidia,hw-instance-id = <0x4>; clocks = <&bpmp_clks 109U>; clock-names = "pwm"; #pwm-cells = <2>; resets = <&bpmp_resets 72U>; reset-names = "pwm"; status = "disabled"; }; tegra_pwm6: pwm@32d0000 { compatible = "nvidia,tegra194-pwm"; reg = <0x0 0x32d0000 0x0 0x10000>; nvidia,hw-instance-id = <0x5>; clocks = <&bpmp_clks 110U>; clock-names = "pwm"; #pwm-cells = <2>; resets = <&bpmp_resets 73U>; reset-names = "pwm"; status = "disabled"; }; tegra_pwm7: pwm@32e0000 { compatible = "nvidia,tegra194-pwm"; reg = <0x0 0x32e0000 0x0 0x10000>; nvidia,hw-instance-id = <0x6>; clocks = <&bpmp_clks 111U>; clock-names = "pwm"; #pwm-cells = <2>; resets = <&bpmp_resets 74U>; reset-names = "pwm"; status = "disabled"; }; tegra_pwm8: pwm@32f0000 { compatible = "nvidia,tegra194-pwm"; reg = <0x0 0x32f0000 0x0 0x10000>; nvidia,hw-instance-id = <0x7>; clocks = <&bpmp_clks 112U>; clock-names = "pwm"; #pwm-cells = <2>; resets = <&bpmp_resets 75U>; reset-names = "pwm"; status = "disabled"; }; }; # 41 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-i2c.dtsi" 1 # 21 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-i2c.dtsi" / { aliases { i2c0 = &gen1_i2c; i2c1 = &gen2_i2c; i2c2 = &cam_i2c; i2c3 = &dp_aux_ch1_i2c; i2c4 = &pwr_i2c; i2c5 = &dp_aux_ch0_i2c; i2c6 = &dp_aux_ch2_i2c; i2c7 = &gen8_i2c; i2c8 = &dp_aux_ch3_i2c; }; gen1_i2c: i2c@3160000 { #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x20>; dma-coherent; compatible = "nvidia,tegra194-i2c"; reg = <0x0 0x3160000 0x0 0x100>; nvidia,hw-instance-id = <0x0>; interrupts = <0 25 0x04>; scl-gpio = <&tegra_main_gpio ((8 * 8) + 3) 0>; sda-gpio = <&tegra_main_gpio ((8 * 8) + 4) 0>; status = "disabled"; clock-frequency = <400000>; clocks = <&bpmp_clks 48U &bpmp_clks 102U>; clock-names = "div-clk", "parent"; resets = <&bpmp_resets 24U>; reset-names = "i2c"; dmas = <&gpcdma 21>, <&gpcdma 21>; dma-names = "rx", "tx"; }; gen2_i2c: i2c@c240000 { #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x20>; dma-coherent; compatible = "nvidia,tegra194-i2c"; reg = <0x0 0xc240000 0x0 0x100>; nvidia,hw-instance-id = <0x1>; interrupts = <0 26 0x04>; scl-gpio = <&tegra_aon_gpio ((2 * 8) + 7) 0>; sda-gpio = <&tegra_aon_gpio ((3 * 8) + 0) 0>; status = "disabled"; clock-frequency = <100000>; clocks = <&bpmp_clks 49U &bpmp_clks 102U>; clock-names = "div-clk", "parent"; resets = <&bpmp_resets 29U>; reset-names = "i2c"; dmas = <&gpcdma 22>, <&gpcdma 22>; dma-names = "rx", "tx"; }; cam_i2c: i2c@3180000 { #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x20>; dma-coherent; compatible = "nvidia,tegra194-i2c"; reg = <0x0 0x3180000 0x0 0x100>; nvidia,hw-instance-id = <0x2>; interrupts = <0 27 0x04>; scl-gpio = <&tegra_main_gpio ((15 * 8) + 2) 0>; sda-gpio = <&tegra_main_gpio ((15 * 8) + 3) 0>; status = "disabled"; clock-frequency = <400000>; clocks = <&bpmp_clks 50U &bpmp_clks 102U>; clock-names = "div-clk", "parent"; resets = <&bpmp_resets 30U>; reset-names = "i2c"; dmas = <&gpcdma 23>, <&gpcdma 23>; dma-names = "rx", "tx"; }; dp_aux_ch1_i2c: i2c@3190000 { #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x20>; dma-coherent; compatible = "nvidia,tegra194-i2c"; reg = <0x0 0x3190000 0x0 0x100>; nvidia,hw-instance-id = <0x3>; interrupts = <0 28 0x04>; status = "disabled"; clock-frequency = <100000>; clocks = <&bpmp_clks 51U &bpmp_clks 102U>; clock-names = "div-clk", "parent"; resets = <&bpmp_resets 31U>; reset-names = "i2c"; dmas = <&gpcdma 26>, <&gpcdma 26>; dma-names = "rx", "tx"; }; pwr_i2c: bpmp_i2c { #address-cells = <1>; #size-cells = <0>; compatible = "nvidia,tegra186-bpmp-i2c"; status = "disabled"; nvidia,hw-instance-id = <0x4>; adapter = <5>; }; dp_aux_ch0_i2c: i2c@31b0000 { #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x20>; dma-coherent; compatible = "nvidia,tegra194-i2c"; reg = <0x0 0x31b0000 0x0 0x100>; nvidia,hw-instance-id = <0x5>; interrupts = <0 30 0x04>; status = "disabled"; clock-frequency = <100000>; clocks = <&bpmp_clks 52U &bpmp_clks 102U>; clock-names = "div-clk", "parent"; resets = <&bpmp_resets 32U>; reset-names = "i2c"; dmas = <&gpcdma 30>, <&gpcdma 30>; dma-names = "rx", "tx"; }; dp_aux_ch2_i2c: i2c@31c0000 { #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x20>; dma-coherent; compatible = "nvidia,tegra194-i2c"; reg = <0x0 0x31c0000 0x0 0x100>; nvidia,hw-instance-id = <0x6>; interrupts = <0 31 0x04>; status = "disabled"; clock-frequency = <100000>; clocks = <&bpmp_clks 53U &bpmp_clks 102U>; clock-names = "div-clk", "parent"; resets = <&bpmp_resets 33U>; reset-names = "i2c"; dmas = <&gpcdma 27>, <&gpcdma 27>; dma-names = "rx", "tx"; }; gen8_i2c: i2c@c250000 { #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x20>; dma-coherent; compatible = "nvidia,tegra194-i2c"; reg = <0x0 0xc250000 0x0 0x100>; nvidia,hw-instance-id = <0x7>; interrupts = <0 32 0x04>; scl-gpio = <&tegra_aon_gpio ((3 * 8) + 1) 0>; sda-gpio = <&tegra_aon_gpio ((3 * 8) + 2) 0>; status = "disabled"; clock-frequency = <400000>; clocks = <&bpmp_clks 54U &bpmp_clks 102U>; clock-names = "div-clk", "parent"; resets = <&bpmp_resets 34U>; reset-names = "i2c"; dmas = <&gpcdma 0>, <&gpcdma 0>; dma-names = "rx", "tx"; }; dp_aux_ch3_i2c: i2c@31e0000 { #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x20>; dma-coherent; compatible = "nvidia,tegra194-i2c"; reg = <0x0 0x31e0000 0x0 0x100>; nvidia,hw-instance-id = <0x8>; interrupts = <0 33 0x04>; status = "disabled"; clock-frequency = <100000>; clocks = <&bpmp_clks 55U &bpmp_clks 102U>; clock-names = "div-clk", "parent"; resets = <&bpmp_resets 35U>; reset-names = "i2c"; dmas = <&gpcdma 31>, <&gpcdma 31>; dma-names = "rx", "tx"; }; }; # 42 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-can.dtsi" 1 # 20 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-can.dtsi" / { mttcan0: mttcan@c310000 { compatible = "nvidia,tegra194-mttcan"; reg = <0x00 0x0c310000 0x00 0x400>, <0x00 0x0c311000 0x00 0x32>, <0x00 0x0c312000 0x00 0x1000>; reg-names = "can-regs", "glue-regs", "msg-ram"; interrupts = <0 40 0x04 >; pll_source = "pllaon"; clocks = <&bpmp_clks 284U>, <&bpmp_clks 10U>, <&bpmp_clks 9U>, <&bpmp_clks 94U>; clock-names = "can_core", "can_host","can","pllaon"; resets = <&bpmp_resets 4U>; reset-names = "can"; mram-params = <0 16 16 32 0 0 16 16 16>; tx-config = <0 16 0 64>; rx-config = <64 64 64>; status = "disabled"; }; mttcan1: mttcan@c320000 { compatible = "nvidia,tegra194-mttcan"; reg = <0x00 0x0c320000 0x00 0x400>, <0x00 0x0c321000 0x00 0x32>, <0x00 0x0c322000 0x00 0x1000>; reg-names = "can-regs", "glue-regs", "msg-ram"; interrupts = <0 42 0x04 >; pll_source = "pllaon"; clocks = <&bpmp_clks 285U>, <&bpmp_clks 12U>, <&bpmp_clks 11U>, <&bpmp_clks 94U>; clock-names = "can_core", "can_host","can","pllaon"; resets = <&bpmp_resets 5U>; reset-names = "can"; mram-params = <0 16 16 32 0 0 16 16 16>; tx-config = <0 16 0 64>; rx-config = <64 64 64>; status = "disabled"; }; }; # 43 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-audio.dtsi" 1 # 19 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-audio.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-include/dt-bindings/interrupt-controller/tegra-t19x-agic.h" 1 # 20 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-audio.dtsi" 2 / { sound { iommus = <&smmu 0x1e>; dma-mask = <0x0 0x5e000000>; iommu-resv-regions = <0x0 0x0 0x0 0x40000000 0x0 0x60000000 0xffffffff 0xffffffff>; iommu-group-id = <0x2>; status = "disabled"; }; sound_ref { iommus = <&smmu 0x1e>; dma-mask = <0x0 0x5e000000>; iommu-resv-regions = <0x0 0x0 0x0 0x40000000 0x0 0x60000000 0xffffffff 0xffffffff>; iommu-group-id = <0x2>; status = "disabled"; }; aconnect@2a41000 { compatible = "nvidia,tegra210-aconnect"; clocks = <&bpmp_clks 6U>, <&bpmp_clks 5U>; power-domains = <&bpmp 1U>; clock-names = "ape", "apb2ape"; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; tegra_agic: agic-controller@2a41000 { compatible = "nvidia,tegra186-agic"; #interrupt-cells = <4>; interrupt-controller; reg = <0x0 0x02a41000 0x0 0x1000>, <0x0 0x02a42000 0x0 0x1000>; interrupts = <0 145 ((((1 << (4)) - 1) << 8) | 0x00000004)>; clocks = <&bpmp_clks 6U>; clock-names = "clk"; status = "disabled"; }; tegra_agic_1: agic-controller@2a51000 { compatible = "nvidia,tegra186-agic"; interrupt-controller; #interrupt-cells = <4>; reg = <0x0 0x02a51000 0x0 0x1000>, <0x0 0x02a52000 0x0 0x1000>; interrupts = <0 146 ((((1 << (4)) - 1) << 8) | 0x00000004)>; clocks = <&bpmp_clks 6U>; clock-names = "clk"; status = "disabled"; }; tegra_agic_2: agic-controller@2a61000 { compatible = "nvidia,tegra186-agic"; interrupt-controller; #interrupt-cells = <4>; reg = <0x0 0x02a61000 0x0 0x1000>, <0x0 0x02a62000 0x0 0x1000>; interrupts = <0 147 ((((1 << (4)) - 1) << 8) | 0x00000004)>; clocks = <&bpmp_clks 6U>; clock-names = "clk"; status = "disabled"; }; adsp@2993000 { compatible = "nvidia,tegra18x-adsp"; interrupt-parent = <&tegra_agic>; nvidia,adsp_os_secload; reg = <0x0 0x02993000 0x0 0x1000>, <0x0 0x02990000 0x0 0x2000>, <0x0 0x0 0x0 0x1>, <0x0 0x0290C800 0x0 0x1>, <0x0 0x029B0000 0x0 0x90000>, <0x0 0x40000000 0x0 0xC0000000>, <0x0 0x0 0x0 0x1>; nvidia,adsp_mem = <0x5EF00000 0x01000000>, <0x5F700000 0x00800000>, <0x3F813000 0x5000>, <0x5FD00000 0x200000>; nvidia,adsp-evp-base = <0x02993700 0x00000040>; interrupts = <0 (73 - 32) 0x00000004 0>, <0 (64 - 32) 0x00000004 0>, <0 (115 - 32) 0x00000004 0>, <0 (94 - 32) 0x00000004 0>, <0 (89 - 32) 0x00000004 0>, <0 (97 - 32) 0x00000004 0>, <0 (72 - 32) 0x00000004 4>, <0 (65 - 32) 0x00000004 4>, <0 (66 - 32) 0x00000004 4>, <0 (110 - 32) 0x00000004 4>, <0 (111 - 32) 0x00000004 4>, <0 (112 - 32) 0x00000004 4>, <0 (107 - 32) 0x00000004 4>; clocks = <&bpmp_clks 6U>, <&bpmp_clks 5U>, <&bpmp_clks 3U>, <&bpmp_clks 2U>, <&bpmp_clks 21U>; clock-names = "adsp.ape", "adsp.apb2ape", "adspneon", "adsp", "aclk"; resets = <&bpmp_resets 2U>; reset-names = "adspall"; iommus = <&smmu 0x1e>; dma-mask = <0x0 0x5e000000>; iommu-resv-regions = <0x0 0x0 0x0 0x40000000 0x0 0x60000000 0xffffffff 0xffffffff>; iommu-group-id = <0x2>; status = "disabled"; }; adma: adma@2930000 { compatible = "nvidia,tegra194-adma"; interrupt-parent = <&tegra_agic>; reg = <0x0 0x02930000 0x0 0x50000>, <0x0 0x029f0000 0x0 0x10>; clocks = <&bpmp_clks 4U>; clock-names = "d_audio"; interrupts = <0 (32 - 32) 0x00000004 0>, <0 (33 - 32) 0x00000004 0>, <0 (34 - 32) 0x00000004 0>, <0 (35 - 32) 0x00000004 0>, <0 (36 - 32) 0x00000004 0>, <0 (37 - 32) 0x00000004 0>, <0 (38 - 32) 0x00000004 0>, <0 (39 - 32) 0x00000004 0>, <0 (40 - 32) 0x00000004 0>, <0 (41 - 32) 0x00000004 0>, <0 (42 - 32) 0x00000004 0>, <0 (43 - 32) 0x00000004 0>, <0 (44 - 32) 0x00000004 0>, <0 (45 - 32) 0x00000004 0>, <0 (46 - 32) 0x00000004 0>, <0 (47 - 32) 0x00000004 0>, <0 (48 - 32) 0x00000004 0>, <0 (49 - 32) 0x00000004 0>, <0 (50 - 32) 0x00000004 0>, <0 (51 - 32) 0x00000004 0>, <0 (52 - 32) 0x00000004 0>, <0 (53 - 32) 0x00000004 0>, <0 (54 - 32) 0x00000004 0>, <0 (55 - 32) 0x00000004 0>, <0 (56 - 32) 0x00000004 0>, <0 (57 - 32) 0x00000004 0>, <0 (58 - 32) 0x00000004 0>, <0 (59 - 32) 0x00000004 0>, <0 (60 - 32) 0x00000004 0>, <0 (61 - 32) 0x00000004 0>, <0 (62 - 32) 0x00000004 0>, <0 (63 - 32) 0x00000004 0>; #dma-cells = <1>; status = "disabled"; }; tegra_axbar: ahub { compatible = "nvidia,tegra186-axbar"; wakeup-disable; reg = <0x0 0x02900800 0x0 0x800>; clocks = <&bpmp_clks 4U>, <&bpmp_clks 104U>, <&bpmp_clks 5U>, <&bpmp_clks 6U>; clock-names = "ahub", "parent", "apb2ape", "xbar.ape"; assigned-clocks = <&bpmp_clks 4U>; assigned-clock-parents = <&bpmp_clks 102U>; assigned-clock-rates = <81600000>; status = "disabled"; #address-cells = <2>; #size-cells = <2>; ranges; tegra_admaif: admaif@290f000 { compatible = "nvidia,tegra186-admaif"; reg = <0x0 0x290f000 0x0 0x1000>; clocks = <&bpmp_clks 4U>; clock-names = "ahub"; dmas = <&adma 1>, <&adma 1>, <&adma 2>, <&adma 2>, <&adma 3>, <&adma 3>, <&adma 4>, <&adma 4>, <&adma 5>, <&adma 5>, <&adma 6>, <&adma 6>, <&adma 7>, <&adma 7>, <&adma 8>, <&adma 8>, <&adma 9>, <&adma 9>, <&adma 10>, <&adma 10>, <&adma 11>, <&adma 11>, <&adma 12>, <&adma 12>, <&adma 13>, <&adma 13>, <&adma 14>, <&adma 14>, <&adma 15>, <&adma 15>, <&adma 16>, <&adma 16>, <&adma 17>, <&adma 17>, <&adma 18>, <&adma 18>, <&adma 19>, <&adma 19>, <&adma 20>, <&adma 20>; dma-names = "rx1", "tx1", "rx2", "tx2", "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", "rx9", "tx9", "rx10", "tx10", "rx11", "tx11", "rx12", "tx12", "rx13", "tx13", "rx14", "tx14", "rx15", "tx15", "rx16", "tx16", "rx17", "tx17", "rx18", "tx18", "rx19", "tx19", "rx20", "tx20"; status = "disabled"; }; tegra_sfc1: sfc@2902000 { compatible = "nvidia,tegra210-sfc"; reg = <0x0 0x2902000 0x0 0x200>; nvidia,ahub-sfc-id = <0>; status = "disabled"; }; tegra_sfc2: sfc@2902200 { compatible = "nvidia,tegra210-sfc"; reg = <0x0 0x2902200 0x0 0x200>; nvidia,ahub-sfc-id = <1>; status = "disabled"; }; tegra_sfc3: sfc@2902400 { compatible = "nvidia,tegra210-sfc"; reg = <0x0 0x2902400 0x0 0x200>; nvidia,ahub-sfc-id = <2>; status = "disabled"; }; tegra_sfc4: sfc@2902600 { compatible = "nvidia,tegra210-sfc"; reg = <0x0 0x2902600 0x0 0x200>; nvidia,ahub-sfc-id = <3>; status = "disabled"; }; tegra_spkprot: spkprot@2908c00 { compatible = "nvidia,tegra210-spkprot"; reg = <0x0 0x2908c00 0x0 0x400>; nvidia,ahub-spkprot-id = <0>; status = "disabled"; }; tegra_amixer: amixer@290bb00 { compatible = "nvidia,tegra210-amixer"; reg = <0x0 0x290bb00 0x0 0x800>; nvidia,ahub-amixer-id = <0>; status = "disabled"; }; tegra_i2s1: i2s@2901000 { compatible = "nvidia,tegra210-i2s"; reg = <0x0 0x2901000 0x0 0x100>; nvidia,ahub-i2s-id = <0>; clocks = <&bpmp_clks 56U>, <&bpmp_clks 104U>, <&bpmp_clks 57U>, <&bpmp_clks 145U>, <&bpmp_clks 57U>; clock-names = "i2s", "i2s_clk_parent", "ext_audio_sync", "audio_sync", "clk_sync_input"; assigned-clocks = <&bpmp_clks 56U>; assigned-clock-parents = <&bpmp_clks 104U>; assigned-clock-rates = <1536000>; fsync-width = <31>; status = "disabled"; }; tegra_i2s2: i2s@2901100 { compatible = "nvidia,tegra210-i2s"; reg = <0x0 0x2901100 0x0 0x100>; nvidia,ahub-i2s-id = <1>; clocks = <&bpmp_clks 58U>, <&bpmp_clks 104U>, <&bpmp_clks 59U>, <&bpmp_clks 146U>, <&bpmp_clks 59U>; clock-names = "i2s", "i2s_clk_parent", "ext_audio_sync", "audio_sync", "clk_sync_input"; assigned-clocks = <&bpmp_clks 58U>; assigned-clock-parents = <&bpmp_clks 104U>; assigned-clock-rates = <1536000>; fsync-width = <31>; status = "disabled"; }; tegra_i2s3: i2s@2901200 { compatible = "nvidia,tegra210-i2s"; reg = <0x0 0x2901200 0x0 0x100>; nvidia,ahub-i2s-id = <2>; clocks = <&bpmp_clks 60U>, <&bpmp_clks 104U>, <&bpmp_clks 61U>, <&bpmp_clks 147U>, <&bpmp_clks 61U>; clock-names = "i2s", "i2s_clk_parent", "ext_audio_sync", "audio_sync", "clk_sync_input"; assigned-clocks = <&bpmp_clks 60U>; assigned-clock-parents = <&bpmp_clks 104U>; assigned-clock-rates = <1536000>; fsync-width = <31>; status = "disabled"; }; tegra_i2s4: i2s@2901300 { compatible = "nvidia,tegra210-i2s"; reg = <0x0 0x2901300 0x0 0x100>; nvidia,ahub-i2s-id = <3>; clocks = <&bpmp_clks 62U>, <&bpmp_clks 104U>, <&bpmp_clks 63U>, <&bpmp_clks 148U>, <&bpmp_clks 63U>; clock-names = "i2s", "i2s_clk_parent", "ext_audio_sync", "audio_sync", "clk_sync_input"; assigned-clocks = <&bpmp_clks 62U>; assigned-clock-parents = <&bpmp_clks 104U>; assigned-clock-rates = <1536000>; fsync-width = <31>; status = "disabled"; }; tegra_i2s5: i2s@2901400 { compatible = "nvidia,tegra210-i2s"; reg = <0x0 0x2901400 0x0 0x100>; nvidia,ahub-i2s-id = <4>; clocks = <&bpmp_clks 64U>, <&bpmp_clks 104U>, <&bpmp_clks 65U>, <&bpmp_clks 149U>, <&bpmp_clks 65U>; clock-names = "i2s", "i2s_clk_parent", "ext_audio_sync", "audio_sync", "clk_sync_input"; assigned-clocks = <&bpmp_clks 64U>; assigned-clock-parents = <&bpmp_clks 104U>; assigned-clock-rates = <1536000>; fsync-width = <31>; status = "disabled"; }; tegra_i2s6: i2s@2901500 { compatible = "nvidia,tegra210-i2s"; reg = <0x0 0x2901500 0x0 0x100>; nvidia,ahub-i2s-id = <5>; clocks = <&bpmp_clks 66U>, <&bpmp_clks 104U>, <&bpmp_clks 67U>, <&bpmp_clks 150U>, <&bpmp_clks 67U>; clock-names = "i2s", "i2s_clk_parent", "ext_audio_sync", "audio_sync", "clk_sync_input"; assigned-clocks = <&bpmp_clks 66U>; assigned-clock-parents = <&bpmp_clks 104U>; assigned-clock-rates = <1536000>; fsync-width = <31>; status = "disabled"; }; tegra_amx1: amx@2903000 { compatible = "nvidia,tegra194-amx"; reg = <0x0 0x2903000 0x0 0x100>; nvidia,ahub-amx-id = <0>; status = "disabled"; }; tegra_amx2: amx@2903100 { compatible = "nvidia,tegra194-amx"; reg = <0x0 0x2903100 0x0 0x100>; nvidia,ahub-amx-id = <1>; status = "disabled"; }; tegra_amx3: amx@2903200 { compatible = "nvidia,tegra194-amx"; reg = <0x0 0x2903200 0x0 0x100>; nvidia,ahub-amx-id = <2>; status = "disabled"; }; tegra_amx4: amx@2903300 { compatible = "nvidia,tegra194-amx"; reg = <0x0 0x2903300 0x0 0x100>; nvidia,ahub-amx-id = <3>; status = "disabled"; }; tegra_adx1: adx@2903800 { compatible = "nvidia,tegra210-adx"; reg = <0x0 0x2903800 0x0 0x100>; nvidia,ahub-adx-id = <0>; status = "disabled"; }; tegra_adx2: adx@2903900 { compatible = "nvidia,tegra210-adx"; reg = <0x0 0x2903900 0x0 0x100>; nvidia,ahub-adx-id = <1>; status = "disabled"; }; tegra_adx3: adx@2903a00 { compatible = "nvidia,tegra210-adx"; reg = <0x0 0x2903a00 0x0 0x100>; nvidia,ahub-adx-id = <2>; status = "disabled"; }; tegra_adx4: adx@2903b00 { compatible = "nvidia,tegra210-adx"; reg = <0x0 0x2903b00 0x0 0x100>; nvidia,ahub-adx-id = <3>; status = "disabled"; }; tegra_dmic1: dmic@2904000 { compatible = "nvidia,tegra210-dmic"; reg = <0x0 0x2904000 0x0 0x100>; nvidia,ahub-dmic-id = <0>; clocks = <&bpmp_clks 15U>, <&bpmp_clks 104U>; clock-names = "dmic", "parent"; assigned-clocks = <&bpmp_clks 15U>; assigned-clock-parents = <&bpmp_clks 104U>; assigned-clock-rates = <3072000>; status = "disabled"; }; tegra_dmic2: dmic@2904100 { compatible = "nvidia,tegra210-dmic"; reg = <0x0 0x2904100 0x0 0x100>; nvidia,ahub-dmic-id = <1>; clocks = <&bpmp_clks 16U>, <&bpmp_clks 104U>; clock-names = "dmic", "parent"; assigned-clocks = <&bpmp_clks 16U>; assigned-clock-parents = <&bpmp_clks 104U>; assigned-clock-rates = <3072000>; status = "disabled"; }; tegra_dmic3: dmic@2904200 { compatible = "nvidia,tegra210-dmic"; reg = <0x0 0x2904200 0x0 0x100>, <0x0 0xc303000 0x0 0x1f0>; nvidia,ahub-dmic-id = <2>; clocks = <&bpmp_clks 17U>, <&bpmp_clks 104U>; clock-names = "dmic", "parent"; assigned-clocks = <&bpmp_clks 17U>; assigned-clock-parents = <&bpmp_clks 104U>; assigned-clock-rates = <3072000>; status = "disabled"; }; tegra_dmic4: dmic@2904300 { compatible = "nvidia,tegra210-dmic"; reg = <0x0 0x2904300 0x0 0x100>; nvidia,ahub-dmic-id = <3>; clocks = <&bpmp_clks 18U>, <&bpmp_clks 104U>; clock-names = "dmic", "parent"; assigned-clocks = <&bpmp_clks 18U>; assigned-clock-parents = <&bpmp_clks 104U>; assigned-clock-rates = <3072000>; status = "disabled"; }; tegra_afc1: afc@2907000 { compatible = "nvidia,tegra186-afc"; reg = <0x0 0x2907000 0x0 0x100>; nvidia,ahub-afc-id = <0>; status = "disabled"; }; tegra_afc2: afc@2907100 { compatible = "nvidia,tegra186-afc"; reg = <0x0 0x2907100 0x0 0x100>; nvidia,ahub-afc-id = <1>; status = "disabled"; }; tegra_afc3: afc@2907200 { compatible = "nvidia,tegra186-afc"; reg = <0x0 0x2907200 0x0 0x100>; nvidia,ahub-afc-id = <2>; status = "disabled"; }; tegra_afc4: afc@2907300 { compatible = "nvidia,tegra186-afc"; reg = <0x0 0x2907300 0x0 0x100>; nvidia,ahub-afc-id = <3>; status = "disabled"; }; tegra_afc5: afc@2907400 { compatible = "nvidia,tegra186-afc"; reg = <0x0 0x2907400 0x0 0x100>; nvidia,ahub-afc-id = <4>; status = "disabled"; }; tegra_afc6: afc@2907500 { compatible = "nvidia,tegra186-afc"; reg = <0x0 0x2907500 0x0 0x100>; nvidia,ahub-afc-id = <5>; status = "disabled"; }; tegra_mvc1: mvc@290a000 { compatible = "nvidia,tegra210-mvc"; reg = <0x0 0x290a000 0x0 0x200>; nvidia,ahub-mvc-id = <0>; status = "disabled"; }; tegra_mvc2: mvc@290a200 { compatible = "nvidia,tegra210-mvc"; reg = <0x0 0x290a200 0x0 0x200>; nvidia,ahub-mvc-id = <1>; status = "disabled"; }; tegra_iqc1: iqc@290e000 { compatible = "nvidia,tegra210-iqc"; reg = <0x0 0x290e000 0x0 0x200>; nvidia,ahub-iqc-id = <0>; clocks = <&bpmp_clks 68U>; clock-names = "iqc"; status = "disabled"; }; tegra_asrc: asrc@2910000 { compatible = "nvidia,tegra186-asrc"; reg = <0x0 0x2910000 0x0 0x2000>; nvidia,ahub-asrc-id = <0>; status = "disabled"; }; tegra_arad: arad@290e400 { compatible = "nvidia,tegra186-arad"; reg = <0x0 0x290e400 0x0 0x400>; nvidia,ahub-arad-id = <0>; status = "disabled"; }; tegra_ahc: ahc@290b900 { compatible = "nvidia,tegra186-ahc"; reg = <0x0 0x290b900 0x0 0x200>; interrupt-parent = <&tegra_agic>; interrupts = <0 (88 - 32) 0x00000004 0>; status = "disabled"; }; tegra_ope1: ope@2908000 { compatible = "nvidia,tegra210-ope"; reg = <0x0 0x2908000 0x0 0x100>, <0x0 0x2908100 0x0 0x100>, <0x0 0x2908200 0x0 0x200>; nvidia,ahub-ope-id = <0>; status = "disabled"; }; tegra_dspk1: dspk@2905000 { compatible = "nvidia,tegra186-dspk"; reg = <0x0 0x2905000 0x0 0x100>; nvidia,ahub-dspk-id = <0>; clocks = <&bpmp_clks 29U>, <&bpmp_clks 104U>, <&bpmp_clks 143U>; clock-names = "dspk", "pll_a_out0", "sync_dspk"; assigned-clocks = <&bpmp_clks 29U>; assigned-clock-parents = <&bpmp_clks 104U>; assigned-clock-rates = <12288000>; status = "disabled"; }; tegra_dspk2: dspk@2905100 { compatible = "nvidia,tegra186-dspk"; reg = <0x0 0x2905100 0x0 0x100>, <0x0 0x2431000 0x0 0x1F0>; nvidia,ahub-dspk-id = <1>; clocks = <&bpmp_clks 30U>, <&bpmp_clks 104U>, <&bpmp_clks 144U>; clock-names = "dspk", "pll_a_out0", "sync_dspk"; assigned-clocks = <&bpmp_clks 30U>; assigned-clock-parents = <&bpmp_clks 104U>; assigned-clock-rates = <12288000>; status = "disabled"; }; }; tegra_adsp_audio: adsp_audio { compatible = "nvidia,tegra186-adsp-audio"; clocks = <&bpmp_clks 4U>, <&bpmp_clks 6U>, <&bpmp_clks 5U>; clock-names = "ahub", "ape", "apb2ape"; wakeup-disable; nvidia,adma_ch_start = <16>; nvidia,adma_ch_cnt = <16>; iommus = <&smmu 0x1e>; iommu-resv-regions = <0x0 0x0 0x0 0x40000000 0x0 0x60000000 0xffffffff 0xffffffff>; iommu-group-id = <0x2>; interrupt-parent = <&tegra_agic>; interrupts = <0 (48 - 32) 0x00000004 4>, <0 (49 - 32) 0x00000004 4>, <0 (50 - 32) 0x00000004 4>, <0 (51 - 32) 0x00000004 4>, <0 (52 - 32) 0x00000004 4>, <0 (53 - 32) 0x00000004 4>, <0 (54 - 32) 0x00000004 4>, <0 (55 - 32) 0x00000004 4>, <0 (56 - 32) 0x00000004 4>, <0 (57 - 32) 0x00000004 4>, <0 (58 - 32) 0x00000004 4>, <0 (59 - 32) 0x00000004 4>, <0 (60 - 32) 0x00000004 4>, <0 (61 - 32) 0x00000004 4>, <0 (62 - 32) 0x00000004 4>, <0 (63 - 32) 0x00000004 4>; status = "disabled"; }; }; hda@3510000 { compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; hda,card-name = "tegra-hda-galen-t194"; iommus = <&smmu 0x12>; reg = <0x0 0x3510000 0x0 0x10000>; clocks = <&bpmp_clks 102U>, <&bpmp_clks 71U>, <&bpmp_clks 43U>, <&bpmp_clks 44U>, <&bpmp_clks 45U>; clock-names = "pllp_out0", "maud", "hda", "hda2codec_2x", "hda2hdmi"; interrupts = <0 161 0x04>; status = "disabled"; }; eqos_ape@2990000 { status = "disabled"; compatible = "nvidia,tegra18x-eqos-ape"; wakeup-disable; reg = <0x0 0x02990054 0x0 0x4>, <0x0 0x029900c0 0x0 0x28>; clocks = <&bpmp_clks 6U>, <&bpmp_clks 104U>, <&bpmp_clks 93U>; clock-names = "eqos_ape.ape", "pll_a_out0", "pll_a"; }; }; # 44 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-safety-sce.dtsi" 1 # 21 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-safety-sce.dtsi" / { tegra_safety_ivc: tegra_safety_ivc { #address-cells = <1>; #size-cells = <0>; status = "disabled"; cmdresp@0 { compatible = "nvidia,tegra194-safety-cmd-resp"; reg = <0x0000>, <0x8000>; reg-names = "rx", "tx"; nvidia,frame-count = <16>; nvidia,frame-size = <256>; }; hb@0 { compatible = "nvidia,tegra194-safety-hb"; reg = <0x1400>, <0x9400>; reg-names = "rx", "tx"; nvidia,frame-count = <1>; nvidia,frame-size = <64>; }; mods@0 { compatible = "nvidia,tegra194-sce-mods"; reg = <0x1500>, <0x9500>; reg-names = "rx", "tx"; nvidia,frame-count = <16>; nvidia,frame-size = <64>; }; }; tegra_safety: sce@b000000 { compatible = "nvidia,tegra194-safety-ivc"; status = "disabled"; reg = <0 0xb040000 0 0x10000>, <0 0xb050000 0 0x10000>; reg-names = "ast-cpu", "ast-dma"; iommus = <&smmu 0x1f>; nvidia,ivc-channels = <&tegra_safety_ivc 2 0x90000000 0x10000>; hsp { compatible = "nvidia,tegra186-hsp-mailbox"; nvidia,hsp-shared-mailbox = <&sce_hsp 1>; nvidia,hsp-shared-mailbox-names = "ivc-pair"; }; }; }; # 45 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-camera.dtsi" 1 # 21 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-camera.dtsi" / { aliases { tegra-camera-rtcpu = &tegra_rce; }; tegra_rce: rtcpu@bc00000 { compatible = "nvidia,tegra194-rce"; nvidia,cpu-name = "rce"; reg = <0 0xbc00000 0 0x1000>, <0 0xb9f0000 0 0x40000>, <0 0xb840000 0 0x10000>, <0 0xb850000 0 0x10000>; reg-names = "rce-evp", "rce-pm", "ast-cpu", "ast-dma"; clocks = <&bpmp_clks 113U>, <&bpmp_clks 114U>; clock-names = "rce-cpu-nic", "rce-nic"; nvidia,clock-rates = <19200000 370000000>, <19200000 370000000>; nvidia,clock-parents = <&bpmp_clks 14U>, <&bpmp_clks 214U>; nvidia,clock-parent-names = "clk-m", "nafll-rce"; resets = <&bpmp_resets 81U>; reset-names = "rce-all"; interrupts = <0 19 0x4>; interrupt-names = "wdt-remote"; nvidia,camera-devices = <&isp &vi &nvcsi>; nvidia,camera-device-names = "isp", "vi", "nvcsi"; nvidia,memory-bw = <0xffffffff>; iommus = <&smmu 0x2a>; iommu-resv-regions = <0x0 0x0 0x0 0xA0000000 0x0 0xc0000000 0xffffffff 0xffffffff>; dma-coherent; nvidia,trace = <&{/tegra-rtcpu-trace} 4 0x70100000 0x100000>; nvidia,ivc-channels = <&{/camera-ivc-channels} 2 0x90000000 0x10000>; nvidia,autosuspend-delay-ms = <5000>; hsp { compatible = "nvidia,tegra186-hsp-mailbox"; nvidia,hsp-shared-mailbox = <&hsp_rce 1 &hsp_rce 6>; nvidia,hsp-shared-mailbox-names = "ivc-pair", "cmd-pair"; }; }; camera-ivc-channels { echo@0 { compatible = "nvidia,tegra186-camera-ivc-protocol-echo"; nvidia,service = "echo"; nvidia,version = <0>; nvidia,group = <1>; nvidia,frame-count = <16>; nvidia,frame-size = <64>; }; dbg@1 { compatible = "nvidia,tegra186-camera-ivc-protocol-dbg"; nvidia,service = "debug"; nvidia,version = <0>; nvidia,group = <1>; nvidia,frame-count = <1>; nvidia,frame-size = <384>; }; dbg@2 { compatible = "nvidia,tegra186-camera-ivc-protocol-debug"; nvidia,service = "debug"; nvidia,version = <0>; nvidia,group = <1>; nvidia,frame-count = <1>; nvidia,frame-size = <8192>; nvidia,ivc-timeout = <50>; nvidia,test-timeout = <5000>; nvidia,mem-map = <&tegra_rce &vi &isp>; nvidia,test-bw = <0xffFFffFF>; }; ivccontrol@3 { compatible = "nvidia,tegra186-camera-ivc-protocol-capture-control"; nvidia,service = "capture-control"; nvidia,version = <0>; nvidia,group = <1>; nvidia,frame-count = <64>; nvidia,frame-size = <320>; }; ivccapture@4 { compatible = "nvidia,tegra186-camera-ivc-protocol-capture"; nvidia,service = "capture"; nvidia,version = <0>; nvidia,group = <1>; nvidia,frame-count = <512>; nvidia,frame-size = <64>; }; }; tegra-rtcpu-trace { nvidia,enable-printk; nvidia,interval-ms = <50>; nvidia,log-prefix = "[RCE]"; }; }; # 46 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-actmon.dtsi" 1 # 16 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-actmon.dtsi" / { actmon@d230000 { status = "disabled"; #address-cells = <2>; #size-cells = <2>; compatible = "nvidia,tegra194-cactmon"; reg = <0x0 0x0d230000 0x0 0x1000>; interrupts = <0 210 0x00000004>; clocks = <&bpmp_clks 1U>; clock-names = "actmon"; resets = <&bpmp_resets 1U>; reset-names = "actmon_rst"; nvidia,sample_period = /bits/ 8 <20>; mc_all { #address-cells = <1>; #size-cells = <0>; nvidia,reg_offs = <0x100>; nvidia,irq_mask = <0x2>; nvidia,suspend_freq = <204000>; nvidia,boost_freq_step = <204000>; nvidia,boost_up_coef = <200>; nvidia,boost_down_coef = <50>; nvidia,boost_up_threshold = <30>; nvidia,boost_down_threshold = <20>; nvidia,up_wmark_window = /bits/ 8 <3>; nvidia,down_wmark_window = /bits/ 8 <2>; nvidia,avg_window_log2 = /bits/ 8 <6>; # 56 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-actmon.dtsi" nvidia,count_weight = <0x100>; nvidia,max_dram_channels = /bits/ 8 <16>; nvidia,type = <1>; status = "disabled"; }; }; }; # 47 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-disp-imp.dtsi" 1 # 19 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-disp-imp.dtsi" / { host1x { disp_imp_table: disp_imp_table { status = "okay"; num_settings = <4>; # 60 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-disp-imp.dtsi" disp_imp_settings_0 { nvidia,total_disp_bw_with_catchup = <0 15681600>; nvidia,total_disp_bw_without_catchup = <0 14256000>; nvidia,disp_emc_floor = <0xffffffff 0xffffffff>; nvidia,disp_min_hubclk = <0xffffffff 0xffffffff>; nvidia,total_win_fetch_slots = /bits/ 16 <1>; nvidia,total_cursor_fetch_slots = /bits/ 16 <1>; nvidia,imp_win_mapping = /bits/ 8 <0 1 2 3 4 5>; nvidia,win_fetch_meter_slots = /bits/ 16 <1 1 1 1 1 1>; nvidia,win_dvfs_watermark_values = <0 0 0 0 0 0 0 0 0 0 0 0>; nvidia,win_pipe_meter_values = <0 0 0 0 0 0>; nvidia,win_mempool_buffer_entries = <0 814 0 814 0 814 0 814 0 814 0 814>; nvidia,win_thread_groups = /bits/ 8 <0 1 2 3 4 5>; nvidia,imp_head_mapping = /bits/ 8 <0 1 2 3>; nvidia,cursor_fetch_meter_slots = /bits/ 16 <1 1 1 1>; nvidia,cursor_dvfs_watermark_values = <0 0 0 0 0 0 0 0>; nvidia,cursor_pipe_meter_values = <0 0 0 0>; nvidia,cursor_mempool_buffer_entries = <0 16 0 16 0 16 0 16>; }; disp_imp_settings_1 { nvidia,total_disp_bw_with_catchup = <0 7088400>; nvidia,total_disp_bw_without_catchup = <0 6444000>; nvidia,disp_emc_floor = <0xffffffff 0xffffffff>; nvidia,disp_min_hubclk = <0xffffffff 0xffffffff>; nvidia,total_win_fetch_slots = /bits/ 16 <1>; nvidia,total_cursor_fetch_slots = /bits/ 16 <1>; nvidia,imp_win_mapping = /bits/ 8 <0 1 2 3 4 5>; nvidia,win_fetch_meter_slots = /bits/ 16 <1 1 1 1 1 1>; nvidia,win_dvfs_watermark_values = <0 0 0 0 0 0 0 0 0 0 0 0>; nvidia,win_pipe_meter_values = <0 0 0 0 0 0>; nvidia,win_mempool_buffer_entries = <0 814 0 814 0 814 0 814 0 814 0 814>; nvidia,win_thread_groups = /bits/ 8 <0 1 2 3 4 5>; nvidia,imp_head_mapping = /bits/ 8 <0 1 2 3>; nvidia,cursor_fetch_meter_slots = /bits/ 16 <1 1 1 1>; nvidia,cursor_dvfs_watermark_values = <0 0 0 0 0 0 0 0>; nvidia,cursor_pipe_meter_values = <0 0 0 0>; nvidia,cursor_mempool_buffer_entries = <0 16 0 16 0 16 0 16>; }; disp_imp_settings_2 { nvidia,total_disp_bw_with_catchup = <0 3920400>; nvidia,total_disp_bw_without_catchup = <0 3564000>; nvidia,disp_emc_floor = <0xffffffff 0xffffffff>; nvidia,disp_min_hubclk = <0xffffffff 0xffffffff>; nvidia,total_win_fetch_slots = /bits/ 16 <1>; nvidia,total_cursor_fetch_slots = /bits/ 16 <1>; nvidia,imp_win_mapping = /bits/ 8 <0 1 2 3 4 5>; nvidia,win_fetch_meter_slots = /bits/ 16 <1 1 1 1 1 1>; nvidia,win_dvfs_watermark_values = <0 0 0 0 0 0 0 0 0 0 0 0>; nvidia,win_pipe_meter_values = <0 0 0 0 0 0>; nvidia,win_mempool_buffer_entries = <0 814 0 814 0 814 0 814 0 814 0 814>; nvidia,win_thread_groups = /bits/ 8 <0 1 2 3 4 5>; nvidia,imp_head_mapping = /bits/ 8 <0 1 2 3>; nvidia,cursor_fetch_meter_slots = /bits/ 16 <1 1 1 1>; nvidia,cursor_dvfs_watermark_values = <0 0 0 0 0 0 0 0>; nvidia,cursor_pipe_meter_values = <0 0 0 0>; nvidia,cursor_mempool_buffer_entries = <0 16 0 16 0 16 0 16>; }; disp_imp_settings_3 { nvidia,total_disp_bw_with_catchup = <0 1966800>; nvidia,total_disp_bw_without_catchup = <0 1788000>; nvidia,disp_emc_floor = <0xffffffff 0xffffffff>; nvidia,disp_min_hubclk = <0xffffffff 0xffffffff>; nvidia,total_win_fetch_slots = /bits/ 16 <1>; nvidia,total_cursor_fetch_slots = /bits/ 16 <1>; nvidia,imp_win_mapping = /bits/ 8 <0 1 2 3 4 5>; nvidia,win_fetch_meter_slots = /bits/ 16 <1 1 1 1 1 1>; nvidia,win_dvfs_watermark_values = <0 0 0 0 0 0 0 0 0 0 0 0>; nvidia,win_pipe_meter_values = <0 0 0 0 0 0>; nvidia,win_mempool_buffer_entries = <0 814 0 814 0 814 0 814 0 814 0 814>; nvidia,win_thread_groups = /bits/ 8 <0 1 2 3 4 5>; nvidia,imp_head_mapping = /bits/ 8 <0 1 2 3>; nvidia,cursor_fetch_meter_slots = /bits/ 16 <1 1 1 1>; nvidia,cursor_dvfs_watermark_values = <0 0 0 0 0 0 0 0>; nvidia,cursor_pipe_meter_values = <0 0 0 0>; nvidia,cursor_mempool_buffer_entries = <0 16 0 16 0 16 0 16>; }; }; }; }; # 48 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-aon.dtsi" 1 # 19 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-aon.dtsi" / { aon: aon@c000000 { compatible = "nvidia,tegra186-aon"; status = "okay"; iommus = <&smmu 0x16>; dma-coherent; reg = <0x0 0x0c1a0000 0x0 0x40000>; #mbox-cells = <1>; nvidia,hsp-shared-mailbox = <&aon_hsp 2>; nvidia,hsp-shared-mailbox-names = "ivc-pair"; nvidia,ivc-carveout-base-ss = <0>; nvidia,ivc-carveout-size-ss = <1>; nvidia,ivc-rx-ss = <2>; nvidia,ivc-tx-ss = <3>; nvidia,ivc-dbg-enable-ss = <0>; ivc-channels@80000000 { #address-cells = <1>; #size-cells = <0>; ivc_aon_echo@0 { reg = <0x0000>, <0x10000>; reg-names = "rx", "tx"; nvidia,frame-count = <16>; nvidia,frame-size = <64>; }; ivc_aon_aondbg@480 { reg = <0x0480>, <0x10480>; reg-names = "rx", "tx"; nvidia,frame-count = <2>; nvidia,frame-size = <128>; }; ivc_aon_spi@600 { reg = <0x0600>, <0x10600>; reg-names = "rx", "tx"; nvidia,frame-count = <2>; nvidia,frame-size = <24704>; }; ivc_can0@c780 { reg = <0xc780>, <0x1c780>; reg-names = "rx", "tx"; nvidia,frame-count = <16>; nvidia,frame-size = <128>; }; ivc_can1@d000 { reg = <0xd000>, <0x1d000>; reg-names = "rx", "tx"; nvidia,frame-count = <16>; nvidia,frame-size = <128>; }; ivc_aon_shub@d880 { reg = <0xd880>, <0x1d880>; reg-names = "rx", "tx"; nvidia,frame-count = <32>; nvidia,frame-size = <256>; }; }; }; aondbg { compatible = "nvidia,tegra186-aondbg"; mboxes = <&aon 1>; status = "okay"; }; aon_shub { status = "disabled"; compatible = "nvidia,tegra186_aon_shub"; mboxes = <&aon 5>; }; aon_clks: aonclk { compatible = "nvidia,tegra-aon-clks"; #clock-cells = <1>; status = "okay"; }; }; # 49 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-cpus.dtsi" 1 # 15 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-cpus.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-cpuidle.dtsi" 1 # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-cpuidle.dtsi" / { cpus { CPU_CORE_POWER_STATES: cpu_core_power_states { compatible = "nvidia,tegra194-cpuidle-core"; C1: c1 { compatible = "nvidia,tegra194-cpuidle-core"; state-name = "Clock gated"; wakeup-latency-us = <1>; min-residency-us = <1>; power = <70>; pmstate = <0x1>; status = "okay"; }; C6: c6 { compatible = "nvidia,tegra194-cpuidle-core"; state-name = "Virtual core powergate"; wakeup-latency-us = <2000>; min-residency-us = <0xffffffff>; power = <60>; pmstate = <0x6>; arm,psci-suspend-param= <0x6>; status = "okay"; }; C7: c7 { compatible = "nvidia,tegra194-cpuidle-core"; state-name = "Core powergate"; wakeup-latency-us = <560>; min-residency-us = <0xffffffff>; power = <60>; pmstate = <0x7>; arm,psci-suspend-param= <0x40000007>; status = "disabled"; }; }; cpu_cluster_power_states { compatible = "nvidia,tegra194-cpuidle-cluster"; cc6 { state-name = "Cluster powergate"; wakeup-latency-us = <5000>; min-residency-us = <0xffffffff>; power = <19>; pmstate = <0x6>; status = "okay"; }; }; cpu_crossover_thresholds { compatible = "nvidia,tegra194-cpuidle-thresholds"; thresholds { crossover_c1_c6 = <30000>; crossover_cc1_cc6 = <80000>; }; }; }; }; # 16 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-cpus.dtsi" 2 / { cpus { #address-cells = <2>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cl0_0>; }; core1 { cpu = <&cl0_1>; }; }; cluster1 { core0 { cpu = <&cl1_0>; }; core1 { cpu = <&cl1_1>; }; }; cluster2 { core0 { cpu = <&cl2_0>; }; core1 { cpu = <&cl2_1>; }; }; cluster3 { core0 { cpu = <&cl3_0>; }; core1 { cpu = <&cl3_1>; }; }; }; cl0_0: cpu@0 { device_type = "cpu"; compatible = "nvidia,carmel", "arm,armv8"; reg = <0x0 0x10000>; enable-method = "psci"; cpu-idle-states = <&C6 &C7>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; d-cache-size = <65536>; d-cache-line-size = <64>; d-cache-sets = <256>; l2-cache = <&L2_0>; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_CARMEL &CPU_COST_CARMEL>; }; cl0_1: cpu@1 { device_type = "cpu"; compatible = "nvidia,carmel", "arm,armv8"; reg = <0x0 0x10001>; enable-method = "psci"; cpu-idle-states = <&C6 &C7>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; d-cache-size = <65536>; d-cache-line-size = <64>; d-cache-sets = <256>; l2-cache = <&L2_0>; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_CARMEL &CPU_COST_CARMEL>; status = "disabled"; }; cl1_0: cpu@2 { device_type = "cpu"; compatible = "nvidia,carmel", "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; cpu-idle-states = <&C6 &C7>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; d-cache-size = <65536>; d-cache-line-size = <64>; d-cache-sets = <256>; l2-cache = <&L2_1>; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_CARMEL &CPU_COST_CARMEL>; status = "disabled"; }; cl1_1: cpu@3 { device_type = "cpu"; compatible = "nvidia,carmel", "arm,armv8"; reg = <0x0 0x101>; enable-method = "psci"; cpu-idle-states = <&C6 &C7>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; d-cache-size = <65536>; d-cache-line-size = <64>; d-cache-sets = <256>; l2-cache = <&L2_1>; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_CARMEL &CPU_COST_CARMEL>; status = "disabled"; }; cl2_0: cpu@4 { device_type = "cpu"; compatible = "nvidia,carmel", "arm,armv8"; reg = <0x0 0x200>; enable-method = "psci"; cpu-idle-states = <&C6 &C7>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; d-cache-size = <65536>; d-cache-line-size = <64>; d-cache-sets = <256>; l2-cache = <&L2_2>; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_CARMEL &CPU_COST_CARMEL>; status = "disabled"; }; cl2_1: cpu@5 { device_type = "cpu"; compatible = "nvidia,carmel", "arm,armv8"; reg = <0x0 0x201>; enable-method = "psci"; cpu-idle-states = <&C6 &C7>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; d-cache-size = <65536>; d-cache-line-size = <64>; d-cache-sets = <256>; l2-cache = <&L2_2>; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_CARMEL &CPU_COST_CARMEL>; status = "disabled"; }; cl3_0: cpu@6 { device_type = "cpu"; compatible = "nvidia,carmel", "arm,armv8"; reg = <0x0 0x10300>; enable-method = "psci"; cpu-idle-states = <&C6 &C7>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; d-cache-size = <65536>; d-cache-line-size = <64>; d-cache-sets = <256>; l2-cache = <&L2_3>; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_CARMEL &CPU_COST_CARMEL>; status = "disabled"; }; cl3_1: cpu@7 { device_type = "cpu"; compatible = "nvidia,carmel", "arm,armv8"; reg = <0x0 0x10301>; enable-method = "psci"; cpu-idle-states = <&C6 &C7>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; d-cache-size = <65536>; d-cache-line-size = <64>; d-cache-sets = <256>; l2-cache = <&L2_3>; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_CARMEL &CPU_COST_CARMEL>; status = "disabled"; }; }; L2_0: l2-cache0 { cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; next-level-cache = <&L3>; }; L2_1: l2-cache1 { cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; next-level-cache = <&L3>; status = "disabled"; }; L2_2: l2-cache2 { cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; next-level-cache = <&L3>; status = "disabled"; }; L2_3: l2-cache3 { cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; next-level-cache = <&L3>; status = "disabled"; }; L3: l3-cache { cache-size = <4194304>; cache-line-size = <64>; cache-sets = <4096>; }; CPU_COST_CARMEL: core-cost1 { busy-cost-data = <1024 1024>; idle-cost-data = <128>; }; arm-pmu { compatible = "arm,armv8-pmuv3"; interrupts = <0 384 0x4>, <0 385 0x4>, <0 386 0x4>, <0 387 0x4>, <0 388 0x4>, <0 389 0x4>, <0 390 0x4>, <0 391 0x4>; interrupt-affinity = <&cl0_0>, <&cl0_1>, <&cl1_0>, <&cl1_1>, <&cl2_0>, <&cl2_1>, <&cl3_0>, <&cl3_1>; status = "disabled"; }; carmel-pmu { compatible = "nvidia,carmel-pmu"; interrupts = <0 365 0x4>; interrupt-affinity = <&{/cpus/cpu@0}>; status = "okay"; }; }; # 50 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-thermal.dtsi" 1 # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-thermal.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-include/dt-bindings/thermal/tegra194-thermal.h" 1 # 19 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-thermal.dtsi" 2 / { bpmp { bpmpthermal { compatible = "nvidia,tegra186-bpmp-thermal"; #thermal-sensor-cells = <1>; status = "disabled"; }; }; thermal-zones { CPU-therm { polling-delay = <0>; polling-delay-passive = <1000>; thermal-sensors = <&{/bpmp/bpmpthermal} 5>; status = "disabled"; }; GPU-therm { polling-delay = <0>; polling-delay-passive = <1000>; thermal-sensors = <&{/bpmp/bpmpthermal} 3>; status = "disabled"; }; AUX-therm { polling-delay = <0>; polling-delay-passive = <1000>; thermal-sensors = <&{/bpmp/bpmpthermal} 4>; status = "disabled"; }; aotag: AO-therm { polling-delay = <0>; polling-delay-passive = <1000>; thermal-sensors = <&{/bpmp/bpmpthermal} 6>; status = "disabled"; }; tj_therm: tj-therm { polling-delay = <0>; polling-delay-passive = <1000>; thermal-sensors = <&{/bpmp/bpmpthermal} 7>; status = "disabled"; }; }; soctherm-oc-event { compatible = "nvidia,tegra194-oc-event"; interrupts = <0 137 0x4>; reg = <0x0 0x0d280000 0x0 0xa40>, <0x0 0x0d170000 0x0 0x4>; status = "disabled"; }; }; # 51 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/tegra/kernel-include/dt-bindings/soc/tegra-io-pads.h" 1 # 52 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/tegra/kernel-include/dt-bindings/input/input.h" 1 # 12 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/tegra/kernel-include/dt-bindings/input/input.h" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/tegra/kernel-include/dt-bindings/input/linux-event-codes.h" 1 # 13 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/tegra/kernel-include/dt-bindings/input/input.h" 2 # 53 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" 2 / { compatible = "nvidia,tegra186"; interrupt-parent = <&intc>; #address-cells = <2>; #size-cells = <2>; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; generic_reserved: generic_carveout { compatible = "nvidia,generic_carveout"; size = <0 0>; alignment = <0 0x100000>; alloc-ranges = <0 0 0x1 0>; no-map; status = "disabled"; }; gos_reserved: grid-of-semaphores { compatible = "nvidia,gosmem"; size = <0 0x6000>; alignment = <0 0x1000>; no-map; status = "disabled"; cvdevs = <&nvdla0 &nvdla1 &pva0 &pva1 &vi_thi &isp_thi>; }; ramoops_reserved: ramoops_carveout { compatible = "nvidia,ramoops"; size = <0x0 0x200000>; alignment = <0x0 0x10000>; alloc-ranges = <0x0 0x0 0x1 0x0>; no-map; }; fb0_reserved: fb0_carveout { reg = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; reg-names = "surface", "lut"; no-map; }; fb1_reserved: fb1_carveout { reg = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; reg-names = "surface", "lut"; no-map; }; fb2_reserved: fb2_carveout { reg = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; reg-names = "surface", "lut"; no-map; }; fb3_reserved: fb3_carveout { reg = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; reg-names = "surface", "lut"; no-map; }; }; tegra-carveouts { compatible = "nvidia,carveouts-t19x"; memory-region = <&gos_reserved &generic_reserved>; status = "disabled"; }; tegra-cache { compatible = "nvidia,t19x-cache"; l3-gpu-cpu-ways = <0>; l3-gpu-only-ways = <0>; l3-total-ways = <16>; l3-size = /bits/ 64 <0x0000000000400000>; status = "disabled"; }; tegra-cvnas { compatible = "nvidia,tegra-cvnas"; power-domains = <&bpmp 26U>; reg = <0x0 0x14000000 0x0 0x20000>, <0x0 0x14020000 0x0 0x10000>, <0x0 0x0b240000 0x0 0x10000>; clocks = <&bpmp_clks 293U>, <&bpmp_clks 213U>, <&bpmp_clks 14U>; clock-names = "cvnas", "nafll_cvnas", "clk_m"; resets = <&bpmp_resets 131U>, <&bpmp_resets 132U>; reset-names = "rst", "rst_fcm"; interrupts = <0 238 4>, <0 239 4>; cvsramslice = <4 0x1000>; cvsram-reg = <0x0 0x50000000 0x0 0x400000>; status = "disabled"; }; timer { compatible = "arm,armv8-timer"; interrupts = <1 13 ((((1 << (8)) - 1) << 8) | 0x00000008)>, <1 14 ((((1 << (8)) - 1) << 8) | 0x00000008)>, <1 11 ((((1 << (8)) - 1) << 8) | 0x00000008)>, <1 10 ((((1 << (8)) - 1) << 8) | 0x00000008)>; status = "disabled"; }; timer@3010000 { compatible = "nvidia,tegra186-timer"; interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>, <0 4 4>, <0 5 4>, <0 6 4>, <0 7 4>; clock-frequency = <19200000>; reg = <0x0 0x03010000 0x0 0x000e0000>; tmr-count = <10>; wdt-count = <3>; status = "disabled"; }; tegra_pm_irq: tegra194-pm-irq { compatible = "nvidia,tegra194-pm-irq"; interrupt-controller; #interrupt-cells = <3>; interrupt-parent = <&intc>; status = "disabled"; }; bpmp_clks: clock@0 { compatible = "nvidia,tegra-bpmp-clks"; reg = <0x0 0x0 0x0 0x0>; #clock-cells = <1>; status = "disabled"; }; bpmp_resets: bpmp_reset@0 { compatible = "nvidia,bpmp-resets"; reg = <0x0 0x0 0x0 0x0>; #reset-cells = <1>; status = "disabled"; }; tegra_rtc: rtc@c2a0000 { compatible = "nvidia,tegra18-rtc"; reg = <0x0 0x0c2a0000 0x0 0x00010000>; interrupt-parent = <&tegra_pm_irq>; interrupts = <0 10 0x04>; status = "disabled"; }; mc_sid@2c00000 { compatible = "nvidia,tegra194-mc-sid"; reg = <0x0 0x02c00000 0x0 0x00010000>, <0x0 0x02c10000 0x0 0x00010000>; status = "disabled"; }; smmu: iommu@12000000{ compatible = "t19x,arm,mmu-500"; # 304 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-base.dtsi" reg = <0x0 0x12000000 0x0 0x01000000>, <0x0 0x11000000 0x0 0x01000000>, <0x0 0x10000000 0x0 0x01000000>; #global-interrupts = <6>; interrupts = <0 170 4>, <0 171 4>, <0 232 4>, <0 233 4>, <0 240 4>, <0 241 4>; iso-smmu-id = <2>; suspend-save-reg = <0x0c3902ac>; status = "disabled"; #iommu-cells = <1>; domains { aon_domain { address-space = <&common_as>; sid-list = <0x16>; }; ape_domain { address-space = <&ape_as>; sid-list = <(0x1e) (0x14)>; }; bpmp_domain { address-space = <&common_as>; sid-list = <0x32>; }; gpcdma_domain { address-space = <&common_as>; sid-list = <0x20>; }; hda_domain { address-space = <&common_as>; sid-list = <0x12>; }; host1x_domain { address-space = <&host1x_as>; sid-list = <(0x1)>; }; host1x_client_domain { address-space = <&host1x_client_as>; sid-list = <(0x3) (0x6) (0x7) (0x8) (0x51) (0x52) (0x55) (0x5C) (0xa) (0xb)>; }; host1x0_domain { address-space = <&host1x_client_as>; sid-list = <0x38>; }; host1x1_domain { address-space = <&host1x_client_as>; sid-list = <0x39>; }; host1x2_domain { address-space = <&host1x_client_as>; sid-list = <0x3a>; }; host1x3_domain { address-space = <&host1x_client_as>; sid-list = <0x3b>; }; host1x4_domain { address-space = <&host1x_client_as>; sid-list = <0x3c>; }; host1x5_domain { address-space = <&host1x_client_as>; sid-list = <0x3d>; }; host1x6_domain { address-space = <&host1x_client_as>; sid-list = <0x3e>; }; host1x7_domain { address-space = <&host1x_client_as>; sid-list = <0x3f>; }; isp_domain { address-space = <&pixel_as>; sid-list = <0x5>; }; nvdisplay_domain { address-space = <&nvdisplay_as>; sid-list = <(0x9)>; }; pcie0_domain { address-space = <&pcie0_as>; sid-list = <0x56>; }; pcie1_domain { address-space = <&pcie1_as>; sid-list = <0x57>; }; pcie2_domain { address-space = <&pcie2_as>; sid-list = <0x58>; }; pcie3_domain { address-space = <&pcie3_as>; sid-list = <0x59>; }; pcie4_domain { address-space = <&pcie4_as>; sid-list = <0x5A>; }; pcie5_domain { address-space = <&pcie5_as>; sid-list = <0x5B>; }; pva0_domain { address-space = <&pva_as>; sid-list = <(0x53)>; }; pva1_domain { address-space = <&pva_as>; sid-list = <(0x54)>; }; sce_domain { address-space = <&common_as>; sid-list = <0x1f>; }; rce_domain { address-space = <&camera_vm1_as>; sid-list = <0x2a>; }; sata2_domain { address-space = <&common_as>; sid-list = <0x1d>; }; sdmmc1a_domain { address-space = <&common_as>; sid-list = <0x1a>; }; sdmmc3a_domain { address-space = <&common_as>; sid-list = <0x18>; }; sdmmc4a_domain { address-space = <&common_as>; sid-list = <0x17>; }; se_domain { address-space = <&se_client_as>; sid-list = <(0xc) (0xd) (0xe) (0xf)>; }; smmu_test_domain { address-space = <&common_as>; sid-list = <0x33>; }; ufshci_domain { address-space = <&common_as>; sid-list = <0x15>; }; vi_domain { address-space = <&pixel_as>; sid-list = <0x4>; }; xusb_dev_domain { address-space = <&common_as>; sid-list = <0x1c>; }; xusb_host_domain { address-space = <&common_as>; sid-list = <0x1b>; }; xusb_host_vf0_domain { address-space = <&common_as>; sid-list = <0x5d>; }; xusb_host_vf1_domain { address-space = <&common_as>; sid-list = <0x5e>; }; xusb_host_vf2_domain { address-space = <&common_as>; sid-list = <0x5f>; }; xusb_host_vf3_domain { address-space = <&common_as>; sid-list = <0x60>; }; }; address-space-prop { ape_as: ape { iova-start = <0x0 0x40000000>; iova-size = <0x0 0x20000000>; alignment = <0xFFFFF>; num-pf-page = <0>; gap-page = <1>; }; camera_vm0_as: camera_vm0 { iova-start = <0x0 0x80000000>; iova-size = <0x0 0x20000000>; alignment = <0xFFFFF>; num-pf-page = <0>; gap-page = <1>; }; camera_vm1_as: camera_vm1 { iova-start = <0x0 0xA0000000>; iova-size = <0x0 0x20000000>; alignment = <0xFFFFF>; num-pf-page = <0>; gap-page = <1>; }; common_as: common { iova-start = <0x0 0x80000000>; iova-size = <0x0 0x7FF00000>; alignment = <0xFFFFF>; num-pf-page = <0>; gap-page = <1>; }; host1x_as: host1x { iova-start = <0x0 0x1000>; iova-size = <0x0 0xFFFFEFFF>; alignment = <0xFFFFF>; num-pf-page = <0>; gap-page = <1>; }; host1x_client_as: host1x_client { iova-start = <0x0 0x1000>; iova-size = <0x1F 0xFFFFF000>; alignment = <0xFFFFF>; num-pf-page = <0>; gap-page = <1>; }; nvdisplay_as: nvdisplay { iova-start = <0x0 0x1000>; iova-size = <0x0 0xFFFFEFFF>; alignment = <0xFFFFF>; num-pf-page = <0>; gap-page = <1>; }; pcie0_as: pcie0 { iova-start = <0x0 0x80000000>; iova-size = <0x4 0x7FFFFFFF>; alignment = <0xFFFFF>; num-pf-page = <0>; gap-page = <1>; }; pcie1_as: pcie1 { iova-start = <0x0 0x80000000>; iova-size = <0x1F 0x7FFFFFFF>; alignment = <0xFFFFF>; num-pf-page = <0>; gap-page = <1>; }; pcie2_as: pcie2 { iova-start = <0x0 0x80000000>; iova-size = <0x0 0xFFFFFFFF>; alignment = <0xFFFFF>; num-pf-page = <0>; gap-page = <1>; }; pcie3_as: pcie3 { iova-start = <0x0 0x80000000>; iova-size = <0x0 0xFFFFFFFF>; alignment = <0xFFFFF>; num-pf-page = <0>; gap-page = <1>; }; pcie4_as: pcie4 { iova-start = <0x0 0x80000000>; iova-size = <0x4 0x7FFFFFFF>; alignment = <0xFFFFF>; num-pf-page = <0>; gap-page = <1>; }; pcie5_as: pcie5 { iova-start = <0x0 0x80000000>; iova-size = <0x4 0x7FFFFFFF>; alignment = <0xFFFFF>; num-pf-page = <0>; gap-page = <1>; }; pixel_as: pixel { iova-start = <0x0 0x80000000>; iova-size = <0x4 0x3FFFFFFF>; alignment = <0xFFFFF>; num-pf-page = <0>; gap-page = <1>; }; pva_as: pva0 { iova-start = <0x0 0x80000000>; iova-size = <0x0 0x7FFFFFFF>; alignment = <0xFFFFF>; num-pf-page = <0>; gap-page = <1>; }; se_client_as: se { iova-start = <0x0 0x1000>; iova-size = <0x0 0xFFFFEFFF>; alignment = <0xFFFFF>; num-pf-page = <0>; gap-page = <1>; }; }; }; smmu_test: smmu_test { compatible = "nvidia,smmu_test"; iommus = <&smmu 0x33>; }; dma_test: dma_test { compatible = "nvidia,dma_test"; }; tegra_udrm: tegra_udrm { compatible = "nvidia,tegra-udrm"; }; mc { #address-cells = <2>; #size-cells = <2>; compatible = "nvidia,tegra-t19x-mc"; reg-ranges = <1>; reg = <0x0 0x2c10000 0x0 0x10000 0x0 0x2c20000 0x0 0x10000 0x0 0x2c30000 0x0 0x10000 0x0 0x2c40000 0x0 0x10000 0x0 0x2c50000 0x0 0x10000 0x0 0x2b80000 0x0 0x10000 0x0 0x2b90000 0x0 0x10000 0x0 0x2ba0000 0x0 0x10000 0x0 0x2bb0000 0x0 0x10000 0x0 0x1700000 0x0 0x10000 0x0 0x1710000 0x0 0x10000 0x0 0x1720000 0x0 0x10000 0x0 0x1730000 0x0 0x10000 0x0 0x1740000 0x0 0x10000 0x0 0x1750000 0x0 0x10000 0x0 0x1760000 0x0 0x10000 0x0 0x1770000 0x0 0x10000 0x0 0x2C60000 0x0 0x10000 0x0 0x2c70000 0x0 0x10000 0x0 0x2c80000 0x0 0x10000 0x0 0x2c90000 0x0 0x10000 0x0 0x2ca0000 0x0 0x10000 0x0 0x2cb0000 0x0 0x10000 0x0 0x2cc0000 0x0 0x10000 0x0 0x2cd0000 0x0 0x10000 0x0 0x2ce0000 0x0 0x10000 0x0 0x1780000 0x0 0x10000 0x0 0x1790000 0x0 0x10000 0x0 0x17a0000 0x0 0x10000 0x0 0x17b0000 0x0 0x10000 0x0 0x17c0000 0x0 0x10000 0x0 0x17d0000 0x0 0x10000 0x0 0x17e0000 0x0 0x10000 0x0 0x17f0000 0x0 0x10000>; interrupts = <0 223 0x4>, <0 224 0x4>; int_mask = <0x1b3140>; ecc_int_mask = <0x1c00>; channels = <16>; ranges; status = "disabled"; mssnvlink@1f20000 { reg = <0x0 0x1f20000 0x0 0x20000 0x0 0x1f40000 0x0 0x20000 0x0 0x1f60000 0x0 0x20000 0x0 0x1f80000 0x0 0x20000>; mssnvlink_hubs = <4>; }; }; intc: interrupt-controller@3881000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0 0x03881000 0 0x1000>, <0 0x03882000 0 0x2000>, <0 0x03884000 0 0x2000>, <0 0x03886000 0 0x2000>; interrupts = <1 9 ((((1 << (8)) - 1) << 8) | 0x00000004)>; interrupt-parent = <&intc>; status = "disabled"; }; chipid@100000 { compatible = "nvidia,tegra186-chipid"; reg = <0x0 0x00100000 0x0 0x10000>; status = "disabled"; }; miscreg@00100000 { compatible = "nvidia,tegra186-miscreg"; reg = <0x0 0x00100000 0x0 0xf000>, <0x0 0x0010f000 0x0 0x1000>; status = "disabled"; }; aon_hsp: tegra-hsp@c150000 { compatible = "nvidia,tegra186-hsp"; reg = <0x0 0x0c150000 0x0 0x00090000>; interrupts = <0 133 0x4>, <0 134 0x4>, <0 135 0x4>, <0 136 0x4>; interrupt-names = "shared1", "shared2", "shared3", "shared4"; status = "disabled"; }; hsp_top: tegra-hsp@3c00000 { compatible = "nvidia,tegra186-hsp"; reg = <0x0 0x03c00000 0x0 0x000a0000>; interrupts = <0 176 0x4>, <0 120 0x4>, <0 121 0x4>, <0 122 0x4>, <0 123 0x4>, <0 124 0x4>, <0 125 0x4>, <0 126 0x4>, <0 127 0x4>; interrupt-names = "doorbell", "shared0", "shared1", "shared2", "shared3", "shared4", "shared5", "shared6", "shared7"; nvidia,mbox-ie; status = "disabled"; }; sce_hsp: tegra-hsp@b150000 { compatible = "nvidia,tegra186-hsp"; reg = <0x0 0x0b150000 0x0 0x00090000>; interrupts = <0 141 0x4>, <0 142 0x4>, <0 143 0x4>, <0 144 0x4>; interrupt-names = "shared1", "shared2", "shared3", "shared4"; nvidia,mbox-ie; status = "disabled"; }; hsp_rce: tegra-hsp@b950000 { compatible = "nvidia,tegra186-hsp"; reg = <0x0 0x0b950000 0x0 0x00090000>; interrupts = <0 182 0x4>, <0 183 0x4>, <0 184 0x4>, <0 185 0x4>; nvidia,mbox-ie; interrupt-names = "shared1", "shared2", "shared3", "shared4"; status = "disabled"; }; efuse@3820000 { compatible = "nvidia,tegra194-efuse"; reg = <0x0 0x03820000 0x0 0x600>; clocks = <&bpmp_clks 40U>, <&bpmp_clks 14U>; clock-names = "fuse", "clk_m"; nvidia,clock-always-on; status = "disabled"; efuse-burn { compatible = "nvidia,tegra194-efuse-burn"; clocks = <&bpmp_clks 14U>; clock-names = "clk_m"; status = "disabled"; }; }; kfuse@3830000 { compatible = "nvidia,tegra194-kfuse"; reg = <0x0 0x3830000 0x0 0x10000>; clocks = <&bpmp_clks 70U>; clock-names = "kfuse"; status = "disabled"; }; bpmp: bpmp { compatible = "nvidia,tegra186-bpmp"; iommus = <&smmu 0x32>; dma-coherent; reg = <0x0 0x0d000000 0x0 0x00800000>, <0x0 0x4004e000 0x0 0x00001000>, <0x0 0x4004f000 0x0 0x00001000>; status = "disabled"; #power-domain-cells = <1>; #strap-cells = <1>; #nvidia,controller-id-cells = <1>; }; se: se_elp@3ad0000 { compatible = "nvidia,tegra194-se-elp"; reg = <0x0 0x03ad0000 0x0 0x10000>, <0x0 0x03ae0000 0x0 0x10000>; interrupts = <0 283 0x04>; clocks = <&bpmp_clks 124U>; clock-names = "se"; pka1-rsa-priority = <300>; status = "disabled"; }; host1x: host1x { compatible = "nvidia,tegra194-host1x", "simple-bus"; reg = <0x0 0x13e10000 0x0 0x00010000>, <0x0 0x13e00000 0x0 0x00010000>, <0x0 0x13ec0000 0x0 0x00040000>, <0x0 0x60000000 0x0 0x00400000>; reg-names = "guest", "hypervisor", "actmon", "sem-syncpt-shim"; interrupts = <0 265 0x04>, <0 263 0x04>; nvidia,ignore-dt-update; wakeup_capable; resets = <&bpmp_resets 23U>; clocks = <&bpmp_clks 46U>, <&bpmp_clks 1U>; clock-names = "host1x", "actmon"; nvidia,vmid = <1>; iommus = <&smmu 0x1>, <&smmu 0x40>, <&smmu 0x41>, <&smmu 0x42>, <&smmu 0x43>, <&smmu 0x44>, <&smmu 0x45>, <&smmu 0x46>, <&smmu 0x47>; dma-coherent; #address-cells = <2>; #size-cells = <2>; ranges; host1x_ctx0: ctx0 { compatible = "nvidia,tegra186-iommu-context"; iommus = <&smmu 0x38>; dma-coherent; status = "disabled"; }; host1x_ctx1: ctx1 { compatible = "nvidia,tegra186-iommu-context"; iommus = <&smmu 0x39>; dma-coherent; status = "disabled"; }; host1x_ctx2: ctx2 { compatible = "nvidia,tegra186-iommu-context"; iommus = <&smmu 0x3a>; dma-coherent; status = "disabled"; }; host1x_ctx3: ctx3 { compatible = "nvidia,tegra186-iommu-context"; iommus = <&smmu 0x3b>; dma-coherent; status = "disabled"; }; host1x_ctx4: ctx4 { compatible = "nvidia,tegra186-iommu-context"; iommus = <&smmu 0x3c>; dma-coherent; status = "disabled"; }; host1x_ctx5: ctx5 { compatible = "nvidia,tegra186-iommu-context"; iommus = <&smmu 0x3d>; dma-coherent; status = "disabled"; }; host1x_ctx6: ctx6 { compatible = "nvidia,tegra186-iommu-context"; iommus = <&smmu 0x3e>; dma-coherent; status = "disabled"; }; host1x_ctx7: ctx7 { compatible = "nvidia,tegra186-iommu-context"; iommus = <&smmu 0x3f>; dma-coherent; status = "disabled"; }; vic@15340000 { compatible = "nvidia,tegra194-vic"; power-domains = <&bpmp 13U>; reg = <0x0 0x15340000 0x0 0x00040000>; interrupts = <0 206 0x04>; resets = <&bpmp_resets 113U>; clocks = <&bpmp_clks 167U>; clock-names = "vic"; iommus = <&smmu 0x3>; iommu-group-id = <0x1>; dma-coherent; }; nvjpg@15380000 { compatible = "nvidia,tegra194-nvjpg"; power-domains = <&bpmp 7U>; reg = <0x0 0x15380000 0x0 0x00040000>; resets = <&bpmp_resets 61U>; clocks = <&bpmp_clks 90U>; clock-names = "nvjpg"; iommus = <&smmu 0x8>; iommu-group-id = <0x1>; dma-coherent; }; tsec@15500000 { compatible = "nvidia,tegra194-tsec"; reg = <0x0 0x15500000 0x0 0x00040000>; resets = <&bpmp_resets 98U>; clocks = <&bpmp_clks 153U>, <&bpmp_clks 40U>; clock-names = "tsec", "efuse"; iommus = <&smmu 0xa>; iommu-group-id = <0x1>; dma-coherent; }; tsecb@15100000 { compatible = "nvidia,tegra194-tsec"; reg = <0x0 0x15100000 0x0 0x00040000>; resets = <&bpmp_resets 99U>; clocks = <&bpmp_clks 154U>, <&bpmp_clks 40U>; clock-names = "tsecb", "efuse"; iommus = <&smmu 0xb>; iommu-group-id = <0x1>; dma-coherent; }; nvdec@15480000 { compatible = "nvidia,tegra194-nvdec"; power-domains = <&bpmp 6U>; reg = <0x0 0x15480000 0x0 0x00040000>; resets = <&bpmp_resets 44U>; clocks = <&bpmp_clks 83U>, <&bpmp_clks 70U>, <&bpmp_clks 40U>; clock-names = "nvdec", "kfuse", "efuse"; iommus = <&smmu 0x6>; iommu-group-id = <0x1>; dma-coherent; }; nvdec1@15140000 { compatible = "nvidia,tegra194-nvdec"; power-domains = <&bpmp 10U>; reg = <0x0 0x15140000 0x0 0x00040000>; resets = <&bpmp_resets 115U>; clocks = <&bpmp_clks 187U>, <&bpmp_clks 70U>, <&bpmp_clks 40U>; clock-names = "nvdec", "kfuse", "efuse"; iommus = <&smmu 0x5C>; iommu-group-id = <0x1>; dma-coherent; }; nvenc@154c0000 { compatible = "nvidia,tegra194-nvenc"; power-domains = <&bpmp 8U>; reg = <0x0 0x154c0000 0x0 0x00040000>; resets = <&bpmp_resets 59U>; clocks = <&bpmp_clks 89U>; clock-names = "nvenc"; iommus = <&smmu 0x7>; iommu-group-id = <0x1>; dma-coherent; }; nvenc1@15a80000 { compatible = "nvidia,tegra194-nvenc"; power-domains = <&bpmp 9U>; reg = <0x0 0x15a80000 0x0 0x00040000>; resets = <&bpmp_resets 60U>; clocks = <&bpmp_clks 188U>; clock-names = "nvenc"; iommus = <&smmu 0x55>; iommu-group-id = <0x1>; dma-coherent; }; nvdla0: nvdla0@15880000 { compatible = "nvidia,tegra194-nvdla"; power-domains = <&bpmp 24U>; reg = <0x0 0x15880000 0x0 0x00040000>; interrupts = <0 236 0x04>; resets = <&bpmp_resets 6U>; clocks = <&bpmp_clks 175U>, <&bpmp_clks 174U>; clock-names = "nvdla0", "nvdla0_flcn"; iommus = <&smmu 0x51>; iommu-group-id = <0x1>; dma-coherent; }; nvdla1: nvdla1@158c0000 { compatible = "nvidia,tegra194-nvdla"; power-domains = <&bpmp 25U>; reg = <0x0 0x158c0000 0x0 0x00040000>; interrupts = <0 237 0x04>; resets = <&bpmp_resets 7U>; clocks = <&bpmp_clks 177U>, <&bpmp_clks 176U>; clock-names = "nvdla1", "nvdla1_flcn"; iommus = <&smmu 0x52>; iommu-group-id = <0x1>; dma-coherent; }; dc_common { compatible = "nvidia,tegra_dc_common"; reg = <0x0 0x15200000 0x0 0x40000>; nvidia,valid_heads = <0x0>; nvidia,disp_imp_table = <&disp_imp_table>; }; head0: nvdisplay@15200000 { status = "disabled"; compatible = "nvidia,tegra194-dc"; reg = <0x0 0x15200000 0x0 0x10000>; interrupts = <0 153 4>; iommus = <&smmu 0x9>; iso-smmu; non-coherent; nvidia,dc-ctrlnum = <0>; nvidia,cmu-enable = <0x1>; clock-names = "nvdisplay_disp", "nvdisplayhub", "nvdisplay_p0", "nvdisplay_p1", "nvdisplay_p2", "nvdisplay_p3", "pllp_display", "pll_d", "plld2", "plld3", "plld4", "emc"; clocks = <&bpmp_clks 85U>, <&bpmp_clks 84U>, <&bpmp_clks 86U>, <&bpmp_clks 87U>, <&bpmp_clks 88U>, <&bpmp_clks 184U>, <&bpmp_clks 102U>, <&bpmp_clks 95U>, <&bpmp_clks 96U>, <&bpmp_clks 97U>, <&bpmp_clks 99U>, <&bpmp_clks 31U>; reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", "wgrp3", "wgrp4", "wgrp5", "head0"; resets = <&bpmp_resets 49U>, <&bpmp_resets 50U>, <&bpmp_resets 51U>, <&bpmp_resets 52U>, <&bpmp_resets 53U>, <&bpmp_resets 54U>, <&bpmp_resets 55U>, <&bpmp_resets 45U>; fb_reserved = <&fb0_reserved>; iommu-direct-regions = <&fb0_reserved &fb1_reserved &fb2_reserved &fb3_reserved>; pinctrl-names = "hdmi-dp0-dpd-disable", "hdmi-dp0-dpd-enable", "hdmi-dp1-dpd-disable", "hdmi-dp1-dpd-enable", "hdmi-dp2-dpd-disable", "hdmi-dp2-dpd-enable", "hdmi-dp3-dpd-disable", "hdmi-dp3-dpd-enable"; pinctrl-0 = <&hdmi_dp0_dpd_disable>; pinctrl-1 = <&hdmi_dp0_dpd_enable>; pinctrl-2 = <&hdmi_dp1_dpd_disable>; pinctrl-3 = <&hdmi_dp1_dpd_enable>; pinctrl-4 = <&hdmi_dp2_dpd_disable>; pinctrl-5 = <&hdmi_dp2_dpd_enable>; pinctrl-6 = <&hdmi_dp3_dpd_disable>; pinctrl-7 = <&hdmi_dp3_dpd_enable>; }; head1: nvdisplay@15210000 { status = "disabled"; compatible = "nvidia,tegra194-dc"; reg = <0x0 0x15210000 0x0 0x10000>; interrupts = <0 154 4>; iommus = <&smmu 0x9>; iso-smmu; non-coherent; nvidia,dc-ctrlnum = <1>; nvidia,cmu-enable = <0x1>; clock-names = "nvdisplay_disp", "nvdisplayhub", "nvdisplay_p0", "nvdisplay_p1", "nvdisplay_p2", "nvdisplay_p3", "pllp_display", "pll_d", "plld2", "plld3", "plld4", "disp2_emc"; clocks = <&bpmp_clks 85U>, <&bpmp_clks 84U>, <&bpmp_clks 86U>, <&bpmp_clks 87U>, <&bpmp_clks 88U>, <&bpmp_clks 184U>, <&bpmp_clks 102U>, <&bpmp_clks 95U>, <&bpmp_clks 96U>, <&bpmp_clks 97U>, <&bpmp_clks 99U>, <&bpmp_clks 31U>; reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", "wgrp3", "wgrp4", "wgrp5", "head1"; resets = <&bpmp_resets 49U>, <&bpmp_resets 50U>, <&bpmp_resets 51U>, <&bpmp_resets 52U>, <&bpmp_resets 53U>, <&bpmp_resets 54U>, <&bpmp_resets 55U>, <&bpmp_resets 46U>; fb_reserved = <&fb1_reserved>; iommu-direct-regions = <&fb0_reserved &fb1_reserved &fb2_reserved &fb3_reserved>; pinctrl-names = "hdmi-dp0-dpd-disable", "hdmi-dp0-dpd-enable", "hdmi-dp1-dpd-disable", "hdmi-dp1-dpd-enable", "hdmi-dp2-dpd-disable", "hdmi-dp2-dpd-enable", "hdmi-dp3-dpd-disable", "hdmi-dp3-dpd-enable"; pinctrl-0 = <&hdmi_dp0_dpd_disable>; pinctrl-1 = <&hdmi_dp0_dpd_enable>; pinctrl-2 = <&hdmi_dp1_dpd_disable>; pinctrl-3 = <&hdmi_dp1_dpd_enable>; pinctrl-4 = <&hdmi_dp2_dpd_disable>; pinctrl-5 = <&hdmi_dp2_dpd_enable>; pinctrl-6 = <&hdmi_dp3_dpd_disable>; pinctrl-7 = <&hdmi_dp3_dpd_enable>; }; head2: nvdisplay@15220000 { status = "disabled"; compatible = "nvidia,tegra194-dc"; reg = <0x0 0x15220000 0x0 0x10000>; interrupts = <0 155 4>; iommus = <&smmu 0x9>; iso-smmu; non-coherent; nvidia,dc-ctrlnum = <2>; nvidia,cmu-enable = <0x1>; clock-names = "nvdisplay_disp", "nvdisplayhub", "nvdisplay_p0", "nvdisplay_p1", "nvdisplay_p2", "nvdisplay_p3", "pllp_display", "pll_d", "plld2", "plld3", "plld4", "disp3_emc"; clocks = <&bpmp_clks 85U>, <&bpmp_clks 84U>, <&bpmp_clks 86U>, <&bpmp_clks 87U>, <&bpmp_clks 88U>, <&bpmp_clks 184U>, <&bpmp_clks 102U>, <&bpmp_clks 95U>, <&bpmp_clks 96U>, <&bpmp_clks 97U>, <&bpmp_clks 99U>, <&bpmp_clks 31U>; reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", "wgrp3", "wgrp4", "wgrp5", "head2"; resets = <&bpmp_resets 49U>, <&bpmp_resets 50U>, <&bpmp_resets 51U>, <&bpmp_resets 52U>, <&bpmp_resets 53U>, <&bpmp_resets 54U>, <&bpmp_resets 55U>, <&bpmp_resets 47U>; fb_reserved = <&fb2_reserved>; iommu-direct-regions = <&fb0_reserved &fb1_reserved &fb2_reserved &fb3_reserved>; pinctrl-names = "hdmi-dp0-dpd-disable", "hdmi-dp0-dpd-enable", "hdmi-dp1-dpd-disable", "hdmi-dp1-dpd-enable", "hdmi-dp2-dpd-disable", "hdmi-dp2-dpd-enable", "hdmi-dp3-dpd-disable", "hdmi-dp3-dpd-enable"; pinctrl-0 = <&hdmi_dp0_dpd_disable>; pinctrl-1 = <&hdmi_dp0_dpd_enable>; pinctrl-2 = <&hdmi_dp1_dpd_disable>; pinctrl-3 = <&hdmi_dp1_dpd_enable>; pinctrl-4 = <&hdmi_dp2_dpd_disable>; pinctrl-5 = <&hdmi_dp2_dpd_enable>; pinctrl-6 = <&hdmi_dp3_dpd_disable>; pinctrl-7 = <&hdmi_dp3_dpd_enable>; }; head3: nvdisplay@15230000 { status = "disabled"; compatible = "nvidia,tegra194-dc"; reg = <0x0 0x15230000 0x0 0x10000>; interrupts = <0 242 4>; iommus = <&smmu 0x9>; iso-smmu; non-coherent; nvidia,dc-ctrlnum = <3>; nvidia,cmu-enable = <0x1>; clock-names = "nvdisplay_disp", "nvdisplayhub", "nvdisplay_p0", "nvdisplay_p1", "nvdisplay_p2", "nvdisplay_p3", "pllp_display", "pll_d", "plld2", "plld3", "plld4", "disp4_emc"; clocks = <&bpmp_clks 85U>, <&bpmp_clks 84U>, <&bpmp_clks 86U>, <&bpmp_clks 87U>, <&bpmp_clks 88U>, <&bpmp_clks 184U>, <&bpmp_clks 102U>, <&bpmp_clks 95U>, <&bpmp_clks 96U>, <&bpmp_clks 97U>, <&bpmp_clks 99U>, <&bpmp_clks 31U>; reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", "wgrp3", "wgrp4", "wgrp5", "head3"; resets = <&bpmp_resets 49U>, <&bpmp_resets 50U>, <&bpmp_resets 51U>, <&bpmp_resets 52U>, <&bpmp_resets 53U>, <&bpmp_resets 54U>, <&bpmp_resets 55U>, <&bpmp_resets 48U>; fb_reserved = <&fb3_reserved>; iommu-direct-regions = <&fb0_reserved &fb1_reserved &fb2_reserved &fb3_reserved>; pinctrl-names = "hdmi-dp0-dpd-disable", "hdmi-dp0-dpd-enable", "hdmi-dp1-dpd-disable", "hdmi-dp1-dpd-enable", "hdmi-dp2-dpd-disable", "hdmi-dp2-dpd-enable", "hdmi-dp3-dpd-disable", "hdmi-dp3-dpd-enable"; pinctrl-0 = <&hdmi_dp0_dpd_disable>; pinctrl-1 = <&hdmi_dp0_dpd_enable>; pinctrl-2 = <&hdmi_dp1_dpd_disable>; pinctrl-3 = <&hdmi_dp1_dpd_enable>; pinctrl-4 = <&hdmi_dp2_dpd_disable>; pinctrl-5 = <&hdmi_dp2_dpd_enable>; pinctrl-6 = <&hdmi_dp3_dpd_disable>; pinctrl-7 = <&hdmi_dp3_dpd_enable>; }; sor0: sor { status = "disabled"; compatible = "nvidia,tegra194-sor"; reg = <0x0 0x15B00000 0x0 0x40000>; nvidia,sor-ctrlnum = <0>; nvidia,dpaux = <&dpaux0>; nvidia,xbar-ctrl = <0x2 0x1 0x0 0x3 0x4>; clocks = <&bpmp_clks 126U>, <&bpmp_clks 131U>, <&bpmp_clks 127U>, <&bpmp_clks 125U>, <&bpmp_clks 98U>, <&bpmp_clks 102U>, <&bpmp_clks 71U>, <&bpmp_clks 43U>, <&bpmp_clks 44U>, <&bpmp_clks 45U>; clock-names = "sor0_ref", "sor_safe", "sor0_pad_clkout", "sor0", "pll_dp", "pllp_out0", "maud", "hda", "hda2codec_2x", "hda2hdmi"; resets = <&bpmp_resets 87U>, <&bpmp_resets 20U>, <&bpmp_resets 21U>, <&bpmp_resets 22U>; reset-names = "sor0","hda_rst", "hda2codec_2x_rst", "hda2hdmi_rst"; sor0_hdmi_display: hdmi-display { compatible = "hdmi,display"; status = "disabled"; }; sor0_dp_display: dp-display { compatible = "dp, display"; status = "disabled"; }; }; sor1: sor1 { status = "disabled"; compatible = "nvidia,tegra194-sor"; reg = <0x0 0x15B40000 0x0 0x40000>; nvidia,sor-ctrlnum = <1>; nvidia,dpaux = <&dpaux1>; nvidia,xbar-ctrl = <0x2 0x1 0x0 0x3 0x4>; clocks = <&bpmp_clks 129U>, <&bpmp_clks 131U>, <&bpmp_clks 130U>, <&bpmp_clks 128U>, <&bpmp_clks 98U>, <&bpmp_clks 102U>, <&bpmp_clks 71U>, <&bpmp_clks 43U>, <&bpmp_clks 44U>, <&bpmp_clks 45U>; clock-names = "sor1_ref", "sor_safe", "sor1_pad_clkout", "sor1", "pll_dp", "pllp_out0", "maud", "hda", "hda2codec_2x", "hda2hdmi"; resets = <&bpmp_resets 88U>, <&bpmp_resets 20U>, <&bpmp_resets 21U>, <&bpmp_resets 22U>; reset-names = "sor1","hda_rst", "hda2codec_2x_rst", "hda2hdmi_rst"; sor1_hdmi_display: hdmi-display { compatible = "hdmi,display"; status = "disabled"; }; sor1_dp_display: dp-display { compatible = "dp, display"; status = "disabled"; }; }; sor2: sor2 { status = "disabled"; compatible = "nvidia,tegra194-sor"; reg = <0x0 0x15B80000 0x0 0x40000>; nvidia,sor-ctrlnum = <2>; nvidia,dpaux = <&dpaux2>; nvidia,xbar-ctrl = <0x2 0x1 0x0 0x3 0x4>; clocks = <&bpmp_clks 179U>, <&bpmp_clks 131U>, <&bpmp_clks 180U>, <&bpmp_clks 178U>, <&bpmp_clks 98U>, <&bpmp_clks 102U>, <&bpmp_clks 71U>, <&bpmp_clks 43U>, <&bpmp_clks 44U>, <&bpmp_clks 45U>; clock-names = "sor2_ref", "sor_safe", "sor2_pad_clkout", "sor2", "pll_dp", "pllp_out0", "maud", "hda", "hda2codec_2x", "hda2hdmi"; resets = <&bpmp_resets 89U>, <&bpmp_resets 20U>, <&bpmp_resets 21U>, <&bpmp_resets 22U>; reset-names = "sor2","hda_rst", "hda2codec_2x_rst", "hda2hdmi_rst"; sor2_hdmi_display: hdmi-display { compatible = "hdmi,display"; status = "disabled"; }; sor2_dp_display: dp-display { compatible = "dp, display"; status = "disabled"; }; }; sor3: sor3 { status = "disabled"; compatible = "nvidia,tegra194-sor"; reg = <0x0 0x15BC0000 0x0 0x40000>; nvidia,sor-ctrlnum = <3>; nvidia,dpaux = <&dpaux3>; nvidia,xbar-ctrl = <0x2 0x1 0x0 0x3 0x4>; clocks = <&bpmp_clks 182U>, <&bpmp_clks 131U>, <&bpmp_clks 183U>, <&bpmp_clks 181U>, <&bpmp_clks 98U>, <&bpmp_clks 102U>, <&bpmp_clks 71U>, <&bpmp_clks 43U>, <&bpmp_clks 44U>, <&bpmp_clks 45U>; clock-names = "sor3_ref", "sor_safe", "sor3_pad_clkout", "sor3", "pll_dp", "pllp_out0", "maud", "hda", "hda2codec_2x", "hda2hdmi"; resets = <&bpmp_resets 90U>, <&bpmp_resets 20U>, <&bpmp_resets 21U>, <&bpmp_resets 22U>; reset-names = "sor3","hda_rst", "hda2codec_2x_rst", "hda2hdmi_rst"; sor3_hdmi_display: hdmi-display { compatible = "hdmi,display"; status = "disabled"; }; sor3_dp_display: dp-display { compatible = "dp, display"; status = "disabled"; }; }; dpaux0: dpaux@155c0000 { status = "disabled"; compatible = "nvidia,tegra194-dpaux"; reg = <0x0 0x155c0000 0x0 0x00010000>; interrupts = <0 159 4>; nvidia,dpaux-ctrlnum = <0>; clocks = <&bpmp_clks 19U>; clock-names = "dpaux"; resets = <&bpmp_resets 8U>; reset-names = "dpaux"; power-domains = <&disa_pd>; }; dpaux1: dpaux@155D0000 { status = "disabled"; compatible = "nvidia,tegra194-dpaux"; reg = <0x0 0x155D0000 0x0 0x00010000>; interrupts = <0 160 4>; nvidia,dpaux-ctrlnum = <1>; clocks = <&bpmp_clks 20U>; clock-names = "dpaux1"; resets = <&bpmp_resets 9U>; reset-names = "dpaux1"; power-domains = <&disa_pd>; }; dpaux2: dpaux@155E0000 { status = "disabled"; compatible = "nvidia,tegra194-dpaux"; reg = <0x0 0x155E0000 0x0 0x00010000>; interrupts = <0 245 4>; nvidia,dpaux-ctrlnum = <2>; clocks = <&bpmp_clks 185U>; clock-names = "dpaux2"; resets = <&bpmp_resets 10U>; reset-names = "dpaux2"; power-domains = <&disa_pd>; }; dpaux3: dpaux@155F0000 { status = "disabled"; compatible = "nvidia,tegra194-dpaux"; reg = <0x0 0x155F0000 0x0 0x00010000>; interrupts = <0 246 4>; nvidia,dpaux-ctrlnum = <3>; clocks = <&bpmp_clks 186U>; clock-names = "dpaux3"; resets = <&bpmp_resets 11U>; reset-names = "dpaux3"; power-domains = <&disa_pd>; }; tegra_cec: tegra_cec { status = "disabled"; compatible = "nvidia,tegra194-cec"; reg = <0x0 0x03960000 0x0 0x00001000>; interrupts = <0 162 0x04>; clocks = <&bpmp_clks 13U>; clock-names = "cec"; }; vi: vi@15c10000 { compatible = "nvidia,tegra194-vi"; reg = <0x0 0x15c10000 0x0 0x00230000>, <0x0 0x15f00000 0x0 0x00100000>; resets = <&bpmp_resets 112U>, <&bpmp_resets 97U>; reset-names = "vi", "tsctnvi"; clocks = <&bpmp_clks 166U>, <&bpmp_clks 196U>, <&bpmp_clks 81U>, <&bpmp_clks 82U>; clock-names = "vi", "vi-const", "nvcsi", "nvcsilp"; power-domains = <&bpmp 12U>; nvidia,vi-falcon-device = <&vi_thi>; iommus = <&smmu 0x4>; iso-smmu; non-coherent; }; vi_thi: vi-thi@15f00000 { compatible = "nvidia,tegra194-vi-thi"; clocks = <&bpmp_clks 166U>, <&bpmp_clks 196U>; clock-names = "vi", "vi-const"; power-domains = <&bpmp 12U>; }; isp: isp@14800000 { compatible = "nvidia,tegra194-isp"; reg = <0x0 0x14800000 0x0 0x00010000>; resets = <&bpmp_resets 36U>; reset-names = "isp"; clocks = <&bpmp_clks 69U>; clock-names = "isp"; power-domains = <&bpmp 5U>; nvidia,isp-falcon-device = <&isp_thi>; iommus = <&smmu 0x5>; dma-coherent; }; isp_thi: isp-thi@14b00000 { compatible = "nvidia,tegra194-isp-thi"; reg = <0x0 0x14b00000 0x0 0x00100000>; }; nvcsi: nvcsi@15a00000 { compatible = "nvidia,tegra194-nvcsi"; reg = <0x0 0x15a00000 0x0 0x00050000>; power-domains = <&bpmp 12U>; resets = <&bpmp_resets 43U>; clocks = <&bpmp_clks 81U>, <&bpmp_clks 82U>; clock-names = "nvcsi", "nvcsilp"; interrupts = <0 119 0x04>; num-ports = <6>; }; slvs_ec: slvs-ec@15ac0000 { compatible = "nvidia,tegra-slvs-ec"; power-domains = <&bpmp 12U>; reg = <0x0 0x15ac0000 0x0 0x00040000>, <0x0 0x15c00000 0x0 0x00010000>, <0x0 0x15e40000 0x0 0x00010000>; resets = <&bpmp_resets 127U>; reset-names = "slvs-ec"; clocks = <&bpmp_clks 252U>, <&bpmp_clks 253U>, <&bpmp_clks 102U>; clock-names = "slvs-ec", "slvs-ec-lp", "slvs-ec-parent"; interrupts = <0 74 0x04>, <0 255 0x04>; nvidia,vi-device = <&vi_thi>; interrupt-names = "slvs-ec", "syncgen"; status = "disabled"; }; pva0: pva0 { compatible = "nvidia,tegra194-pva"; power-domains = <&bpmp 22U>; reg = <0x0 0x16000000 0x0 0x800000>; interrupts = <0 234 0x04>; resets = <&bpmp_resets 66U>; clocks = <&bpmp_clks 168U>, <&bpmp_clks 169U>, <&bpmp_clks 170U>; clock-names = "axi", "vps0", "vps1"; iommus = <&smmu 0x53>; dma-coherent; }; pva1: pva1 { compatible = "nvidia,tegra194-pva"; power-domains = <&bpmp 23U>; reg = <0x0 0x16800000 0x0 0x800000>; interrupts = <0 235 0x04>; resets = <&bpmp_resets 67U>; clocks = <&bpmp_clks 171U>, <&bpmp_clks 172U>, <&bpmp_clks 173U>; clock-names = "axi", "vps0", "vps1"; iommus = <&smmu 0x54>; dma-coherent; }; se@15810000 { compatible = "nvidia,tegra186-se1-nvhost"; reg = <0x0 0x15810000 0x0 0x10000>; supported-algos = "drbg"; nvidia,io-coherent; opcode_addr = <0x204>; resets = <&bpmp_resets 86U>; clocks = <&bpmp_clks 124U>; clock-names = "se"; iommus = <&smmu 0xc>; iommu-group-id = <0x4>; dma-coherent; status = "disabled"; }; se@15820000 { compatible = "nvidia,tegra186-se2-nvhost"; reg = <0x0 0x15820000 0x0 0x10000>; supported-algos = "xts", "aes", "cmac"; nvidia,io-coherent; opcode_addr = <0x404>; resets = <&bpmp_resets 86U>; clocks = <&bpmp_clks 124U>; clock-names = "se"; iommus = <&smmu 0xd>; iommu-group-id = <0x4>; dma-coherent; status = "disabled"; }; se@15830000 { compatible = "nvidia,tegra186-se3-nvhost"; reg = <0x0 0x15830000 0x0 0x10000>; supported-algos = "rsa"; nvidia,io-coherent; opcode_addr = <0x604>; resets = <&bpmp_resets 86U>; clocks = <&bpmp_clks 124U>; clock-names = "se"; iommus = <&smmu 0xe>; iommu-group-id = <0x4>; dma-coherent; status = "disabled"; }; se@15840000 { compatible = "nvidia,tegra186-se4-nvhost"; reg = <0x0 0x15840000 0x0 0x10000>; supported-algos = "sha"; nvidia,io-coherent; opcode_addr = <0x104>; resets = <&bpmp_resets 86U>; clocks = <&bpmp_clks 124U>; clock-names = "se"; iommus = <&smmu 0xf>; iommu-group-id = <0x4>; dma-coherent; status = "disabled"; }; }; gpcdma: dma@2600000 { compatible = "nvidia,tegra19x-gpcdma", "nvidia,tegra186-gpcdma"; reg = <0x0 0x2600000 0x0 0x210000>; resets = <&bpmp_resets 18U>; reset-names = "gpcdma"; interrupts = <0 75 0x04 0 76 0x04 0 77 0x04 0 78 0x04 0 79 0x04 0 80 0x04 0 81 0x04 0 82 0x04 0 83 0x04 0 84 0x04 0 85 0x04 0 86 0x04 0 87 0x04 0 88 0x04 0 89 0x04 0 90 0x04 0 91 0x04 0 92 0x04 0 93 0x04 0 94 0x04 0 95 0x04 0 96 0x04 0 97 0x04 0 98 0x04 0 99 0x04 0 100 0x04 0 101 0x04 0 102 0x04 0 103 0x04 0 104 0x04 0 105 0x04 0 106 0x04 0 107 0x04>; #dma-cells = <1>; iommus = <&smmu 0x20>; dma-coherent; nvidia,start-dma-channel-index = <1>; dma-channels = <31>; status = "disabled"; }; tegra_pinctrl: pinmux: pinmux@2430000 { compatible = "nvidia,tegra194-pinmux"; reg = <0x0 0x2430000 0x0 0x17000 0x0 0xc300000 0x0 0x4000>; #gpio-range-cells = <3>; status = "disabled"; vbus_en0_sfio_tristate_state: vbus_en0_oc_tristate { usb_vbus_en0_pz1 { nvidia,pins = "usb_vbus_en0_pz1"; nvidia,function = "usb"; nvidia,tristate = <1>; nvidia,io-high-voltage = <1>; nvidia,enable-input = <1>; }; }; vbus_en1_sfio_tristate_state: vbus_en1_oc_tristate { usb_vbus_en1_pz2 { nvidia,pins = "usb_vbus_en1_pz2"; nvidia,function = "usb"; nvidia,tristate = <1>; nvidia,io-high-voltage = <1>; nvidia,enable-input = <1>; }; }; vbus_en0_sfio_passthrough_state: vbus_en0_oc_passthrough { usb_vbus_en0_pz1 { nvidia,pins = "usb_vbus_en0_pz1"; nvidia,function = "usb"; nvidia,tristate = <0>; nvidia,io-high-voltage = <1>; nvidia,enable-input = <1>; }; }; vbus_en1_sfio_passthrough_state: vbus_en1_oc_passthrough { usb_vbus_en1_pz2 { nvidia,pins = "usb_vbus_en1_pz2"; nvidia,function = "usb"; nvidia,tristate = <0>; nvidia,io-high-voltage = <1>; nvidia,enable-input = <1>; }; }; vbus_en0_default_state: vbus_en0_default { usb_vbus_en0_pz1 { nvidia,pins = "usb_vbus_en0_pz1"; nvidia,function = "rsvd1"; nvidia,io-high-voltage = <1>; nvidia,enable-input = <1>; }; }; vbus_en1_default_state: vbus_en1_default { usb_vbus_en1_pz2 { nvidia,pins = "usb_vbus_en1_pz2"; nvidia,function = "rsvd1"; nvidia,io-high-voltage = <1>; nvidia,enable-input = <1>; }; }; }; tegra_main_gpio: gpio@2200000 { compatible = "nvidia,tegra194-gpio"; reg-names = "security", "gpio"; reg = <0x0 0x2200000 0x0 0x10000>, <0x0 0x2210000 0x0 0x10000>; interrupts = <0 288 0x00000004>, <0 289 0x00000004>, <0 290 0x00000004>, <0 291 0x00000004>, <0 292 0x00000004>, <0 293 0x00000004>, <0 294 0x00000004>, <0 295 0x00000004>, <0 296 0x00000004>, <0 297 0x00000004>, <0 298 0x00000004>, <0 299 0x00000004>, <0 300 0x00000004>, <0 301 0x00000004>, <0 302 0x00000004>, <0 303 0x00000004>, <0 304 0x00000004>, <0 305 0x00000004>, <0 306 0x00000004>, <0 307 0x00000004>, <0 308 0x00000004>, <0 309 0x00000004>, <0 310 0x00000004>, <0 311 0x00000004>, <0 312 0x00000004>, <0 313 0x00000004>, <0 314 0x00000004>, <0 315 0x00000004>, <0 316 0x00000004>, <0 317 0x00000004>, <0 318 0x00000004>, <0 319 0x00000004>, <0 320 0x00000004>, <0 321 0x00000004>, <0 322 0x00000004>, <0 323 0x00000004>, <0 324 0x00000004>, <0 325 0x00000004>, <0 326 0x00000004>, <0 327 0x00000004>, <0 328 0x00000004>, <0 329 0x00000004>, <0 330 0x00000004>, <0 331 0x00000004>, <0 332 0x00000004>, <0 333 0x00000004>, <0 334 0x00000004>, <0 335 0x00000004>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tegra_pinctrl (0 * 8) (0 * 8) ((25 - 0 + 1) * 8) >, <&tegra_pinctrl (26 * 8) (31 * 8) ((27 - 26 + 1) * 8) >; status = "disabled"; }; tegra_aon_gpio: gpio@c2f0000 { compatible = "nvidia,tegra194-gpio-aon"; reg-names = "security", "gpio", "gte"; reg = <0x0 0xc2f0000 0x0 0x1000>, <0x0 0xc2f1000 0x0 0x1000>, <0x0 0xc1e0000 0x0 0x10000>; interrupts = <0 56 0x00000004>, <0 57 0x00000004>, <0 58 0x00000004>, <0 59 0x00000004>; status = "disabled"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tegra_pinctrl (0 * 8) (26 * 8) ((4 - 0 + 1) * 8) >; }; tegra_gte_lic: gte@3aa0000 { compatible = "nvidia,tegra194-gte-lic"; reg = <0x0 0x3aa0000 0x0 0x10000>; interrupts = <0 11 0x4>; nvidia,int-threshold = <1>; nvidia,num-slices = <11>; status = "disabled"; }; tegra_gte_aon: gte@c1e0000 { compatible = "nvidia,tegra194-gte-aon"; reg = <0x0 0xc1e0000 0x0 0x10000>; interrupts = <0 13 0x4>; nvidia,int-threshold = <1>; nvidia,num-slices = <3>; nvidia,gpio-controller = <&tegra_aon_gpio>; status = "disabled"; }; tegra_wdt:watchdog@30c0000 { compatible = "nvidia,tegra-wdt-t18x"; reg = <0x0 0x030c0000 0x0 0x10000>, <0x0 0x03020000 0x0 0x10000>, <0x0 0x03010000 0x0 0x10000>; interrupts = <0 7 0x4 0 8 0x4>; nvidia,watchdog-index = <0>; nvidia,timer-index = <7>; nvidia,expiry-count = <5>; nvidia,enable-on-init; nvidia,extend-watchdog-suspend; timeout-sec = <120>; nvidia,disable-debug-reset; status = "disabled"; }; tegra_fiq_debugger { compatible = "nvidia,fiq-debugger"; use-console-port; interrupts = <0 17 0x4>; }; tegra_pcie_pexclk_pinctrl: pinctrl@3790000 { compatible = "nvidia,tegra194-pexclk-padctl"; reg = <0x0 0x03790000 0x0 0x1000>, <0x0 0x037a0000 0x0 0x1000>; status = "disabled"; }; tegra_tachometer: tachometer@39c0000 { compatible = "nvidia,pwm-tegra194-tachometer"; reg = <0x0 0x039c0000 0x0 0x10>; #pwm-cells = <2>; clocks = <&bpmp_clks 152U>; clock-names = "tach"; resets = <&bpmp_resets 95U>; reset-names = "tach"; pulse-per-rev = <2>; capture-window-length = <2>; disable-clk-gate; status = "disabled"; }; generic_pwm_tachometer { compatible = "generic-pwm-tachometer"; pwms = <&tegra_tachometer 0 1000000>; status = "disabled"; }; tegra_pmc: pmc@c360000 { compatible = "nvidia,tegra194-pmc"; reg = <0x0 0xC360000 0x0 0x400 0x0 0xC390000 0x0 0x2fff 0x0 0xC3a0000 0x0 0xfff>; #padcontroller-cells = <1>; nvidia,restrict-voltage-switch; pinctrl-names = "default"; pinctrl-0 = <&iopad_defaults>; status = "disabled"; iopad_defaults: iopad-defaults { }; hdmi_dp0_dpd_enable: hdmi-dp0-dpd-enable { hdmi-dp0-pad-lowpower-enable { pins = "hdmi-dp0"; low-power-enable; }; }; hdmi_dp0_dpd_disable: hdmi-dp0-dpd-disable { hdmi-dp0-pad-lowpower-disable { pins = "hdmi-dp0"; low-power-disable; }; }; hdmi_dp1_dpd_enable: hdmi-dp1-dpd-enable { hdmi-dp1-pad-lowpower-enable { pins = "hdmi-dp1"; low-power-enable; }; }; hdmi_dp1_dpd_disable: hdmi-dp1-dpd-disable { hdmi-dp1-pad-lowpower-disable { pins = "hdmi-dp1"; low-power-disable; }; }; hdmi_dp2_dpd_enable: hdmi-dp2-dpd-enable { hdmi-dp2-pad-lowpower-enable { pins = "hdmi-dp2"; low-power-enable; }; }; hdmi_dp2_dpd_disable: hdmi-dp2-dpd-disable { hdmi-dp2-pad-lowpower-disable { pins = "hdmi-dp2"; low-power-disable; }; }; hdmi_dp3_dpd_enable: hdmi-dp3-dpd-enable { hdmi-dp3-pad-lowpower-enable { pins = "hdmi-dp3"; low-power-enable; }; }; hdmi_dp3_dpd_disable: hdmi-dp3-dpd-disable { hdmi-dp3-pad-lowpower-disable { pins = "hdmi-dp3"; low-power-disable; }; }; }; tegra_aowake: pmc@c370000 { compatible = "nvidia,tegra194-aowake"; reg = <0x0 0xc370000 0x0 0x600>; status = "disabled"; }; gpio-keys { compatible = "gpio-keys"; gpio-keys,name = "gpio-keys"; status = "disabled"; sw_wake { label = "sw-wake"; interrupt-parent = <&tegra_pm_irq>; interrupts = <0 179 0x00000004>; linux,code = <116>; wakeup-source; }; }; xusb_padctl: xusb_padctl@3520000 { compatible = "nvidia,tegra19x-xusb-padctl"; reg = <0x0 0x03520000 0x0 0x1000>, <0x0 0x03540000 0x0 0x1000>; reg-names = "padctl", "ao"; interrupts = <0 167 0x4>; resets = <&bpmp_resets 114U>; reset-names = "padctl"; status = "disabled"; pads { usb2 { clocks = <&bpmp_clks 165U>; clock-names = "trk"; lanes { usb2-0 { status = "disabled"; #phy-cells = <0>; }; usb2-1 { status = "disabled"; #phy-cells = <0>; }; usb2-2 { status = "disabled"; #phy-cells = <0>; }; usb2-3 { status = "disabled"; #phy-cells = <0>; }; }; }; usb3 { lanes { usb3-0 { status = "disabled"; #phy-cells = <0>; }; usb3-1 { status = "disabled"; #phy-cells = <0>; }; usb3-2 { status = "disabled"; #phy-cells = <0>; }; usb3-3 { status = "disabled"; #phy-cells = <0>; }; }; }; }; ports { usb2-0 { status = "disabled"; }; usb2-1 { status = "disabled"; }; usb2-2 { status = "disabled"; }; usb2-3 { status = "disabled"; }; usb3-0 { status = "disabled"; }; usb3-1 { status = "disabled"; }; usb3-2 { status = "disabled"; }; usb3-3 { status = "disabled"; }; }; }; tegra_usb_cd: usb_cd { compatible = "nvidia,tegra194-usb-cd"; nvidia,xusb-padctl = <&xusb_padctl>; phys = <&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-0}>; phy-names = "otg-phy"; status = "okay"; }; tegra_xudc: xudc@3550000 { compatible = "nvidia,tegra194-xudc"; reg = <0x0 0x03550000 0x0 0x8000>, <0x0 0x03558000 0x0 0x1000>; interrupts = <0 166 0x4>; clocks = <&bpmp_clks 265U>, <&bpmp_clks 277U>, <&bpmp_clks 275U>, <&bpmp_clks 272U>; nvidia,xusb-padctl = <&xusb_padctl>; iommus = <&smmu 0x1c>; dma-coherent; status = "disabled"; }; tegra_xhci: xhci@3610000 { compatible = "nvidia,tegra194-xhci"; reg = <0x0 0x03610000 0x0 0x40000>, <0x0 0x03600000 0x0 0x10000>; interrupts = <0 163 0x4>, <0 164 0x4>, <0 167 0x4>; interrupt-parent = <&tegra_pm_irq>; clocks = <&bpmp_clks 266U>, <&bpmp_clks 267U>, <&bpmp_clks 268U>, <&bpmp_clks 269U>, <&bpmp_clks 270U>, <&bpmp_clks 271U>, <&bpmp_clks 272U>, <&bpmp_clks 273U>, <&bpmp_clks 275U>, <&bpmp_clks 277U>, <&bpmp_clks 103U>, <&bpmp_clks 14U>, <&bpmp_clks 100U>; clock-names = "xusb_hs_src", "xusb_host", "xusb_core_superspeed_clk", "xusb_falcon_src", "xusb_falcon_host_clk", "xusb_falcon_superspeed_clk", "xusb_fs_src", "xusb_fs_host_clk", "xusb_ss_src", "xusb_ss", "pll_u_480m", "clk_m", "pll_e"; nvidia,xusb-padctl = <&xusb_padctl>; iommus = <&smmu 0x1b>; dma-coherent; status = "disabled"; }; tegra_xhci_vf1: xhci@3660000 { compatible = "nvidia,tegra194-xhci-vf1"; reg = <0x0 0x03660000 0x0 0x40000>; interrupts = <0 21 0x4>; nvidia,xusb-padctl = <&xusb_padctl>; iommus = <&smmu 0x5d>; dma-coherent; status = "disabled"; }; tegra_xhci_vf2: xhci@36b0000 { compatible = "nvidia,tegra194-xhci-vf2"; reg = <0x0 0x036b0000 0x0 0x40000>; interrupts = <0 22 0x4>; nvidia,xusb-padctl = <&xusb_padctl>; iommus = <&smmu 0x5e>; dma-coherent; status = "disabled"; }; tegra_xhci_vf3: xhci@3700000 { compatible = "nvidia,tegra194-xhci-vf3"; reg = <0x0 0x03700000 0x0 0x40000>; interrupts = <0 23 0x4>; nvidia,xusb-padctl = <&xusb_padctl>; iommus = <&smmu 0x5f>; dma-coherent; status = "disabled"; }; tegra_xhci_vf4: xhci@3750000 { compatible = "nvidia,tegra194-xhci-vf4"; reg = <0x0 0x03750000 0x0 0x40000>; interrupts = <0 24 0x4>; nvidia,xusb-padctl = <&xusb_padctl>; iommus = <&smmu 0x60>; dma-coherent; status = "disabled"; }; gv11b { compatible = "nvidia,gv11b"; reg = <0x0 0x17000000 0x0 0x1000000 0x0 0x18000000 0x0 0x1000000 0x0 0x03b41000 0x0 0x00001000>; interrupts = <0 70 0x04 0 71 0x04>; dma-noncontig; interrupt-names = "stall", "nonstall"; nvidia,host1x = <&host1x>; access-vpr-phys; clocks = <&bpmp_clks 41U>, <&bpmp_clks 42U>; clock-names = "gpu", "gpu_sys"; resets = <&bpmp_resets 19U>; dma-coherent; status = "disabled"; }; psci { compatible = "arm,psci-1.0"; method = "smc"; cpu_off = <0x84000002>; cpu_on = <0xC4000003>; cpu_suspend = <0xC4000001>; status = "disabled"; }; bwmgr: bwmgr { compatible = "nvidia,bwmgr"; clocks = <&bpmp_clks 31U>; clock-names = "emc"; cdev-type = "bwmgr-therm-handler"; cooling-min-state = <0>; cooling-max-state = <1>; #cooling-cells = <2>; status = "okay"; }; tegra_hv_xhci_debug@0 { compatible = "nvidia,tegra-hv-xhci-debug"; status = "disabled"; }; arm64_ras: arm64_ras { compatible = "arm,armv8.2-ras"; interrupts = <0 392 0x04>, <0 393 0x04>, <0 394 0x04>, <0 395 0x04>, <0 396 0x04>, <0 397 0x04>, <0 398 0x04>, <0 399 0x04>; status = "disabled"; }; carmel_ras { compatible = "nvidia,carmel-ras"; status = "disabled"; }; cpufreq { compatible = "nvidia,tegra194-cpufreq"; status = "disabled"; cpu_emc_map = <2112000 2133000>, <1881600 800000>, <1574400 665000>, <1267200 408000>; }; cbb-noc@2300000 { compatible = "nvidia,tegra194-CBB-NOC"; reg = <0x0 0x02300000 0x0 0x1000>; interrupts = <0 230 4>, <0 231 4>; status = "disabled"; }; aon-noc@C600000 { compatible = "nvidia,tegra194-AON-NOC"; reg = <0x0 0xC600000 0x0 0x1000>; interrupts = <0 260 4>, <0 172 4>; status = "disabled"; }; bpmp-noc@D600000 { compatible = "nvidia,tegra194-BPMP-NOC"; reg = <0x0 0xD600000 0x0 0x1000>; interrupts = <0 262 4>, <0 174 4>; status = "disabled"; }; rce-noc@BE00000 { compatible = "nvidia,tegra194-RCE-NOC"; reg = <0x0 0xBE00000 0x0 0x1000>; interrupts = <0 259 4>, <0 175 4>; status = "disabled"; }; sce-noc@B600000 { compatible = "nvidia,tegra194-SCE-NOC"; reg = <0x0 0xB600000 0x0 0x1000>; interrupts = <0 261 4>, <0 173 4>; status = "disabled"; }; cv-noc@14040000 { compatible = "nvidia,tegra194-CV-NOC"; reg = <0x0 0x14040000 0x0 0x1000>; interrupts = <0 238 4>, <0 239 4>; status = "disabled"; }; axi2apb@2390000 { compatible = "nvidia,tegra194-AXI2APB-bridge"; reg = <0x0 0x02390000 0x0 0x1000>, <0x0 0x023A0000 0x0 0x1000>, <0x0 0x023B0000 0x0 0x1000>, <0x0 0x023C0000 0x0 0x1000>, <0x0 0x023D0000 0x0 0x1000>, <0x0 0x023E0000 0x0 0x1000>; status = "disabled"; }; mipical@3990000{ compatible = "nvidia, tegra194-mipical"; reg = <0x0 0x03990000 0x0 0x10000>; clocks = <&bpmp_clks 72U>, <&bpmp_clks 162U>; clock-names = "mipi_cal", "uart_fs_mipi_cal"; resets = <&bpmp_resets 37U>; reset-names = "mipi_cal"; status = "disabled"; }; tnvlink_controller: tegra_nvlink_controller { compatible = "nvidia,t19x-nvlink-controller"; reg = <0x0 0x3b80000 0x0 0x1000 0x0 0x3b84000 0x0 0x1000 0x0 0x3b86000 0x0 0x1000 0x0 0x3b90000 0x0 0x4000 0x0 0x3b94000 0x0 0x1000 0x0 0x3b96000 0x0 0x1000 0x0 0x1f00000 0x0 0x20000>; clocks = <&bpmp_clks 264U>, <&bpmp_clks 327U>, <&bpmp_clks 259U>, <&bpmp_clks 243U>, <&bpmp_clks 14U>, <&bpmp_clks 325U>, <&bpmp_clks 261U>; clock-names = "nvhs_pll0_mgmt", "pllrefe_vcoout_gated", "nvlink_sys", "pllnvhs", "clk_m", "nvlink_pll_txclk", "nvlink_tx"; resets = <&bpmp_resets 180U>, <&bpmp_resets 143U>, <&bpmp_resets 133U>, <&bpmp_resets 134U>, <&bpmp_resets 135U>, <&bpmp_resets 136U>, <&bpmp_resets 137U>, <&bpmp_resets 138U>, <&bpmp_resets 139U>, <&bpmp_resets 140U>, <&bpmp_resets 141U>, <&bpmp_resets 142U>, <&bpmp_resets 128U>; reset-names = "mssnvl", "nvhs_uphy_pm", "nvhs_uphy", "nvhs_uphy_pll0", "nvhs_uphy_l0", "nvhs_uphy_l1", "nvhs_uphy_l2", "nvhs_uphy_l3", "nvhs_uphy_l4", "nvhs_uphy_l5", "nvhs_uphy_l6", "nvhs_uphy_l7", "nvlink"; interrupts = <0 178 0x4>; status = "disabled"; }; nvpmodel { compatible = "nvidia,nvpmodel"; clocks = <&bpmp_clks 210U>, <&bpmp_clks 216U>, <&bpmp_clks 212U>, <&bpmp_clks 211U>, <&bpmp_clks 213U>; clock-names = "nafll_dla", "nafll_dla_falcon", "nafll_pva_vps", "nafll_pva_core", "nafll_cvnas"; status = "okay"; }; external-connection { disp-state { compatible = "extcon-disp-state"; #extcon-cells = <1>; }; }; }; # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-cvm.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-cpus.dtsi" 1 # 15 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-cpus.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-cpuidle.dtsi" 1 # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-cpuidle.dtsi" / { cpus { CPU_CORE_POWER_STATES: cpu_core_power_states { compatible = "nvidia,tegra194-cpuidle-core"; C1: c1 { compatible = "nvidia,tegra194-cpuidle-core"; state-name = "Clock gated"; wakeup-latency-us = <1>; min-residency-us = <1>; power = <70>; pmstate = <0x1>; status = "okay"; }; C6: c6 { compatible = "nvidia,tegra194-cpuidle-core"; state-name = "Virtual core powergate"; wakeup-latency-us = <2000>; min-residency-us = <0xffffffff>; power = <60>; pmstate = <0x6>; arm,psci-suspend-param= <0x6>; status = "okay"; }; C7: c7 { compatible = "nvidia,tegra194-cpuidle-core"; state-name = "Core powergate"; wakeup-latency-us = <560>; min-residency-us = <0xffffffff>; power = <60>; pmstate = <0x7>; arm,psci-suspend-param= <0x40000007>; status = "disabled"; }; }; cpu_cluster_power_states { compatible = "nvidia,tegra194-cpuidle-cluster"; cc6 { state-name = "Cluster powergate"; wakeup-latency-us = <5000>; min-residency-us = <0xffffffff>; power = <19>; pmstate = <0x6>; status = "okay"; }; }; cpu_crossover_thresholds { compatible = "nvidia,tegra194-cpuidle-thresholds"; thresholds { crossover_c1_c6 = <30000>; crossover_cc1_cc6 = <80000>; }; }; }; }; # 16 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-cpus.dtsi" 2 / { cpus { #address-cells = <2>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cl0_0>; }; core1 { cpu = <&cl0_1>; }; }; cluster1 { core0 { cpu = <&cl1_0>; }; core1 { cpu = <&cl1_1>; }; }; cluster2 { core0 { cpu = <&cl2_0>; }; core1 { cpu = <&cl2_1>; }; }; cluster3 { core0 { cpu = <&cl3_0>; }; core1 { cpu = <&cl3_1>; }; }; }; cl0_0: cpu@0 { device_type = "cpu"; compatible = "nvidia,carmel", "arm,armv8"; reg = <0x0 0x10000>; enable-method = "psci"; cpu-idle-states = <&C6 &C7>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; d-cache-size = <65536>; d-cache-line-size = <64>; d-cache-sets = <256>; l2-cache = <&L2_0>; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_CARMEL &CPU_COST_CARMEL>; }; cl0_1: cpu@1 { device_type = "cpu"; compatible = "nvidia,carmel", "arm,armv8"; reg = <0x0 0x10001>; enable-method = "psci"; cpu-idle-states = <&C6 &C7>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; d-cache-size = <65536>; d-cache-line-size = <64>; d-cache-sets = <256>; l2-cache = <&L2_0>; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_CARMEL &CPU_COST_CARMEL>; status = "disabled"; }; cl1_0: cpu@2 { device_type = "cpu"; compatible = "nvidia,carmel", "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; cpu-idle-states = <&C6 &C7>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; d-cache-size = <65536>; d-cache-line-size = <64>; d-cache-sets = <256>; l2-cache = <&L2_1>; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_CARMEL &CPU_COST_CARMEL>; status = "disabled"; }; cl1_1: cpu@3 { device_type = "cpu"; compatible = "nvidia,carmel", "arm,armv8"; reg = <0x0 0x101>; enable-method = "psci"; cpu-idle-states = <&C6 &C7>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; d-cache-size = <65536>; d-cache-line-size = <64>; d-cache-sets = <256>; l2-cache = <&L2_1>; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_CARMEL &CPU_COST_CARMEL>; status = "disabled"; }; cl2_0: cpu@4 { device_type = "cpu"; compatible = "nvidia,carmel", "arm,armv8"; reg = <0x0 0x200>; enable-method = "psci"; cpu-idle-states = <&C6 &C7>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; d-cache-size = <65536>; d-cache-line-size = <64>; d-cache-sets = <256>; l2-cache = <&L2_2>; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_CARMEL &CPU_COST_CARMEL>; status = "disabled"; }; cl2_1: cpu@5 { device_type = "cpu"; compatible = "nvidia,carmel", "arm,armv8"; reg = <0x0 0x201>; enable-method = "psci"; cpu-idle-states = <&C6 &C7>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; d-cache-size = <65536>; d-cache-line-size = <64>; d-cache-sets = <256>; l2-cache = <&L2_2>; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_CARMEL &CPU_COST_CARMEL>; status = "disabled"; }; cl3_0: cpu@6 { device_type = "cpu"; compatible = "nvidia,carmel", "arm,armv8"; reg = <0x0 0x10300>; enable-method = "psci"; cpu-idle-states = <&C6 &C7>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; d-cache-size = <65536>; d-cache-line-size = <64>; d-cache-sets = <256>; l2-cache = <&L2_3>; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_CARMEL &CPU_COST_CARMEL>; status = "disabled"; }; cl3_1: cpu@7 { device_type = "cpu"; compatible = "nvidia,carmel", "arm,armv8"; reg = <0x0 0x10301>; enable-method = "psci"; cpu-idle-states = <&C6 &C7>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; d-cache-size = <65536>; d-cache-line-size = <64>; d-cache-sets = <256>; l2-cache = <&L2_3>; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_CARMEL &CPU_COST_CARMEL>; status = "disabled"; }; }; L2_0: l2-cache0 { cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; next-level-cache = <&L3>; }; L2_1: l2-cache1 { cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; next-level-cache = <&L3>; status = "disabled"; }; L2_2: l2-cache2 { cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; next-level-cache = <&L3>; status = "disabled"; }; L2_3: l2-cache3 { cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; next-level-cache = <&L3>; status = "disabled"; }; L3: l3-cache { cache-size = <4194304>; cache-line-size = <64>; cache-sets = <4096>; }; CPU_COST_CARMEL: core-cost1 { busy-cost-data = <1024 1024>; idle-cost-data = <128>; }; arm-pmu { compatible = "arm,armv8-pmuv3"; interrupts = <0 384 0x4>, <0 385 0x4>, <0 386 0x4>, <0 387 0x4>, <0 388 0x4>, <0 389 0x4>, <0 390 0x4>, <0 391 0x4>; interrupt-affinity = <&cl0_0>, <&cl0_1>, <&cl1_0>, <&cl1_1>, <&cl2_0>, <&cl2_1>, <&cl3_0>, <&cl3_1>; status = "disabled"; }; carmel-pmu { compatible = "nvidia,carmel-pmu"; interrupts = <0 365 0x4>; interrupt-affinity = <&{/cpus/cpu@0}>; status = "okay"; }; }; # 19 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-cvm.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/mods-simple-bus.dtsi" 1 # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/mods-simple-bus.dtsi" / { mods-simple-bus { compatible = "simple-bus"; device_type = "mods-simple-bus"; #address-cells = <1>; #size-cells = <0>; mods-clocks { compatible = "nvidia,mods-clocks"; status = "disabled"; clocks = <&bpmp_clks 1U>, <&bpmp_clks 2U>, <&bpmp_clks 3U>, <&bpmp_clks 4U>, <&bpmp_clks 5U>, <&bpmp_clks 6U>, <&bpmp_clks 7U>, <&bpmp_clks 8U>, <&bpmp_clks 9U>, <&bpmp_clks 10U>, <&bpmp_clks 11U>, <&bpmp_clks 12U>, <&bpmp_clks 13U>, <&bpmp_clks 14U>, <&bpmp_clks 15U>, <&bpmp_clks 16U>, <&bpmp_clks 17U>, <&bpmp_clks 18U>, <&bpmp_clks 19U>, <&bpmp_clks 20U>, <&bpmp_clks 21U>, <&bpmp_clks 22U>, <&bpmp_clks 23U>, <&bpmp_clks 24U>, <&bpmp_clks 25U>, <&bpmp_clks 26U>, <&bpmp_clks 27U>, <&bpmp_clks 28U>, <&bpmp_clks 29U>, <&bpmp_clks 30U>, <&bpmp_clks 31U>, <&bpmp_clks 32U>, <&bpmp_clks 33U>, <&bpmp_clks 34U>, <&bpmp_clks 35U>, <&bpmp_clks 36U>, <&bpmp_clks 37U>, <&bpmp_clks 38U>, <&bpmp_clks 39U>, <&bpmp_clks 40U>, <&bpmp_clks 41U>, <&bpmp_clks 42U>, <&bpmp_clks 43U>, <&bpmp_clks 44U>, <&bpmp_clks 45U>, <&bpmp_clks 46U>, <&bpmp_clks 47U>, <&bpmp_clks 48U>, <&bpmp_clks 49U>, <&bpmp_clks 50U>, <&bpmp_clks 51U>, <&bpmp_clks 52U>, <&bpmp_clks 53U>, <&bpmp_clks 54U>, <&bpmp_clks 55U>, <&bpmp_clks 56U>, <&bpmp_clks 57U>, <&bpmp_clks 58U>, <&bpmp_clks 59U>, <&bpmp_clks 60U>, <&bpmp_clks 61U>, <&bpmp_clks 62U>, <&bpmp_clks 63U>, <&bpmp_clks 64U>, <&bpmp_clks 65U>, <&bpmp_clks 66U>, <&bpmp_clks 67U>, <&bpmp_clks 68U>, <&bpmp_clks 69U>, <&bpmp_clks 70U>, <&bpmp_clks 71U>, <&bpmp_clks 72U>, <&bpmp_clks 73U>, <&bpmp_clks 74U>, <&bpmp_clks 75U>, <&bpmp_clks 76U>, <&bpmp_clks 77U>, <&bpmp_clks 78U>, <&bpmp_clks 79U>, <&bpmp_clks 80U>, <&bpmp_clks 81U>, <&bpmp_clks 82U>, <&bpmp_clks 83U>, <&bpmp_clks 84U>, <&bpmp_clks 85U>, <&bpmp_clks 86U>, <&bpmp_clks 87U>, <&bpmp_clks 88U>, <&bpmp_clks 89U>, <&bpmp_clks 90U>, <&bpmp_clks 91U>, <&bpmp_clks 92U>, <&bpmp_clks 93U>, <&bpmp_clks 94U>, <&bpmp_clks 95U>, <&bpmp_clks 96U>, <&bpmp_clks 97U>, <&bpmp_clks 98U>, <&bpmp_clks 99U>, <&bpmp_clks 100U>, <&bpmp_clks 101U>, <&bpmp_clks 102U>, <&bpmp_clks 103U>, <&bpmp_clks 104U>, <&bpmp_clks 105U>, <&bpmp_clks 106U>, <&bpmp_clks 107U>, <&bpmp_clks 108U>, <&bpmp_clks 109U>, <&bpmp_clks 110U>, <&bpmp_clks 111U>, <&bpmp_clks 112U>, <&bpmp_clks 113U>, <&bpmp_clks 114U>, <&bpmp_clks 115U>, <&bpmp_clks 116U>, <&bpmp_clks 117U>, <&bpmp_clks 118U>, <&bpmp_clks 119U>, <&bpmp_clks 120U>, <&bpmp_clks 121U>, <&bpmp_clks 122U>, <&bpmp_clks 123U>, <&bpmp_clks 124U>, <&bpmp_clks 125U>, <&bpmp_clks 126U>, <&bpmp_clks 127U>, <&bpmp_clks 128U>, <&bpmp_clks 129U>, <&bpmp_clks 130U>, <&bpmp_clks 131U>, <&bpmp_clks 132U>, <&bpmp_clks 133U>, <&bpmp_clks 134U>, <&bpmp_clks 135U>, <&bpmp_clks 136U>, <&bpmp_clks 137U>, <&bpmp_clks 138U>, <&bpmp_clks 139U>, <&bpmp_clks 140U>, <&bpmp_clks 141U>, <&bpmp_clks 142U>, <&bpmp_clks 143U>, <&bpmp_clks 144U>, <&bpmp_clks 145U>, <&bpmp_clks 146U>, <&bpmp_clks 147U>, <&bpmp_clks 148U>, <&bpmp_clks 149U>, <&bpmp_clks 150U>, <&bpmp_clks 151U>, <&bpmp_clks 152U>, <&bpmp_clks 153U>, <&bpmp_clks 154U>, <&bpmp_clks 155U>, <&bpmp_clks 156U>, <&bpmp_clks 157U>, <&bpmp_clks 158U>, <&bpmp_clks 159U>, <&bpmp_clks 160U>, <&bpmp_clks 161U>, <&bpmp_clks 162U>, <&bpmp_clks 163U>, <&bpmp_clks 164U>, <&bpmp_clks 165U>, <&bpmp_clks 166U>, <&bpmp_clks 167U>, <&bpmp_clks 168U>, <&bpmp_clks 169U>, <&bpmp_clks 170U>, <&bpmp_clks 171U>, <&bpmp_clks 172U>, <&bpmp_clks 173U>, <&bpmp_clks 174U>, <&bpmp_clks 175U>, <&bpmp_clks 176U>, <&bpmp_clks 177U>, <&bpmp_clks 178U>, <&bpmp_clks 179U>, <&bpmp_clks 180U>, <&bpmp_clks 181U>, <&bpmp_clks 182U>, <&bpmp_clks 183U>, <&bpmp_clks 184U>, <&bpmp_clks 185U>, <&bpmp_clks 186U>, <&bpmp_clks 187U>, <&bpmp_clks 188U>, <&bpmp_clks 189U>, <&bpmp_clks 190U>, <&bpmp_clks 191U>, <&bpmp_clks 192U>, <&bpmp_clks 193U>, <&bpmp_clks 194U>, <&bpmp_clks 195U>, <&bpmp_clks 196U>, <&bpmp_clks 197U>, <&bpmp_clks 198U>, <&bpmp_clks 199U>, <&bpmp_clks 200U>, <&bpmp_clks 201U>, <&bpmp_clks 202U>, <&bpmp_clks 203U>, <&bpmp_clks 204U>, <&bpmp_clks 205U>, <&bpmp_clks 206U>, <&bpmp_clks 207U>, <&bpmp_clks 208U>, <&bpmp_clks 209U>, <&bpmp_clks 210U>, <&bpmp_clks 211U>, <&bpmp_clks 212U>, <&bpmp_clks 213U>, <&bpmp_clks 214U>, <&bpmp_clks 215U>, <&bpmp_clks 216U>, <&bpmp_clks 217U>, <&bpmp_clks 218U>, <&bpmp_clks 219U>, <&bpmp_clks 220U>, <&bpmp_clks 221U>, <&bpmp_clks 222U>, <&bpmp_clks 223U>, <&bpmp_clks 224U>, <&bpmp_clks 225U>, <&bpmp_clks 226U>, <&bpmp_clks 227U>, <&bpmp_clks 228U>, <&bpmp_clks 229U>, <&bpmp_clks 230U>, <&bpmp_clks 231U>, <&bpmp_clks 232U>, <&bpmp_clks 233U>, <&bpmp_clks 234U>, <&bpmp_clks 235U>, <&bpmp_clks 236U>, <&bpmp_clks 237U>, <&bpmp_clks 238U>, <&bpmp_clks 239U>, <&bpmp_clks 240U>, <&bpmp_clks 241U>, <&bpmp_clks 242U>, <&bpmp_clks 243U>, <&bpmp_clks 244U>, <&bpmp_clks 245U>, <&bpmp_clks 246U>, <&bpmp_clks 247U>, <&bpmp_clks 248U>, <&bpmp_clks 249U>, <&bpmp_clks 250U>, <&bpmp_clks 251U>, <&bpmp_clks 252U>, <&bpmp_clks 253U>, <&bpmp_clks 254U>, <&bpmp_clks 255U>, <&bpmp_clks 256U>, <&bpmp_clks 257U>, <&bpmp_clks 258U>, <&bpmp_clks 259U>, <&bpmp_clks 260U>, <&bpmp_clks 261U>, <&bpmp_clks 262U>, <&bpmp_clks 263U>, <&bpmp_clks 264U>, <&bpmp_clks 265U>, <&bpmp_clks 266U>, <&bpmp_clks 267U>, <&bpmp_clks 268U>, <&bpmp_clks 269U>, <&bpmp_clks 270U>, <&bpmp_clks 271U>, <&bpmp_clks 272U>, <&bpmp_clks 273U>, <&bpmp_clks 274U>, <&bpmp_clks 275U>, <&bpmp_clks 276U>, <&bpmp_clks 277U>, <&bpmp_clks 278U>, <&bpmp_clks 279U>, <&bpmp_clks 280U>, <&bpmp_clks 281U>, <&bpmp_clks 282U>, <&bpmp_clks 283U>, <&bpmp_clks 284U>, <&bpmp_clks 285U>, <&bpmp_clks 286U>, <&bpmp_clks 287U>, <&bpmp_clks 288U>, <&bpmp_clks 289U>, <&bpmp_clks 290U>, <&bpmp_clks 291U>, <&bpmp_clks 292U>, <&bpmp_clks 293U>, <&bpmp_clks 294U>, <&bpmp_clks 295U>, <&bpmp_clks 296U>, <&bpmp_clks 297U>, <&bpmp_clks 298U>, <&bpmp_clks 299U>, <&bpmp_clks 300U>, <&bpmp_clks 301U>, <&bpmp_clks 302U>, <&bpmp_clks 304U>, <&bpmp_clks 305U>, <&bpmp_clks 306U>, <&bpmp_clks 307U>, <&bpmp_clks 308U>, <&bpmp_clks 309U>, <&bpmp_clks 310U>, <&bpmp_clks 311U>, <&bpmp_clks 312U>, <&bpmp_clks 313U>, <&bpmp_clks 314U>, <&bpmp_clks 315U>, <&bpmp_clks 316U>, <&bpmp_clks 326U>; clock-names = "actmon", "adsp", "adspneon", "ahub", "apb2ape", "ape", "aud_mclk", "axi_cbb", "can1", "can1_host", "can2", "can2_host", "cec", "clk_m", "dmic1", "dmic2", "dmic3", "dmic4", "dpaux", "dpaux1", "aclk", "mss_encrypt", "eqos_rx_input", "icq2", "aon_apb", "aon_nic", "aon_cpu_nic", "plla1", "dspk1", "dspk2", "emc", "eqos_axi", "eqos_ptp_ref", "eqos_rx", "eqos_tx", "extperiph1", "extperiph2", "extperiph3", "extperiph4", "fuse", "gpcclk", "gpu_pwr", "hda", "hda2codec_2x", "hda2hdmicodec", "host1x", "hsic_trk", "i2c1", "i2c2", "i2c3", "i2c4", "i2c6", "i2c7", "i2c8", "i2c9", "i2s1", "i2s1_sync_input", "i2s2", "i2s2_sync_input", "i2s3", "i2s3_sync_input", "i2s4", "i2s4_sync_input", "i2s5", "i2s5_sync_input", "i2s6", "i2s6_sync_input", "iqc1", "isp", "kfuse", "maud", "mipi_cal", "mphy_core_pll_fixed", "mphy_l0_rx_ana", "mphy_l0_rx_ls_bit", "mphy_l0_rx_symb", "mphy_l0_tx_ls_3xbit", "mphy_l0_tx_symb", "mphy_l1_rx_ana", "mphy_tx_1mhz_ref", "nvcsi", "nvcsilp", "nvdec", "nvdisplayhub", "nvdisplay_disp", "nvdisplay_p0", "nvdisplay_p1", "nvdisplay_p2", "nvenc", "nvjpg", "osc", "aon_touch", "plla", "pllaon", "plld", "plld2", "plld3", "plldp", "plld4", "plle", "pllp", "pllp_out0", "utmipll", "plla_out0", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7", "pwm8", "rce_cpu_nic", "rce_nic", "sata", "sata_oob", "aon_i2c_slow", "sce_cpu_nic", "sce_nic", "sdmmc1", "uphy_pll3", "sdmmc3", "sdmmc4", "se", "sor0_out", "sor0_ref", "sor0_pad_clkout", "sor1_out", "sor1_ref", "sor1_pad_clkout", "sor_safe", "iqc1_in", "iqc2_in", "dmic5", "spi1", "spi2", "spi3", "i2c_slow", "sync_dmic1", "sync_dmic2", "sync_dmic3", "sync_dmic4", "sync_dspk1", "sync_dspk2", "sync_i2s1", "sync_i2s2", "sync_i2s3", "sync_i2s4", "sync_i2s5", "sync_i2s6", "mphy_force_ls_mode", "tach", "tsec", "tsecb", "uarta", "uartb", "uartc", "uartd", "uarte", "uartf", "uartg", "uart_fst_mipi_cal", "ufsdev_ref", "ufshc", "usb2_trk", "vi", "vic", "pva0_axi", "pva0_vps0", "pva0_vps1", "pva1_axi", "pva1_vps0", "pva1_vps1", "dla0_falcon", "dla0_core", "dla1_falcon", "dla1_core", "sor2_out", "sor2_ref", "sor2_pad_clkout", "sor3_out", "sor3_ref", "sor3_pad_clkout", "nvdisplay_p3", "dpaux2", "dpaux3", "nvdec1", "nvenc1", "se_free", "uarth", "fuse_serial", "qspi0", "qspi1", "qspi0_pm", "qspi1_pm", "vi_const", "nafll_bpmp", "nafll_sce", "nafll_nvdec", "nafll_nvjpg", "nafll_tsec", "nafll_tsecb", "nafll_vi", "nafll_se", "nafll_nvenc", "nafll_isp", "nafll_vic", "nafll_nvdisplayhub", "nafll_axicbb", "nafll_dla", "nafll_pva_core", "nafll_pva_vps", "nafll_cvnas", "nafll_rce", "nafll_nvenc1", "nafll_dla_falcon", "nafll_nvdec1", "nafll_gpu", "sdmmc_legacy_tm", "pex0_core_0", "pex0_core_1", "pex0_core_2", "pex0_core_3", "pex0_core_4", "pex1_core_5", "pex_ref1", "pex_ref2", "nvhs_ref", "csi_a", "csi_b", "csi_c", "csi_d", "csi_e", "csi_f", "csi_g", "csi_h", "pllc4", "pllc4_out", "pllc4_out1", "pllc4_out2", "pllc4_muxed", "pllc4_vco_div2", "pllnvhs", "csi_a_pad", "csi_b_pad", "csi_c_pad", "csi_d_pad", "csi_e_pad", "csi_f_pad", "csi_g_pad", "csi_h_pad", "slvsec", "slvsec_padctrl", "pex_sata_usb_rx_byp", "pex_usb_pad_pll0_mgmt", "pex_usb_pad_pll1_mgmt", "pex_usb_pad_pll2_mgmt", "pex_usb_pad_pll3_mgmt", "nvlink_sys", "nvlink_rx", "nvlink_tx", "nvlink_tx_div", "nvhs_rx_byp_ref", "nvhs_pll0_mgmt", "xusb_core_dev", "xusb_core_mux", "xusb_core_host", "xusb_core_ss", "xusb_falcon", "xusb_falcon_host", "xusb_falcon_ss", "xusb_fs", "xusb_fs_host", "xusb_fs_dev", "xusb_ss", "xusb_ss_dev", "xusb_ss_superspeed", "plldisphub", "plldisphub_div", "nafll_cluster0", "nafll_cluster1", "nafll_cluster2", "nafll_cluster3", "can1_core", "can2_core", "plla1_out1", "pllnvhs_hps", "pllrefe_vcoout", "clk_32k", "spdifin_sync_input", "utmipll_clkout48", "utmipll_clkout480", "cvnas", "pllnvcsi", "pva0_cpu_axi", "pva1_cpu_axi", "pva0_vps", "pva1_vps", "dla0_falcon_mux", "dla1_falcon_mux", "dla0_core_mux", "dla1_core_mux", "utmipll_hps", "i2c5", "i2c10", "bpmp_cpu_nic", "bpmp_apb", "tsc", "emcsa", "emcsb", "emcsc", "emcsd", "pll_c", "pll_c2", "pll_c3", "plle_hps"; resets = <&bpmp_resets 1U>, <&bpmp_resets 2U>, <&bpmp_resets 3U>, <&bpmp_resets 4U>, <&bpmp_resets 5U>, <&bpmp_resets 6U>, <&bpmp_resets 7U>, <&bpmp_resets 8U>, <&bpmp_resets 9U>, <&bpmp_resets 10U>, <&bpmp_resets 11U>, <&bpmp_resets 17U>, <&bpmp_resets 18U>, <&bpmp_resets 19U>, <&bpmp_resets 20U>, <&bpmp_resets 21U>, <&bpmp_resets 22U>, <&bpmp_resets 23U>, <&bpmp_resets 24U>, <&bpmp_resets 25U>, <&bpmp_resets 29U>, <&bpmp_resets 30U>, <&bpmp_resets 31U>, <&bpmp_resets 32U>, <&bpmp_resets 33U>, <&bpmp_resets 34U>, <&bpmp_resets 35U>, <&bpmp_resets 36U>, <&bpmp_resets 37U>, <&bpmp_resets 38U>, <&bpmp_resets 39U>, <&bpmp_resets 40U>, <&bpmp_resets 41U>, <&bpmp_resets 42U>, <&bpmp_resets 43U>, <&bpmp_resets 44U>, <&bpmp_resets 45U>, <&bpmp_resets 46U>, <&bpmp_resets 47U>, <&bpmp_resets 48U>, <&bpmp_resets 49U>, <&bpmp_resets 50U>, <&bpmp_resets 51U>, <&bpmp_resets 52U>, <&bpmp_resets 53U>, <&bpmp_resets 54U>, <&bpmp_resets 55U>, <&bpmp_resets 59U>, <&bpmp_resets 60U>, <&bpmp_resets 61U>, <&bpmp_resets 62U>, <&bpmp_resets 63U>, <&bpmp_resets 66U>, <&bpmp_resets 67U>, <&bpmp_resets 68U>, <&bpmp_resets 69U>, <&bpmp_resets 70U>, <&bpmp_resets 71U>, <&bpmp_resets 72U>, <&bpmp_resets 73U>, <&bpmp_resets 74U>, <&bpmp_resets 75U>, <&bpmp_resets 76U>, <&bpmp_resets 77U>, <&bpmp_resets 78U>, <&bpmp_resets 79U>, <&bpmp_resets 80U>, <&bpmp_resets 81U>, <&bpmp_resets 82U>, <&bpmp_resets 84U>, <&bpmp_resets 85U>, <&bpmp_resets 86U>, <&bpmp_resets 87U>, <&bpmp_resets 88U>, <&bpmp_resets 89U>, <&bpmp_resets 90U>, <&bpmp_resets 91U>, <&bpmp_resets 92U>, <&bpmp_resets 93U>, <&bpmp_resets 94U>, <&bpmp_resets 95U>, <&bpmp_resets 97U>, <&bpmp_resets 98U>, <&bpmp_resets 99U>, <&bpmp_resets 100U>, <&bpmp_resets 101U>, <&bpmp_resets 102U>, <&bpmp_resets 103U>, <&bpmp_resets 104U>, <&bpmp_resets 105U>, <&bpmp_resets 106U>, <&bpmp_resets 107U>, <&bpmp_resets 108U>, <&bpmp_resets 109U>, <&bpmp_resets 110U>, <&bpmp_resets 112U>, <&bpmp_resets 113U>, <&bpmp_resets 114U>, <&bpmp_resets 115U>, <&bpmp_resets 116U>, <&bpmp_resets 117U>, <&bpmp_resets 118U>, <&bpmp_resets 119U>, <&bpmp_resets 120U>, <&bpmp_resets 121U>, <&bpmp_resets 122U>, <&bpmp_resets 123U>, <&bpmp_resets 124U>, <&bpmp_resets 125U>, <&bpmp_resets 126U>, <&bpmp_resets 127U>, <&bpmp_resets 128U>, <&bpmp_resets 129U>, <&bpmp_resets 130U>, <&bpmp_resets 131U>, <&bpmp_resets 132U>, <&bpmp_resets 133U>, <&bpmp_resets 134U>, <&bpmp_resets 135U>, <&bpmp_resets 136U>, <&bpmp_resets 137U>, <&bpmp_resets 138U>, <&bpmp_resets 139U>, <&bpmp_resets 140U>, <&bpmp_resets 141U>, <&bpmp_resets 142U>, <&bpmp_resets 143U>, <&bpmp_resets 144U>, <&bpmp_resets 145U>, <&bpmp_resets 146U>, <&bpmp_resets 147U>, <&bpmp_resets 148U>, <&bpmp_resets 149U>, <&bpmp_resets 150U>, <&bpmp_resets 151U>, <&bpmp_resets 152U>, <&bpmp_resets 153U>, <&bpmp_resets 154U>, <&bpmp_resets 155U>, <&bpmp_resets 156U>, <&bpmp_resets 157U>, <&bpmp_resets 158U>, <&bpmp_resets 159U>, <&bpmp_resets 160U>, <&bpmp_resets 161U>, <&bpmp_resets 162U>; reset-names = "actmon", "adsp_all", "afi", "can1", "can2", "dla0", "dla1", "dpaux", "dpaux1", "dpaux2", "dpaux3", "eqos", "gpcdma", "gpu", "hda", "hda2codec_2x", "hda2hdmicodec", "host1x", "i2c1", "i2c10", "i2c2", "i2c3", "i2c4", "i2c6", "i2c7", "i2c8", "i2c9", "isp", "mipi_cal", "mphy_clk_ctl", "mphy_l0_rx", "mphy_l0_tx", "mphy_l1_rx", "mphy_l1_tx", "nvcsi", "nvdec", "nvdisplay0_head0", "nvdisplay0_head1", "nvdisplay0_head2", "nvdisplay0_head3", "nvdisplay0_misc", "nvdisplay0_wgrp0", "nvdisplay0_wgrp1", "nvdisplay0_wgrp2", "nvdisplay0_wgrp3", "nvdisplay0_wgrp4", "nvdisplay0_wgrp5", "nvenc", "nvenc1", "nvjpg", "pcie", "pciexclk", "pva0_all", "pva1_all", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7", "pwm8", "qspi0", "qspi1", "sata", "satacold", "sce_all", "rce_all", "sdmmc1", "sdmmc3", "sdmmc4", "se", "sor0", "sor1", "sor2", "sor3", "spi1", "spi2", "spi3", "spi4", "tach", "tsctnvi", "tsec", "tsecb", "uarta", "uartb", "uartc", "uartd", "uarte", "uartf", "uartg", "uarth", "ufshc", "ufshc_axi_m", "ufshc_lp_seq", "vi", "vic", "xusb_padctl", "nvdec1", "pex0_core_0", "pex0_core_1", "pex0_core_2", "pex0_core_3", "pex0_core_4", "pex0_core_0_apb", "pex0_core_1_apb", "pex0_core_2_apb", "pex0_core_3_apb", "pex0_core_4_apb", "pex0_common_apb", "slvsec", "nvlink", "pex1_core_5", "pex1_core_5_apb", "cvnas", "cvnas_fcm", "nvhs_uphy", "nvhs_uphy_pll0", "nvhs_uphy_l0", "nvhs_uphy_l1", "nvhs_uphy_l2", "nvhs_uphy_l3", "nvhs_uphy_l4", "nvhs_uphy_l5", "nvhs_uphy_l6", "nvhs_uphy_l7", "nvhs_uphy_pm", "dmic5", "ape", "pex_usb_uphy", "pex_usb_uphy_l0", "pex_usb_uphy_l1", "pex_usb_uphy_l2", "pex_usb_uphy_l3", "pex_usb_uphy_l4", "pex_usb_uphy_l5", "pex_usb_uphy_l6", "pex_usb_uphy_l7", "pex_usb_uphy_l8", "pex_usb_uphy_l9", "pex_usb_uphy_l10", "pex_usb_uphy_l11", "pex_usb_uphy_pll0", "pex_usb_uphy_pll1", "pex_usb_uphy_pll2", "pex_usb_uphy_pll3"; }; }; }; # 20 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-cvm.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-prod.dtsi" 1 # 28 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-prod.dtsi" / { host1x { prod-settings { #prod-cells = <4>; prod { prod = < 1 0x000022e4 0x0000ffff 0x00000808>; }; }; se@15810000 { prod-settings { #prod-cells = <4>; prod { prod = < 0 0x00000018 0x00020002 0x00000000>; }; }; }; se@15820000 { prod-settings { #prod-cells = <4>; prod { prod = < 0 0x00000018 0x00020002 0x00000000>; }; }; }; se@15830000 { prod-settings { #prod-cells = <4>; prod { prod = < 0 0x00000018 0x00020002 0x00000000>; }; }; }; se@15840000 { prod-settings { #prod-cells = <4>; prod { prod = < 0 0x00000018 0x00020002 0x00000000>; }; }; }; sor { prod-settings { #prod-cells = <4>; prod_list_hdmi_soc = "prod_c_hdmi_0m_54m","prod_c_hdmi_54m_111m","prod_c_hdmi_111m_223m","prod_c_hdmi_223m_300m","prod_c_hdmi_300m_600m"; prod_c_dp { prod = < 0 0x00000180 0x00000001 0x00000001 0 0x000005a4 0x0f0f0f00 0x05050300 0 0x000005a8 0x00000100 0x00000100 0 0x000005ac 0xf000ff00 0x00000000 0 0x000005b0 0x00000ff0 0x00000440 0 0x000005b4 0x00400000 0x00000000 0 0x000005e4 0x00003b80 0x00001a00>; }; prod_c_rbr { prod = < 0 0x000005a8 0x00f00000 0x00200000>; }; prod_c_hbr { prod = < 0 0x000005a8 0x00f00000 0x00200000>; }; prod_c_hbr2 { prod = < 0 0x000005a8 0x00f00000 0x00300000>; }; prod_c_hbr3 { prod = < 0 0x000005a8 0x00f00000 0x00300000>; }; prod_c_hdmi_0m_54m { prod = < 0 0x000005a4 0x0f0f0f00 0x05050000 0 0x000005a8 0x00f00100 0x00300100 0 0x000005b0 0xff000ff0 0x38000440 0 0x000005e4 0x00003f80 0x00002a00 0 0x00000138 0xffffffff 0x333a3a3a 0 0x00000148 0xffffffff 0x00000000 0 0x000005b8 0x0040ff00 0x00400000>; }; prod_c_hdmi_54m_111m { prod = < 0 0x000005a4 0x0f0f0f00 0x05050100 0 0x000005a8 0x00f00100 0x00300100 0 0x000005b0 0xff000ff0 0x38000440 0 0x000005e4 0x00003f80 0x00002200 0 0x00000138 0xffffffff 0x333a3a3a 0 0x00000148 0xffffffff 0x00000000 0 0x000005b8 0x0040ff00 0x00400000>; }; prod_c_hdmi_111m_223m { prod = < 0 0x000005a4 0x0f0f0f00 0x05050300 0 0x000005a8 0x00f00100 0x00300100 0 0x000005b0 0xff000ff0 0x38000440 0 0x000005e4 0x00003f80 0x00001a00 0 0x00000138 0xffffffff 0x373a3a3a 0 0x00000148 0xffffffff 0x00000000 0 0x000005b8 0x0040ff00 0x00400000>; }; prod_c_hdmi_223m_300m { prod = < 0 0x000005a4 0x0f0f0f00 0x05050300 0 0x000005a8 0x00f00100 0x00300100 0 0x000005b0 0xff000ff0 0x38000440 0 0x000005e4 0x00003f80 0x00001a00 0 0x00000138 0xffffffff 0x333d3d3d 0 0x00000148 0xffffffff 0x00000000 0 0x000005b8 0x0040ff00 0x00404000>; }; prod_c_hdmi_300m_600m { prod = < 0 0x000005a4 0x0f0f0f00 0x05050300 0 0x000005a8 0x00f00100 0x00300100 0 0x000005b0 0xff000ff0 0x38000440 0 0x000005e4 0x00003f80 0x00001a00 0 0x00000138 0xffffffff 0x333d3d3d 0 0x00000148 0xffffffff 0x00000000 0 0x000005b8 0x0040ff00 0x00406000>; }; }; }; sor1 { prod-settings { #prod-cells = <4>; prod_list_hdmi_soc = "prod_c_hdmi_0m_54m","prod_c_hdmi_54m_111m","prod_c_hdmi_111m_223m","prod_c_hdmi_223m_300m","prod_c_hdmi_300m_600m"; prod_c_dp { prod = < 0 0x00000180 0x00000001 0x00000001 0 0x000005a4 0x0f0f0f00 0x05050300 0 0x000005a8 0x00000100 0x00000100 0 0x000005ac 0xf000ff00 0x00000000 0 0x000005b0 0x00000ff0 0x00000440 0 0x000005b4 0x00400000 0x00000000 0 0x000005e4 0x00003b80 0x00001a00>; }; prod_c_rbr { prod = < 0 0x000005a8 0x00f00000 0x00200000>; }; prod_c_hbr { prod = < 0 0x000005a8 0x00f00000 0x00200000>; }; prod_c_hbr2 { prod = < 0 0x000005a8 0x00f00000 0x00300000>; }; prod_c_hbr3 { prod = < 0 0x000005a8 0x00f00000 0x00300000>; }; prod_c_hdmi_0m_54m { prod = < 0 0x000005a4 0x0f0f0f00 0x05050000 0 0x000005a8 0x00f00100 0x00300100 0 0x000005b0 0xff000ff0 0x38000440 0 0x000005e4 0x00003f80 0x00002a00 0 0x00000138 0xffffffff 0x333a3a3a 0 0x00000148 0xffffffff 0x00000000 0 0x000005b8 0x0040ff00 0x00400000>; }; prod_c_hdmi_54m_111m { prod = < 0 0x000005a4 0x0f0f0f00 0x05050100 0 0x000005a8 0x00f00100 0x00300100 0 0x000005b0 0xff000ff0 0x38000440 0 0x000005e4 0x00003f80 0x00002200 0 0x00000138 0xffffffff 0x333a3a3a 0 0x00000148 0xffffffff 0x00000000 0 0x000005b8 0x0040ff00 0x00400000>; }; prod_c_hdmi_111m_223m { prod = < 0 0x000005a4 0x0f0f0f00 0x05050300 0 0x000005a8 0x00f00100 0x00300100 0 0x000005b0 0xff000ff0 0x38000440 0 0x000005e4 0x00003f80 0x00001a00 0 0x00000138 0xffffffff 0x373a3a3a 0 0x00000148 0xffffffff 0x00000000 0 0x000005b8 0x0040ff00 0x00400000>; }; prod_c_hdmi_223m_300m { prod = < 0 0x000005a4 0x0f0f0f00 0x05050300 0 0x000005a8 0x00f00100 0x00300100 0 0x000005b0 0xff000ff0 0x38000440 0 0x000005e4 0x00003f80 0x00001a00 0 0x00000138 0xffffffff 0x333d3d3d 0 0x00000148 0xffffffff 0x00000000 0 0x000005b8 0x0040ff00 0x00404000>; }; prod_c_hdmi_300m_600m { prod = < 0 0x000005a4 0x0f0f0f00 0x05050300 0 0x000005a8 0x00f00100 0x00300100 0 0x000005b0 0xff000ff0 0x38000440 0 0x000005e4 0x00003f80 0x00001a00 0 0x00000138 0xffffffff 0x333d3d3d 0 0x00000148 0xffffffff 0x00000000 0 0x000005b8 0x0040ff00 0x00406000>; }; }; }; sor2 { prod-settings { #prod-cells = <4>; prod_list_hdmi_soc = "prod_c_hdmi_0m_54m","prod_c_hdmi_54m_111m","prod_c_hdmi_111m_223m","prod_c_hdmi_223m_300m","prod_c_hdmi_300m_600m"; prod_c_dp { prod = < 0 0x00000180 0x00000001 0x00000001 0 0x000005a4 0x0f0f0f00 0x05050300 0 0x000005a8 0x00000100 0x00000100 0 0x000005ac 0xf000ff00 0x00000000 0 0x000005b0 0x00000ff0 0x00000440 0 0x000005b4 0x00400000 0x00000000 0 0x000005e4 0x00003b80 0x00001a00>; }; prod_c_rbr { prod = < 0 0x000005a8 0x00f00000 0x00200000>; }; prod_c_hbr { prod = < 0 0x000005a8 0x00f00000 0x00200000>; }; prod_c_hbr2 { prod = < 0 0x000005a8 0x00f00000 0x00300000>; }; prod_c_hbr3 { prod = < 0 0x000005a8 0x00f00000 0x00300000>; }; prod_c_hdmi_0m_54m { prod = < 0 0x000005a4 0x0f0f0f00 0x05050000 0 0x000005a8 0x00f00100 0x00300100 0 0x000005b0 0xff000ff0 0x38000440 0 0x000005e4 0x00003f80 0x00002a00 0 0x00000138 0xffffffff 0x333a3a3a 0 0x00000148 0xffffffff 0x00000000 0 0x000005b8 0x0040ff00 0x00400000>; }; prod_c_hdmi_54m_111m { prod = < 0 0x000005a4 0x0f0f0f00 0x05050100 0 0x000005a8 0x00f00100 0x00300100 0 0x000005b0 0xff000ff0 0x38000440 0 0x000005e4 0x00003f80 0x00002200 0 0x00000138 0xffffffff 0x333a3a3a 0 0x00000148 0xffffffff 0x00000000 0 0x000005b8 0x0040ff00 0x00400000>; }; prod_c_hdmi_111m_223m { prod = < 0 0x000005a4 0x0f0f0f00 0x05050300 0 0x000005a8 0x00f00100 0x00300100 0 0x000005b0 0xff000ff0 0x38000440 0 0x000005e4 0x00003f80 0x00001a00 0 0x00000138 0xffffffff 0x373a3a3a 0 0x00000148 0xffffffff 0x00000000 0 0x000005b8 0x0040ff00 0x00400000>; }; prod_c_hdmi_223m_300m { prod = < 0 0x000005a4 0x0f0f0f00 0x05050300 0 0x000005a8 0x00f00100 0x00300100 0 0x000005b0 0xff000ff0 0x38000440 0 0x000005e4 0x00003f80 0x00001a00 0 0x00000138 0xffffffff 0x333d3d3d 0 0x00000148 0xffffffff 0x00000000 0 0x000005b8 0x0040ff00 0x00404000>; }; prod_c_hdmi_300m_600m { prod = < 0 0x000005a4 0x0f0f0f00 0x05050300 0 0x000005a8 0x00f00100 0x00300100 0 0x000005b0 0xff000ff0 0x38000440 0 0x000005e4 0x00003f80 0x00001a00 0 0x00000138 0xffffffff 0x333d3d3d 0 0x00000148 0xffffffff 0x00000000 0 0x000005b8 0x0040ff00 0x00406000>; }; }; }; sor3 { prod-settings { #prod-cells = <4>; prod_list_hdmi_soc = "prod_c_hdmi_0m_54m","prod_c_hdmi_54m_111m","prod_c_hdmi_111m_223m","prod_c_hdmi_223m_300m","prod_c_hdmi_300m_600m"; prod_c_dp { prod = < 0 0x00000180 0x00000001 0x00000001 0 0x000005a4 0x0f0f0f00 0x05050300 0 0x000005a8 0x00000100 0x00000100 0 0x000005ac 0xf000ff00 0x00000000 0 0x000005b0 0x00000ff0 0x00000440 0 0x000005b4 0x00400000 0x00000000 0 0x000005e4 0x00003b80 0x00001a00>; }; prod_c_rbr { prod = < 0 0x000005a8 0x00f00000 0x00200000>; }; prod_c_hbr { prod = < 0 0x000005a8 0x00f00000 0x00200000>; }; prod_c_hbr2 { prod = < 0 0x000005a8 0x00f00000 0x00300000>; }; prod_c_hbr3 { prod = < 0 0x000005a8 0x00f00000 0x00300000>; }; prod_c_hdmi_0m_54m { prod = < 0 0x000005a4 0x0f0f0f00 0x05050000 0 0x000005a8 0x00f00100 0x00300100 0 0x000005b0 0xff000ff0 0x38000440 0 0x000005e4 0x00003f80 0x00002a00 0 0x00000138 0xffffffff 0x333a3a3a 0 0x00000148 0xffffffff 0x00000000 0 0x000005b8 0x0040ff00 0x00400000>; }; prod_c_hdmi_54m_111m { prod = < 0 0x000005a4 0x0f0f0f00 0x05050100 0 0x000005a8 0x00f00100 0x00300100 0 0x000005b0 0xff000ff0 0x38000440 0 0x000005e4 0x00003f80 0x00002200 0 0x00000138 0xffffffff 0x333a3a3a 0 0x00000148 0xffffffff 0x00000000 0 0x000005b8 0x0040ff00 0x00400000>; }; prod_c_hdmi_111m_223m { prod = < 0 0x000005a4 0x0f0f0f00 0x05050300 0 0x000005a8 0x00f00100 0x00300100 0 0x000005b0 0xff000ff0 0x38000440 0 0x000005e4 0x00003f80 0x00001a00 0 0x00000138 0xffffffff 0x373a3a3a 0 0x00000148 0xffffffff 0x00000000 0 0x000005b8 0x0040ff00 0x00400000>; }; prod_c_hdmi_223m_300m { prod = < 0 0x000005a4 0x0f0f0f00 0x05050300 0 0x000005a8 0x00f00100 0x00300100 0 0x000005b0 0xff000ff0 0x38000440 0 0x000005e4 0x00003f80 0x00001a00 0 0x00000138 0xffffffff 0x333d3d3d 0 0x00000148 0xffffffff 0x00000000 0 0x000005b8 0x0040ff00 0x00404000>; }; prod_c_hdmi_300m_600m { prod = < 0 0x000005a4 0x0f0f0f00 0x05050300 0 0x000005a8 0x00f00100 0x00300100 0 0x000005b0 0xff000ff0 0x38000440 0 0x000005e4 0x00003f80 0x00001a00 0 0x00000138 0xffffffff 0x333d3d3d 0 0x00000148 0xffffffff 0x00000000 0 0x000005b8 0x0040ff00 0x00406000>; }; }; }; dpaux@155c0000 { prod-settings { #prod-cells = <4>; prod_c_dpaux_hdmi { prod = < 0 0x00000124 0x000037fc 0x00000700 >; }; prod_c_dpaux_dp { prod = < 0 0x00000124 0x000037fe 0x000024b2 >; }; }; }; dpaux@155D0000 { prod-settings { #prod-cells = <4>; prod_c_dpaux_hdmi { prod = < 0 0x00000124 0x000037fc 0x00000700 >; }; prod_c_dpaux_dp { prod = < 0 0x00000124 0x000037fe 0x000024b2 >; }; }; }; dpaux@155E0000 { prod-settings { #prod-cells = <4>; prod_c_dpaux_hdmi { prod = < 0 0x00000124 0x000037fc 0x00000700 >; }; prod_c_dpaux_dp { prod = < 0 0x00000124 0x000037fe 0x000024b2 >; }; }; }; dpaux@155F0000 { prod-settings { #prod-cells = <4>; prod_c_dpaux_hdmi { prod = < 0 0x00000124 0x000037fc 0x00000700 >; }; prod_c_dpaux_dp { prod = < 0 0x00000124 0x000037fe 0x000024b2 >; }; }; }; nvcsi@15a00000 { prod-settings { #prod-cells = <4>; prod { prod = < 0 0x00011018 0x00070000 0x00020000 0 0x0001109c 0xe000e000 0xc000c000 0 0x000110a8 0x0000fefe 0x00004c4c 0 0x00011128 0xe000e000 0xc000c000 0 0x00011134 0x0000fefe 0x00004c4c 0 0x00021018 0x00070000 0x00020000 0 0x0002109c 0xe000e000 0xc000c000 0 0x000210a8 0x0000fefe 0x00004c4c 0 0x00021128 0xe000e000 0xc000c000 0 0x00021134 0x0000fefe 0x00004c4c 0 0x00031018 0x00070000 0x00020000 0 0x0003109c 0xe000e000 0xc000c000 0 0x000310a8 0x0000fefe 0x00004c4c 0 0x00031128 0xe000e000 0xc000c000 0 0x00031134 0x0000fefe 0x00004c4c 0 0x00041018 0x00070000 0x00020000 0 0x0004109c 0xe000e000 0xc000c000 0 0x000410a8 0x0000fefe 0x00004c4c 0 0x00041128 0xe000e000 0xc000c000 0 0x00041134 0x0000fefe 0x00004c4c 0 0x0001102c 0xfc000000 0xe0000000 0 0x000110b8 0xfc000000 0xe0000000 0 0x0002102c 0xfc000000 0xe0000000 0 0x000210b8 0xfc000000 0xe0000000 0 0x0003102c 0xfc000000 0xe0000000 0 0x000310b8 0xfc000000 0xe0000000 0 0x0004102c 0xfc000000 0xe0000000 0 0x000410b8 0xfc000000 0xe0000000>; }; prod_c_cphy_mode { prod = < 0 0x00011030 0x007f7f7f 0x00444444 0 0x000110bc 0x007f7f7f 0x00444444 0 0x00021030 0x007f7f7f 0x00444444 0 0x000210bc 0x007f7f7f 0x00444444 0 0x00031030 0x007f7f7f 0x00444444 0 0x000310bc 0x007f7f7f 0x00444444 0 0x00041030 0x007f7f7f 0x00444444 0 0x000410bc 0x007f7f7f 0x00444444 0 0x000110a8 0x0000ffff 0x0000fcfc 0 0x0001109c 0xffffffff 0xd848d848 0 0x000110a0 0x00000003 0x00000000 0 0x00011098 0x00000003 0x00000003 0 0x00011134 0x0000ffff 0x0000fcfc 0 0x00011128 0xffffffff 0xd848d848 0 0x0001112c 0x00000003 0x00000000 0 0x00011124 0x00000003 0x00000003 0 0x000210a8 0x0000ffff 0x0000fcfc 0 0x0002109c 0xffffffff 0xd848d848 0 0x000210a0 0x00000003 0x00000000 0 0x00021098 0x00000003 0x00000003 0 0x00021134 0x0000ffff 0x0000fcfc 0 0x00021128 0xffffffff 0xd848d848 0 0x0002112c 0x00000003 0x00000000 0 0x00021124 0x00000003 0x00000003 0 0x000310a8 0x0000ffff 0x0000fcfc 0 0x0003109c 0xffffffff 0xd848d848 0 0x000310a0 0x00000003 0x00000000 0 0x00031098 0x00000003 0x00000003 0 0x00031134 0x0000ffff 0x0000fcfc 0 0x00031128 0xffffffff 0xd848d848 0 0x0003112c 0x00000003 0x00000000 0 0x00031124 0x00000003 0x00000003 0 0x000410a8 0x0000ffff 0x0000fcfc 0 0x0004109c 0xffffffff 0xd848d848 0 0x000410a0 0x00000003 0x00000000 0 0x00041098 0x00000003 0x00000003 0 0x00041134 0x0000ffff 0x0000fcfc 0 0x00041128 0xffffffff 0xd848d848 0 0x0004112c 0x00000003 0x00000000 0 0x00041124 0x00000003 0x00000003>; }; prod_c_dphy_mode { prod = < 0 0x00011030 0x007f7f7f 0x00000000 0 0x000110bc 0x007f7f7f 0x00000000 0 0x00021030 0x007f7f7f 0x00000000 0 0x000210bc 0x007f7f7f 0x00000000 0 0x00031030 0x007f7f7f 0x00000000 0 0x000310bc 0x007f7f7f 0x00000000 0 0x00041030 0x007f7f7f 0x00000000 0 0x000410bc 0x007f7f7f 0x00000000>; }; }; }; pva0 { prod-settings { #prod-cells = <4>; prod { prod = < 0 0x00073000 0x00000001 0x00000001 0 0x00200050 0x00000001 0x00000000 0 0x00030000 0x00000001 0x00000001 0 0x0002804c 0x000000ff 0x000000ff>; }; }; }; pva1 { prod-settings { #prod-cells = <4>; prod { prod = < 0 0x00073000 0x00000001 0x00000001 0 0x00200050 0x00000001 0x00000000 0 0x00030000 0x00000001 0x00000001 0 0x0002804c 0x000000ff 0x000000ff>; }; }; }; }; ahci-sata@3507000 { prod-settings { #prod-cells = <4>; prod { prod = < 1 0x0000052C 0xFFFFFFFF 0x00031CE0 1 0x00000338 0x10000000 0x10000000 >; }; }; }; i2c@3160000 { prod-settings { #prod-cells = <4>; prod { prod = < 0 0x0000009c 0x0000ffff 0x00000308 0 0x000000d4 0x000000ff 0x00000000 0 0x000000d8 0x000000ff 0x00000000 0 0x000000dc 0x0000ffff 0x00000001 0 0x000000e0 0x0000ffff 0x00000002>; }; prod_c_fm { prod = < 0 0x0000006c 0xffff0000 0x003c0000 0 0x00000094 0x0000ffff 0x00000202 0 0x00000098 0xffffffff 0x02020202>; }; prod_c_fmplus { prod = < 0 0x0000006c 0xffff0000 0x00160000 0 0x00000094 0x0000ffff 0x00000202 0 0x00000098 0xffffffff 0x02020202>; }; prod_c_hs { prod = < 0 0x0000006c 0xffffffff 0x00020002 0 0x00000094 0x0000ffff 0x00000101 0 0x00000098 0xffffffff 0x02020202 0 0x000000a0 0x00ffffff 0x00090909>; }; prod_c_sm { prod = < 0 0x0000006c 0xffff0000 0x004f0000 0 0x00000094 0x0000ffff 0x00000708 0 0x00000098 0xffffffff 0x08080808>; }; }; }; i2c@c240000 { prod-settings { #prod-cells = <4>; prod { prod = < 0 0x0000009c 0x0000ffff 0x00000308 0 0x000000d4 0x000000ff 0x00000000 0 0x000000d8 0x000000ff 0x00000000 0 0x000000dc 0x0000ffff 0x00000001 0 0x000000e0 0x0000ffff 0x00000002>; }; prod_c_fm { prod = < 0 0x0000006c 0xffff0000 0x003c0000 0 0x00000094 0x0000ffff 0x00000202 0 0x00000098 0xffffffff 0x02020202>; }; prod_c_fmplus { prod = < 0 0x0000006c 0xffff0000 0x00160000 0 0x00000094 0x0000ffff 0x00000202 0 0x00000098 0xffffffff 0x02020202>; }; prod_c_hs { prod = < 0 0x0000006c 0xffffffff 0x00020002 0 0x00000094 0x0000ffff 0x00000101 0 0x00000098 0xffffffff 0x02020202 0 0x000000a0 0x00ffffff 0x00090909>; }; prod_c_sm { prod = < 0 0x0000006c 0xffff0000 0x004f0000 0 0x00000094 0x0000ffff 0x00000708 0 0x00000098 0xffffffff 0x08080808>; }; }; }; i2c@3180000 { prod-settings { #prod-cells = <4>; prod { prod = < 0 0x0000009c 0x0000ffff 0x00000308 0 0x000000d4 0x000000ff 0x00000000 0 0x000000d8 0x000000ff 0x00000000 0 0x000000dc 0x0000ffff 0x00000001 0 0x000000e0 0x0000ffff 0x00000002>; }; prod_c_fm { prod = < 0 0x0000006c 0xffff0000 0x003c0000 0 0x00000094 0x0000ffff 0x00000202 0 0x00000098 0xffffffff 0x02020202>; }; prod_c_fmplus { prod = < 0 0x0000006c 0xffff0000 0x00160000 0 0x00000094 0x0000ffff 0x00000202 0 0x00000098 0xffffffff 0x02020202>; }; prod_c_hs { prod = < 0 0x0000006c 0xffffffff 0x00580002 0 0x00000094 0x0000ffff 0x00000101 0 0x00000098 0xffffffff 0x02020202 0 0x000000a0 0x00ffffff 0x00090909>; }; prod_c_sm { prod = < 0 0x0000006c 0xffff0000 0x004f0000 0 0x00000094 0x0000ffff 0x00000708 0 0x00000098 0xffffffff 0x08080808>; }; }; }; i2c@3190000 { prod-settings { #prod-cells = <4>; prod { prod = < 0 0x0000009c 0x0000ffff 0x00000308 0 0x000000d4 0x000000ff 0x00000000 0 0x000000d8 0x000000ff 0x00000000 0 0x000000dc 0x0000ffff 0x00000001 0 0x000000e0 0x0000ffff 0x00000002>; }; prod_c_fm { prod = < 0 0x0000006c 0xffff0000 0x003c0000 0 0x00000094 0x0000ffff 0x00000202 0 0x00000098 0xffffffff 0x02020202>; }; prod_c_fmplus { prod = < 0 0x0000006c 0xffff0000 0x00160000 0 0x00000094 0x0000ffff 0x00000202 0 0x00000098 0xffffffff 0x02020202>; }; prod_c_hs { prod = < 0 0x0000006c 0xffffffff 0x00580002 0 0x00000094 0x0000ffff 0x00000101 0 0x00000098 0xffffffff 0x02020202 0 0x000000a0 0x00ffffff 0x00090909>; }; prod_c_sm { prod = < 0 0x0000006c 0xffff0000 0x004f0000 0 0x00000094 0x0000ffff 0x00000708 0 0x00000098 0xffffffff 0x08080808>; }; }; }; i2c@31b0000 { prod-settings { #prod-cells = <4>; prod { prod = < 0 0x0000009c 0x0000ffff 0x00000308 0 0x000000d4 0x000000ff 0x00000000 0 0x000000d8 0x000000ff 0x00000000 0 0x000000dc 0x0000ffff 0x00000001 0 0x000000e0 0x0000ffff 0x00000002>; }; prod_c_fm { prod = < 0 0x0000006c 0xffff0000 0x003c0000 0 0x00000094 0x0000ffff 0x00000202 0 0x00000098 0xffffffff 0x02020202>; }; prod_c_fmplus { prod = < 0 0x0000006c 0xffff0000 0x00160000 0 0x00000094 0x0000ffff 0x00000202 0 0x00000098 0xffffffff 0x02020202>; }; prod_c_hs { prod = < 0 0x0000006c 0xffffffff 0x00580002 0 0x00000094 0x0000ffff 0x00000201 0 0x00000098 0xffffffff 0x02020202 0 0x000000a0 0x00ffffff 0x00090909>; }; prod_c_sm { prod = < 0 0x0000006c 0xffff0000 0x004f0000 0 0x00000094 0x0000ffff 0x00000708 0 0x00000098 0xffffffff 0x08080808>; }; }; }; i2c@31c0000 { prod-settings { #prod-cells = <4>; prod { prod = < 0 0x0000009c 0x0000ffff 0x00000308 0 0x000000d4 0x000000ff 0x00000000 0 0x000000d8 0x000000ff 0x00000000 0 0x000000dc 0x0000ffff 0x00000001 0 0x000000e0 0x0000ffff 0x00000002>; }; prod_c_fm { prod = < 0 0x0000006c 0xffff0000 0x003c0000 0 0x00000094 0x0000ffff 0x00000202 0 0x00000098 0xffffffff 0x02020202>; }; prod_c_fmplus { prod = < 0 0x0000006c 0xffff0000 0x00160000 0 0x00000094 0x0000ffff 0x00000202 0 0x00000098 0xffffffff 0x02020202>; }; prod_c_hs { prod = < 0 0x0000006c 0xffffffff 0x00580002 0 0x00000094 0x0000ffff 0x00000101 0 0x00000098 0xffffffff 0x02020202 0 0x000000a0 0x00ffffff 0x00090909>; }; prod_c_sm { prod = < 0 0x0000006c 0xffff0000 0x004f0000 0 0x00000094 0x0000ffff 0x00000708 0 0x00000098 0xffffffff 0x08080808>; }; }; }; i2c@c250000 { prod-settings { #prod-cells = <4>; prod { prod = < 0 0x0000009c 0x0000ffff 0x00000308 0 0x000000d4 0x000000ff 0x00000000 0 0x000000d8 0x000000ff 0x00000000 0 0x000000dc 0x0000ffff 0x00000001 0 0x000000e0 0x0000ffff 0x00000002>; }; prod_c_fm { prod = < 0 0x0000006c 0xffff0000 0x003c0000 0 0x00000094 0x0000ffff 0x00000202 0 0x00000098 0xffffffff 0x02020202>; }; prod_c_fmplus { prod = < 0 0x0000006c 0xffff0000 0x00160000 0 0x00000094 0x0000ffff 0x00000202 0 0x00000098 0xffffffff 0x02020202>; }; prod_c_hs { prod = < 0 0x0000006c 0xffffffff 0x00580002 0 0x00000094 0x0000ffff 0x00000101 0 0x00000098 0xffffffff 0x02020202 0 0x000000a0 0x00ffffff 0x00090909>; }; prod_c_sm { prod = < 0 0x0000006c 0xffff0000 0x004f0000 0 0x00000094 0x0000ffff 0x00000708 0 0x00000098 0xffffffff 0x08080808>; }; }; }; i2c@31e0000 { prod-settings { #prod-cells = <4>; prod { prod = < 0 0x0000009c 0x0000ffff 0x00000308 0 0x000000d4 0x000000ff 0x00000000 0 0x000000d8 0x000000ff 0x00000000 0 0x000000dc 0x0000ffff 0x00000001 0 0x000000e0 0x0000ffff 0x00000002>; }; prod_c_fm { prod = < 0 0x0000006c 0xffff0000 0x003c0000 0 0x00000094 0x0000ffff 0x00000202 0 0x00000098 0xffffffff 0x02020202>; }; prod_c_fmplus { prod = < 0 0x0000006c 0xffff0000 0x00160000 0 0x00000094 0x0000ffff 0x00000202 0 0x00000098 0xffffffff 0x02020202>; }; prod_c_hs { prod = < 0 0x0000006c 0xffffffff 0x00580002 0 0x00000094 0x0000ffff 0x00000101 0 0x00000098 0xffffffff 0x02020202 0 0x000000a0 0x00ffffff 0x00090909>; }; prod_c_sm { prod = < 0 0x0000006c 0xffff0000 0x004f0000 0 0x00000094 0x0000ffff 0x00000708 0 0x00000098 0xffffffff 0x08080808>; }; }; }; mipical@3990000 { prod-settings { #prod-cells = <4>; prod { prod = < 0 0x00000044 0x003f0000 0x00000000 0 0x00000048 0x003f0000 0x00000000 0 0x0000004c 0x003f0000 0x00000000 0 0x00000050 0x003f0000 0x00000000 0 0x0000006c 0x000f00f4 0x00010010 0 0x00000070 0x003f0000 0x00000000 0 0x00000074 0x003f0000 0x00000000 0 0x0000007c 0x003f0000 0x00000000 0 0x00000080 0x003f0000 0x00000000>; }; prod_c_cphy_csi { prod = < 0 0x00000018 0x0000f81f 0x00000000 0 0x0000001c 0x0000f81f 0x00000000 0 0x00000020 0x0000f81f 0x00000000 0 0x00000024 0x0000f81f 0x00000000 0 0x00000028 0x0000f81f 0x00000000 0 0x0000002c 0x0000f81f 0x00000000 0 0x00000030 0x0000f81f 0x00000000 0 0x00000034 0x0000f81f 0x00000000>; }; prod_c_dphy_csi { prod = < 0 0x00000018 0x0000f81f 0x00000000 0 0x0000001c 0x0000f81f 0x00000000 0 0x00000020 0x0000f81f 0x00000000 0 0x00000024 0x0000f81f 0x00000000 0 0x00000028 0x0000f81f 0x00000000 0 0x0000002c 0x0000f81f 0x00000000 0 0x00000030 0x0000f81f 0x00000000 0 0x00000034 0x0000f81f 0x00000000>; }; }; }; tegra_nvlink_controller { prod-settings { #prod-cells = <4>; prod { prod = < 0 0x00000038 0x00000001 0x00000001 0 0x00000054 0x003fffff 0x00000000 0 0x00000058 0x003fffff 0x00000000>; }; }; }; pinctrl@3790000 { prod-settings { #prod-cells = <4>; prod { prod = < 0 0x00000000 0x00000038 0x00000010 0 0x00000004 0x00000038 0x00000010 1 0x00000000 0x00000038 0x00000010>; }; }; }; pmc@c360000 { prod-settings { #prod-cells = <4>; prod { prod = < 1 0x0000202c 0x80000000 0x80000000 2 0x00000010 0x00000001 0x00000001>; }; }; }; se_elp@3ad0000 { prod-settings { #prod-cells = <4>; prod { prod = < 1 0x00000f04 0x00000008 0x00000008 1 0x00000f08 0x00000002 0x00000002 1 0x00000fec 0x00000002 0x00000000>; }; }; }; sdhci@3400000 { prod-settings { #prod-cells = <4>; prod_c_1_8v { prod = < 0 0x000001e0 0x07f00000 0x00600000>; }; prod_c_3_3v { prod = < 0 0x000001e0 0x07f00000 0x00800000>; }; prod { prod = < 0 0x00000004 0x00000fff 0x00000200 0 0x00000028 0x00000022 0x00000002 0 0x00000100 0x1fff004a 0x05090000 0 0x00000128 0x42000000 0x00000000 0 0x000001ac 0x00000004 0x00000000 0 0x000001c0 0x00001fc0 0x00000040 0 0x000001c4 0x0003ff77 0x00000400 0 0x000001e0 0x8007f000 0x00007000 0 0x000001e4 0x20007F7F 0x20007A00 0 0x00000204 0x80000000 0x00000000>; }; prod_c_ds { prod = < 0 0x00000100 0x1fff0000 0x05090000>; }; prod_c_hs { prod = < 0 0x00000100 0x1fff0000 0x05090000>; }; prod_c_ddr52 { prod = < 0 0x0000003c 0x00070000 0x00040000 0 0x00000120 0x0000fffe 0x00000298>; }; prod_c_hs200 { prod = < 0 0x0000003c 0x00070000 0x00030000 0 0x000001c0 0x0000e000 0x00004000>; }; prod_c_sdr104 { prod = < 0 0x0000003c 0x00070000 0x00030000 0 0x000001c0 0x0000e000 0x00004000>; }; prod_c_sdr12 { prod = < 0 0x0000003c 0x00070000 0x00000000>; }; prod_c_sdr25 { prod = < 0 0x0000003c 0x00070000 0x00010000>; }; prod_c_sdr50 { prod = < 0 0x0000003c 0x00070000 0x00020000 0 0x000001c0 0x0000e000 0x00008000>; }; }; }; sdhci@3440000 { prod-settings { #prod-cells = <4>; prod_c_1_8v { prod = < 0 0x000001e0 0x07f00000 0x00600000>; }; prod_c_3_3v { prod = < 0 0x000001e0 0x07f00000 0x00800000>; }; prod { prod = < 0 0x00000004 0x00000fff 0x00000200 0 0x00000028 0x00000022 0x00000002 0 0x00000100 0x1fff004a 0x05090000 0 0x00000128 0x42000000 0x00000000 0 0x000001ac 0x00000004 0x00000000 0 0x000001c0 0x00001fc0 0x00000040 0 0x000001c4 0x0003ff77 0x00000400 0 0x000001e0 0x8007f000 0x00007000 0 0x000001e4 0x20000000 0x20000000 0 0x00000204 0x80000000 0x00000000>; }; prod_c_ds { prod = < 0 0x00000100 0x1fff0000 0x05090000>; }; prod_c_hs { prod = < 0 0x00000100 0x1fff0000 0x05090000>; }; prod_c_ddr52 { prod = < 0 0x0000003c 0x00070000 0x00040000 0 0x00000120 0x0000fffe 0x00000298>; }; prod_c_hs200 { prod = < 0 0x0000003c 0x00070000 0x00030000 0 0x000001c0 0x0000e000 0x00004000>; }; prod_c_sdr104 { prod = < 0 0x0000003c 0x00070000 0x00030000 0 0x000001c0 0x0000e000 0x00004000>; }; prod_c_sdr12 { prod = < 0 0x0000003c 0x00070000 0x00000000>; }; prod_c_sdr25 { prod = < 0 0x0000003c 0x00070000 0x00010000>; }; prod_c_sdr50 { prod = < 0 0x0000003c 0x00070000 0x00020000 0 0x000001c0 0x0000e000 0x00008000>; }; }; }; sdhci@3460000 { prod-settings { #prod-cells = <4>; prod { prod = < 0 0x00000004 0x00000fff 0x00000200 0 0x00000028 0x00000020 0x00000020 0 0x00000100 0x1fff004a 0x14080000 0 0x0000010c 0x00003f00 0x00002800 0 0x00000128 0x43000000 0x00000000 0 0x000001ac 0x00000004 0x00000000 0 0x000001c0 0x00001fc0 0x00000040 0 0x000001c4 0x0003ff77 0x00000400 0 0x000001e0 0x87f7f000 0x00a0a000 0 0x000001e4 0x20000000 0x20000000 0 0x00000204 0x80000000 0x00000000 0 0x00000218 0x80000000 0x00000000>; }; prod_c_ds { prod = < 0 0x00000100 0x1fff0000 0x14080000>; }; prod_c_hs { prod = < 0 0x00000100 0x1fff0000 0x14080000>; }; prod_c_cqe { prod = < 0 0x0000f008 0x00000001 0x00000001>; }; prod_c_ddr52 { prod = < 0 0x0000003c 0x00070000 0x00040000 0 0x00000120 0x0000fffe 0x00000298>; }; prod_c_hs200 { prod = < 0 0x0000003c 0x00070000 0x00030000 0 0x000001c0 0x0000e000 0x00004000>; }; prod_c_hs400 { prod = < 0 0x0000003c 0x00070000 0x00050000 0 0x00000100 0x00ff0008 0x00080008 0 0x000001c0 0x0000e000 0x00004000 0 0x000001e4 0x00007f7f 0x00000000>; }; prod_c_sdr50 { prod = < 0 0x0000003c 0x00070000 0x00020000>; }; }; }; xusb_padctl@3520000 { prod-settings { #prod-cells = <4>; prod_c_bias { prod = <0 0x284 0x00000038 0x38>; }; prod { prod = < 0 0x00000024 0x00000fff 0x00000000>; }; }; }; ether_qos@2490000 { prod-settings { #prod-cells = <4>; prod { prod = < 0 0x00008800 0x80000000 0x00000000 0 0x00008804 0x20000000 0x20000000>; }; }; }; }; # 21 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-cvm.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-floor-sweeping.dtsi" 1 # 16 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-floor-sweeping.dtsi" / { plugin-manager { fragment-fs-disable-isp { fuse-info = "fuse-disable-isp"; override@0 { target = <&isp>; _overlay_ { status = "disabled"; }; }; }; fragment-fs-disable-nvenc { fuse-info = "fuse-disable-nvenc"; override@0 { target = <&{/host1x/nvenc@154c0000}>; _overlay_ { status = "disabled"; }; }; override@1 { target = <&{/host1x/nvenc1@15a80000}>; _overlay_ { status = "disabled"; }; }; }; fragment-fs-disable-pva { fuse-info = "fuse-disable-pva"; override@0 { target = <&pva0>; _overlay_ { status = "disabled"; }; }; override@1 { target = <&pva1>; _overlay_ { status = "disabled"; }; }; }; fragment-fs-disable-dla { fuse-info = "fuse-disable-dla"; override@0 { target = <&nvdla0>; _overlay_ { status = "disabled"; }; }; override@1 { target = <&nvdla1>; _overlay_ { status = "disabled"; }; }; }; fragment-fs-disable-cv { fuse-info = "fuse-disable-cv"; override@0 { target = <&{/tegra-cvnas}>; _overlay_ { status = "disabled"; }; }; }; }; }; # 22 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-cvm.dtsi" 2 / { cpus { cpu@1 { status = "okay"; }; cpu@2 { status = "okay"; }; cpu@3 { status = "okay"; }; cpu@4 { status = "okay"; }; cpu@5 { status = "okay"; }; cpu@6 { status = "okay"; }; cpu@7 { status = "okay"; }; }; L2_1: l2-cache1 { status = "okay"; }; L2_2: l2-cache2 { status = "okay"; }; L2_3: l2-cache3 { status = "okay"; }; tegra-carveouts { status = "okay"; }; reserved-memory { vpr: vpr-carveout { compatible = "nvidia,vpr-carveout"; size = <0 0x2a000000>; alignment = <0 0x400000>; alloc-ranges = <0x0 0x80000000 0x0 0x70000000>; reusable; }; }; mc { status = "okay"; }; power-domain { status = "okay"; }; interrupt-controller { status = "okay"; }; clock@0 { status = "okay"; }; ether_qos@2490000 { status = "okay"; }; bpmp_reset@0 { status = "okay"; }; bpmp { status = "okay"; }; gv11b { status = "okay"; }; dma@2600000 { status = "okay"; }; pinmux@2430000 { status = "okay"; }; gpio@2200000 { status = "okay"; port-GG-interrupt-line = <0x0>; }; gpio@c2f0000 { status = "okay"; }; i2c@3160000 { status = "okay"; }; i2c@c240000 { status = "okay"; }; i2c@3180000 { status = "okay"; }; i2c@3190000 { status = "okay"; }; bpmp_i2c { status = "okay"; }; i2c@31b0000 { status = "okay"; }; i2c@31c0000 { status = "okay"; }; i2c@c250000 { status = "okay"; }; i2c@31e0000 { status = "okay"; }; efuse@3820000 { status = "okay"; efuse-burn { status = "okay"; }; }; kfuse@3830000 { status = "okay"; }; tegra194-pm-irq { status = "okay"; }; pwm@c340000 { status = "okay"; }; tachometer@39c0000 { status = "okay"; }; generic_pwm_tachometer { status = "okay"; }; host1x { se@15810000 { status = "okay"; }; se@15820000 { status = "okay"; }; se@15830000 { status = "okay"; }; se@15840000 { status = "okay"; }; }; se_elp@3ad0000 { status = "okay"; }; pmc@c360000 { status = "okay"; }; pmc@c370000 { status = "okay"; }; rtc@c2a0000 { status = "okay"; }; gpio-keys { status = "okay"; }; tegra-cache { status = "okay"; }; reserved-memory { grid-of-semaphores { status = "okay"; }; }; tegra-cvnas { status = "okay"; }; mc { status = "okay"; }; mc_sid@2c00000 { status = "okay"; }; interrupt-controller@3881000 { status = "okay"; }; timer { status = "okay"; }; cbb-noc@2300000 { status = "okay"; }; aon-noc@C600000 { status = "okay"; }; bpmp-noc@D600000 { status = "okay"; }; rce-noc@BE00000 { status = "okay"; }; sce-noc@B600000 { status = "okay"; }; cv-noc@14040000 { status = "okay"; }; axi2apb@2390000 { status = "okay"; }; actmon@d230000 { status = "okay"; mc_all { status = "okay"; }; }; iommu@12000000 { status = "okay"; }; tegra-hsp@c150000 { status = "okay"; }; tegra-hsp@3c00000 { status = "okay"; }; host1x { ctx0 { status = "okay"; }; ctx1 { status = "okay"; }; ctx2 { status = "okay"; }; ctx3 { status = "okay"; }; ctx4 { status = "okay"; }; ctx5 { status = "okay"; }; ctx6 { status = "okay"; }; ctx7 { status = "okay"; }; }; psci { status = "okay"; }; cpufreq { status = "okay"; cpufreq_single_policy; }; arm64_ras { status = "okay"; }; carmel_ras { status = "okay"; }; }; # 22 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-cvm-p2888-0000-a00.dtsi" 2 / { model = "Jetson-AGX"; compatible = "nvidia,tegra194"; #address-cells = <2>; #size-cells = <2>; pmc@c360000 { iopad-defaults { sdmmc-io-pads { pins = "sdmmc1-hv", "sdmmc3-hv"; nvidia,enable-voltage-switching; }; }; }; pmc@c370000 { nvidia,invert-interrupt; }; plugin-manager { fragment-p2888-mods { odm-data = "mods-build"; override@0 { target = <&gpcdma>; _overlay_ { nvidia,bypass-smmu; }; }; }; }; }; # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0000-a00.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-eeprom-manager-p2888-0000.dtsi" 1 # 14 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-eeprom-manager-p2888-0000.dtsi" / { eeprom-manager { data-size = <0x100>; bus@0 { i2c-bus = <&gen1_i2c>; eeprom@0 { slave-address = <0x50>; label = "cvm"; }; eeprom@1 { slave-address = <0x56>; }; }; bus@1 { i2c-bus = <&cam_i2c>; eeprom@0 { slave-address = <0x54>; }; eeprom@1 { slave-address = <0x57>; }; eeprom@2 { slave-address = <0x52>; }; }; bus@2 { i2c-bus = <&gen2_i2c>; eeprom@0 { slave-address = <0x52>; label = "cvm"; }; eeprom@1 { slave-address = <0x50>; }; }; }; }; # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0000-a00.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-powermon-p2888.dtsi" 1 # 14 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-powermon-p2888.dtsi" / { p2888_shuntv_offset: shuntv-offset { offset = <0>; conditional_offset@0 { shunt_volt_start = <0xFFFFFFD8>; shunt_volt_end = <0xFFFFFFD8>; offset = <40>; }; }; i2c@c240000 { ina3221x_40: ina3221x@40 { compatible = "ti,ina3221x"; reg = <0x40>; ti,trigger-config = <0x7003>; ti,continuous-config = <0x7c07>; ti,enable-forced-continuous; #address-cells = <1>; #size-cells = <0>; #io-channel-cells = <1>; channel@0 { reg = <0x0>; ti,rail-name = "GPU"; ti,shunt-resistor-mohm = <5>; shunt-volt-offset-uv = <&p2888_shuntv_offset>; }; channel@1 { reg = <0x1>; ti,rail-name = "CPU"; ti,shunt-resistor-mohm = <5>; shunt-volt-offset-uv = <&p2888_shuntv_offset>; }; channel@2 { reg = <0x2>; ti,rail-name = "SOC"; ti,shunt-resistor-mohm = <5>; shunt-volt-offset-uv = <&p2888_shuntv_offset>; }; }; ina3221x_41: ina3221x@41 { compatible = "ti,ina3221x"; reg = <0x41>; ti,trigger-config = <0x7003>; ti,continuous-config = <0x7c07>; ti,enable-forced-continuous; #address-cells = <1>; #size-cells = <0>; #io-channel-cells = <1>; channel@0 { reg = <0x0>; ti,rail-name = "CV"; ti,shunt-resistor-mohm = <5>; shunt-volt-offset-uv = <&p2888_shuntv_offset>; }; channel@1 { reg = <0x1>; ti,rail-name = "VDDRQ"; ti,shunt-resistor-mohm = <5>; shunt-volt-offset-uv = <&p2888_shuntv_offset>; }; channel@2 { reg = <0x2>; ti,rail-name = "SYS5V"; ti,shunt-resistor-mohm = <5>; shunt-volt-offset-uv = <&p2888_shuntv_offset>; }; }; }; }; # 19 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0000-a00.dtsi" 2 / { serial@3100000 { compatible = "nvidia,tegra186-hsuart"; uart-has-rtscts; status = "okay"; }; serial@3140000 { compatible = "nvidia,tegra186-hsuart"; status = "okay"; }; combined-uart { console-port; combined-uart; status = "okay"; }; pwm@c340000 { status = "okay"; }; tachometer@39c0000 { status = "okay"; }; sdhci@3460000 { uhs-mask = <0x0>; nvidia,enable-hwcq; status = "okay"; }; mipical@3990000 { status = "okay"; }; tegra-hsp@b950000 { status = "okay"; }; rtcpu@bc00000 { status = "okay"; nvidia,cmd-timeout = <2000>; }; gpio@c2f0000 { status = "okay"; gpio-line-names = "CAN1_DOUT", "CAN1_DIN", "CAN0_DOUT", "CAN0_DIN", "GPIO4", "GPIO5", "GPIO6", "GPIO7", "GPIO8", "GPIO9", "GPIO10", "GPIO11", "GPIO12", "GPIO13", "GPIO14", "GPIO15", "GPIO16", "GPIO17", "GPIO18", "GPIO19", "GPIO20", "GPIO21", "GPIO22", "I2C2_CLK", "I2C2_DAT", "", "", "", "", ""; pex-refclk-sel-low { gpio-hog; output-low; gpios = <((0 * 8) + 5) 0>; label = "pex_refclk_sel_low"; status = "disabled"; }; pex-refclk-sel-high { gpio-hog; output-high; gpios = <((0 * 8) + 5) 0>; label = "pex_refclk_sel_high"; status = "disabled"; }; tpm-rst-pin { gpio-hog; gpios = <((1 * 8) + 0) 0>; label = "tpm-rst-pin"; output-high; status = "okay"; }; }; gpio@2200000 { status = "okay"; gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "GPIO35", "", "", "", "", "", "", "I2S2_CLK", "I2S2_DOUT", "I2S2_DIN", "I2S2_FS", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "GPIO32", "", "", "", "", "GPIO17", "", "", "", "", "MCLK05", "", "", "", "UART1_TX", "UART1_RX", "UART1_RTS", "UART1_CTS", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "SPI3_CS0_N", "", "", "", "", "", "", "", "SPI1_CLK", "SPI1_MISO", "SPI1_MOSI", "SPI1_CS0_N", "SPI1_CS1_N", "", ""; CVM_CD_A_OE { gpio-hog; output-high; gpios = <((0 * 8) + 2) 0>; label = "CVM_CD_A_OE"; status = "okay"; }; # 181 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0000-a00.dtsi" }; pcie@14180000 { status = "okay"; nvidia,disable-aspm-states = <0xf>; nvidia,enable-power-down; nvidia,disable-clock-request; phys = <&p2u_2>, <&p2u_3>, <&p2u_4>, <&p2u_5>; phy-names = "pcie-p2u-0", "pcie-p2u-1", "pcie-p2u-2", "pcie-p2u-3"; }; pcie@14100000 { status = "okay"; nvidia,disable-aspm-states = <0xc>; nvidia,enable-power-down; nvidia,disable-clock-request; nvidia,max-speed = <2>; phys = <&p2u_0>; phy-names = "pcie-p2u-0"; }; pcie@14140000 { status = "okay"; nvidia,pex-wake = <&tegra_main_gpio ((11 * 8) + 2) 0>; nvidia,disable-aspm-states = <0xf>; nvidia,enable-power-down; nvidia,disable-clock-request; phys = <&p2u_7>; phy-names = "pcie-p2u-0"; }; pcie@14160000 { status = "okay"; vddio-pex-ctl-supply = <&p2888_spmic_sd3>; nvidia,disable-aspm-states = <0xf>; nvidia,enable-power-down; nvidia,disable-clock-request; nvidia,max-speed = <4>; phys = <&p2u_8>, <&p2u_9>; phy-names = "pcie-p2u-0", "pcie-p2u-1"; }; pcie@141a0000 { status = "disabled"; nvidia,disable-aspm-states = <0xf>; nvidia,enable-power-down; nvidia,disable-clock-request; nvidia,plat-gpios = < >; phys = <&p2u_12>, <&p2u_13>, <&p2u_14>, <&p2u_15>, <&p2u_16>, <&p2u_17>, <&p2u_18>, <&p2u_19>; phy-names = "pcie-p2u-0", "pcie-p2u-1", "pcie-p2u-2", "pcie-p2u-3", "pcie-p2u-4", "pcie-p2u-5", "pcie-p2u-6", "pcie-p2u-7"; }; pcie_ep@141a0000 { status = "disabled"; nvidia,disable-aspm-states = <0xf>; phys = <&p2u_12>, <&p2u_13>, <&p2u_14>, <&p2u_15>, <&p2u_16>, <&p2u_17>, <&p2u_18>, <&p2u_19>; phy-names = "pcie-p2u-0", "pcie-p2u-1", "pcie-p2u-2", "pcie-p2u-3", "pcie-p2u-4", "pcie-p2u-5", "pcie-p2u-6", "pcie-p2u-7"; nvidia,pex-rst-gpio = <&tegra_main_gpio ((27 * 8) + 1) 1>; }; i2c@c240000 { multi-master; }; hardwood { compatible = "nvidia,denver-hardwood"; interrupts = <0 24 0x4>; }; }; # 19 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0001-p2822-0000-common.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-platforms-eqos.dtsi" 1 # 23 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-platforms-eqos.dtsi" / { ether_qos@2490000 { nvidia,ptp_ref_clock_speed = <312500000>; nvidia,rxq_enable_ctrl = <2 2 2 2>; nvidia,queue_prio = <0 1 2 3>; nvidia,use_tagged_ptp; nvidia,ptp_dma_ch = <3>; nvidia,chan_napi_quota = <64 64 64 64>; nvidia,pause_frames = <0>; nvidia,phy-reset-gpio = <&tegra_main_gpio ((6 * 8) + 5) 0>; nvidia,phy-max-frame-size = <16>; nvidia,eth_iso_enable = <1>; phy-mode = "rgmii-id"; phy-handle = <&phy0>; mdio { compatible = "nvidia,eqos-mdio"; #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@0 { reg = <0>; phy_rst_lp_mode = <1>; interrupt-parent = <&tegra_main_gpio>; interrupts = <((6 * 8) + 4) 0x00000008>; marvell,copper-mode; marvell,reg-init = <0x03 0x12 0x7fff 0x880>; }; }; }; thermal-zones { CPU-therm { trips { eqos_m40: eqos-m40@-40000 { temperature = <(-40000)>; hysteresis = <5000>; type = "active"; }; eqos_m5: eqos-m5@-5000 { temperature = <(-5000)>; hysteresis = <5000>; type = "active"; }; eqos_p30: eqos-p30@30000 { temperature = <(30000)>; hysteresis = <5000>; type = "active"; }; eqos_p65: eqos-p65@65000 { temperature = <(65000)>; hysteresis = <5000>; type = "active"; }; eqos_p100: eqos-p100@100000 { temperature = <(100000)>; hysteresis = <5000>; type = "active"; }; }; cooling-maps { map_eqos_m40 { trip = <&eqos_m40>; cooling-device = <&eqos_cool_dev 1 1>; cdev-type = "tegra-eqos"; }; map_eqos_m5 { trip = <&eqos_m5>; cooling-device = <&eqos_cool_dev 2 2>; cdev-type = "tegra-eqos"; }; map_eqos_p30 { trip = <&eqos_p30>; cooling-device = <&eqos_cool_dev 3 3>; cdev-type = "tegra-eqos"; }; map_eqos_p65 { trip = <&eqos_p65>; cooling-device = <&eqos_cool_dev 4 4>; cdev-type = "tegra-eqos"; }; map_eqos_p100 { trip = <&eqos_p100>; cooling-device = <&eqos_cool_dev 5 5>; cdev-type = "tegra-eqos"; }; }; }; }; }; # 20 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0001-p2822-0000-common.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-a00.dtsi" 1 # 14 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-a00.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-cvb-p2822-0000-a00.dtsi" 1 # 14 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-cvb-p2822-0000-a00.dtsi" / { soft_wdt:soft_watchdog { compatible = "softdog-platform"; status = "okay"; }; plugin-manager { fragement-tegra-wdt-en { odm-data = "enable-denver-wdt"; override@0 { target = <&tegra_wdt>; _overlay_ { status = "okay"; }; }; }; fragemen-tegra-wdt-dis { odm-data = "disable-denver-wdt"; override@0 { target = <&tegra_pmc>; _overlay_ { nvidia,enable-halt-in-fiq; }; }; }; fragement-soft-wdt { odm-data = "enable-pmic-wdt", "enable-denver-wdt"; override@0 { target = <&soft_wdt>; _overlay_ { status = "disabled"; }; }; }; }; i2c@c240000 { ucsi_ccg: ucsi_ccg@8 { compatible = "nvidia,ucsi_ccg"; reg = <0x08>; ccg,irqflags = <0x00000008>; interrupt-parent = <&tegra_aon_gpio>; interrupts = <((1 * 8) + 2) 0>; wakeup-source; status = "okay"; }; }; }; # 15 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-a00.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-audio-p2822-0000.dtsi" 1 # 16 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-audio-p2822-0000.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/tegra/common/kernel-dts/audio/tegra-platforms-audio-dai-links.dtsi" 1 # 19 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/tegra/common/kernel-dts/audio/tegra-platforms-audio-dai-links.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/tegra/common/kernel-dts/audio/tegra-platforms-audio-simple-bus.dtsi" 1 # 19 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/tegra/common/kernel-dts/audio/tegra-platforms-audio-simple-bus.dtsi" / { spdif_dit { compatible = "simple-bus"; device_type = "spdif-dit"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; spdif_dit0: spdif-dit.0@0 { compatible = "linux,spdif-dit"; reg = <0x0>; status = "disabled"; }; spdif_dit1: spdif-dit.1@1 { compatible = "linux,spdif-dit"; reg = <0x1>; status = "disabled"; }; spdif_dit2: spdif-dit.2@2 { compatible = "linux,spdif-dit"; reg = <0x2>; status = "disabled"; }; spdif_dit3: spdif-dit.3@3 { compatible = "linux,spdif-dit"; reg = <0x03>; status = "disabled"; }; spdif_dit4: spdif-dit.4@4 { compatible = "linux,spdif-dit"; reg = <0x04>; status = "disabled"; }; spdif_dit5: spdif-dit.5@5 { compatible = "linux,spdif-dit"; reg = <0x05>; status = "disabled"; }; spdif_dit6: spdif-dit.6@6 { compatible = "linux,spdif-dit"; reg = <0x06>; status = "disabled"; }; spdif_dit7: spdif-dit.7@7 { compatible = "linux,spdif-dit"; reg = <0x07>; status = "disabled"; }; spdif_dit8: spdif-dit.8@8 { compatible = "linux,spdif-dit"; reg = <0x08>; status = "disabled"; }; spdif_dit9: spdif-dit.9@9 { compatible = "linux,spdif-dit"; reg = <0x09>; status = "disabled"; }; spdif_dit10: spdif-dit.10@a { compatible = "linux,spdif-dit"; reg = <0x0a>; status = "disabled"; }; spdif_dit11: spdif-dit.11@b { compatible = "linux,spdif-dit"; reg = <0x0b>; status = "disabled"; }; spdif_dit12: spdif-dit.12@c { compatible = "linux,spdif-dit"; reg = <0x0c>; status = "disabled"; }; spdif_dit13: spdif-dit.13@d { compatible = "linux,spdif-dit"; reg = <0x0d>; status = "disabled"; }; }; }; # 20 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/tegra/common/kernel-dts/audio/tegra-platforms-audio-dai-links.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/tegra/common/kernel-dts/audio/tegra-platforms-audio-enable.dtsi" 1 # 19 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/tegra/common/kernel-dts/audio/tegra-platforms-audio-enable.dtsi" / { aconnect@2a41000 { status = "okay"; ahub { status = "okay"; admaif@290f000 { status = "okay"; }; sfc@2902000 { status = "okay"; }; sfc@2902200 { status = "okay"; }; sfc@2902400 { status = "okay"; }; sfc@2902600 { status = "okay"; }; spkprot@2908c00 { status = "okay"; }; amixer@290bb00 { status = "okay"; }; i2s@2901000 { status = "okay"; }; i2s@2901100 { status = "okay"; }; i2s@2901200 { status = "okay"; }; i2s@2901300 { status = "okay"; }; i2s@2901400 { status = "okay"; }; i2s@2901500 { status = "okay"; }; amx@2903000 { status = "okay"; }; amx@2903100 { status = "okay"; }; amx@2903200 { status = "okay"; }; amx@2903300 { status = "okay"; }; adx@2903800 { status = "okay"; }; adx@2903900 { status = "okay"; }; adx@2903a00 { status = "okay"; }; adx@2903b00 { status = "okay"; }; dmic@2904000 { status = "okay"; }; dmic@2904100 { status = "okay"; }; dmic@2904200 { status = "okay"; }; dmic@2904300 { status = "okay"; }; afc@2907000 { status = "okay"; }; afc@2907100 { status = "okay"; }; afc@2907200 { status = "okay"; }; afc@2907300 { status = "okay"; }; afc@2907400 { status = "okay"; }; afc@2907500 { status = "okay"; }; mvc@290a000 { status = "okay"; }; mvc@290a200 { status = "okay"; }; iqc@290e000 { status = "okay"; }; asrc@2910000 { status = "okay"; }; arad@290e400 { status = "okay"; }; ahc@290b900 { status = "okay"; }; ope@2908000 { status = "okay"; peq@2908100 { status = "okay"; }; mbdrc@2908200 { status = "okay"; }; }; dspk@2905000 { status = "okay"; }; dspk@2905100 { status = "okay"; }; }; adma@2930000 { status = "okay"; }; adsp_audio { status = "okay"; }; }; spdif_dit { status = "okay"; spdif-dit.0@0 { status = "okay"; }; spdif-dit.1@1 { status = "okay"; }; spdif-dit.2@2 { status = "okay"; }; spdif-dit.3@3 { status = "okay"; }; spdif-dit.4@4 { status = "okay"; }; spdif-dit.5@5 { status = "okay"; }; spdif-dit.6@6 { status = "okay"; }; spdif-dit.7@7 { status = "okay"; }; spdif-dit.8@8 { status = "okay"; }; spdif-dit.9@9 { status = "okay"; }; spdif-dit.10@a { status = "okay"; }; spdif-dit.11@b { status = "okay"; }; spdif-dit.12@c { status = "okay"; }; spdif-dit.13@d { status = "okay"; }; }; }; # 21 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/tegra/common/kernel-dts/audio/tegra-platforms-audio-dai-links.dtsi" 2 / { aconnect@2a41000 { adsp_audio { compr-ops = <1>; num-plugin = <6>; plugin-info-1 { plugin-name = "mp3-dec1"; firmware-name = "nvmp3dec.elf"; widget-name = "MP3-DEC1"; }; plugin-info-2 { plugin-name = "spkprot"; firmware-name = "nvspkprot.elf"; widget-name = "SPKPROT-SW"; }; plugin-info-3 { plugin-name = "src"; firmware-name = "nvsrc.elf"; widget-name = "SRC"; }; plugin-info-4 { plugin-name = "aac-dec1"; firmware-name = "nvaacdec.elf"; widget-name = "AAC-DEC1"; }; plugin-info-5 { plugin-name = "aec"; firmware-name = "nvoice.elf"; widget-name = "AEC"; }; plugin-info-6 { plugin-name = "wire"; firmware-name = "libnvwirefx.elf"; widget-name = "WIRE"; }; }; }; tegra_sound: sound { status = "disabled"; nvidia,num-codec-link = <12>; nvidia,num-clk = <8>; nvidia,clk-rates = < 270950400 11289600 45158400 45158400 245760000 12288000 49152000 49152000 >; nvidia,xbar = <&tegra_axbar>; nvidia,audio-routing = "x Headphone", "x OUT", "x IN", "x Mic", "y Headphone", "y OUT", "y IN", "y Mic", "z Headphone", "z OUT", "z IN", "z Mic", "m Headphone", "m OUT", "m IN", "m Mic", "n Headphone", "n OUT", "n IN", "n Mic", "o Headphone", "o OUT", "o IN", "o Mic", "a IN", "a Mic", "b IN", "b Mic", "c IN", "c Mic", "d IN", "d Mic", "d1 Headphone", "d1 OUT", "d2 Headphone", "d2 OUT"; nvidia,dai-link-1 { link-name = "spdif-dit-0"; cpu-dai = <&tegra_i2s1>; codec-dai = <&spdif_dit0>; cpu-dai-name = "I2S1"; codec-dai-name = "dit-hifi"; format = "i2s"; bit-format = "s16_le"; srate = <48000>; num-channel = <2>; ignore_suspend; name-prefix = "x"; status = "okay"; }; nvidia,dai-link-2 { link-name = "spdif-dit-1"; cpu-dai = <&tegra_i2s2>; codec-dai = <&spdif_dit1>; cpu-dai-name = "I2S2"; codec-dai-name = "dit-hifi"; format = "i2s"; bit-format = "s16_le"; srate = <48000>; num-channel = <2>; ignore_suspend; name-prefix = "y"; status = "okay"; }; nvidia,dai-link-3 { link-name = "spdif-dit-2"; cpu-dai = <&tegra_i2s3>; codec-dai = <&spdif_dit2>; cpu-dai-name = "I2S3"; codec-dai-name = "dit-hifi"; format = "i2s"; bit-format = "s16_le"; srate = <48000>; num-channel = <2>; ignore_suspend; name-prefix = "z"; status = "okay"; }; nvidia,dai-link-4 { link-name = "spdif-dit-3"; cpu-dai = <&tegra_i2s4>; codec-dai = <&spdif_dit3>; cpu-dai-name = "I2S4"; codec-dai-name = "dit-hifi"; format = "i2s"; bit-format = "s16_le"; srate = <48000>; num-channel = <2>; ignore_suspend; name-prefix = "m"; status = "okay"; }; nvidia,dai-link-5 { link-name = "spdif-dit-4"; cpu-dai = <&tegra_i2s5>; codec-dai = <&spdif_dit4>; cpu-dai-name = "I2S5"; codec-dai-name = "dit-hifi"; format = "i2s"; bit-format = "s16_le"; srate = <48000>; num-channel = <2>; ignore_suspend; name-prefix = "n"; status = "okay"; }; nvidia,dai-link-6 { link-name = "spdif-dit-6"; cpu-dai = <&tegra_i2s6>; codec-dai = <&spdif_dit6>; cpu-dai-name = "I2S6"; codec-dai-name = "dit-hifi"; format = "i2s"; bit-format = "s16_le"; srate = <8000>; num-channel = <1>; ignore_suspend; name-prefix = "o"; status = "okay"; }; nvidia,dai-link-7 { link-name = "spdif-dit-7"; cpu-dai = <&tegra_dmic1>; codec-dai = <&spdif_dit7>; cpu-dai-name = "DMIC1"; codec-dai-name = "dit-hifi"; format = "i2s"; bit-format = "s16_le"; srate = <48000>; ignore_suspend; num-channel = <2>; name-prefix = "a"; status = "okay"; }; nvidia,dai-link-8 { link-name = "spdif-dit-8"; cpu-dai = <&tegra_dmic2>; codec-dai = <&spdif_dit8>; cpu-dai-name = "DMIC2"; codec-dai-name = "dit-hifi"; format = "i2s"; bit-format = "s16_le"; srate = <48000>; ignore_suspend; num-channel = <2>; name-prefix = "b"; status = "okay"; }; nvidia,dai-link-9 { link-name = "spdif-dit-9"; cpu-dai = <&tegra_dmic3>; codec-dai = <&spdif_dit9>; cpu-dai-name = "DMIC3"; codec-dai-name = "dit-hifi"; format = "i2s"; bit-format = "s16_le"; srate = <48000>; ignore_suspend; num-channel = <2>; name-prefix = "c"; status = "okay"; }; nvidia,dai-link-10 { link-name = "spdif-dit-10"; cpu-dai = <&tegra_dmic4>; codec-dai = <&spdif_dit10>; cpu-dai-name = "DMIC4"; codec-dai-name = "dit-hifi"; format = "i2s"; bit-format = "s16_le"; srate = <48000>; ignore_suspend; num-channel = <2>; name-prefix = "d"; status = "okay"; }; nvidia,dai-link-11 { link-name = "dspk1-playback"; cpu-dai = <&tegra_dspk1>; codec-dai = <&spdif_dit11>; cpu-dai-name = "DSPK1"; codec-dai-name = "dit-hifi"; format = "i2s"; bit-format = "s16_le"; srate = <48000>; num-channel = <2>; ignore_suspend; name-prefix = "d1"; status = "okay"; }; nvidia,dai-link-12 { link-name = "dspk2-playback"; cpu-dai = <&tegra_dspk2>; codec-dai = <&spdif_dit12>; cpu-dai-name = "DSPK2"; codec-dai-name = "dit-hifi"; format = "i2s"; bit-format = "s16_le"; srate = <48000>; num-channel = <2>; ignore_suspend; name-prefix = "d2"; status = "okay"; }; }; }; # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-audio-p2822-0000.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-include/dt-bindings/audio/tegra194-audio.h" 1 # 19 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-audio-p2822-0000.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/tegra/kernel-include/dt-bindings/sound/rt5659.h" 1 # 20 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-audio-p2822-0000.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/tegra/common/kernel-dts/audio/tegra-platforms-audio-dmic3-5-switch.dtsi" 1 # 16 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/tegra/common/kernel-dts/audio/tegra-platforms-audio-dmic3-5-switch.dtsi" &tegra_pinctrl { dmic3_dap_active_state: dmic3_dap_active { dmic3_dat { nvidia,pins = "can1_stb_pbb0"; nvidia,function = "dmic3"; nvidia,tristate = <1>; nvidia,enable-input = <1>; nvidia,pull = <1>; }; dmic3_clk { nvidia,pins = "can1_en_pbb1"; nvidia,function = "dmic3"; nvidia,tristate = <0>; nvidia,enable-input = <0>; nvidia,pull = <0>; }; }; dmic3_dap_inactive_state: dmic3_dap_inactive { dmic5_dat { nvidia,pins = "can1_stb_pbb0"; nvidia,function = "dmic5"; nvidia,tristate = <1>; nvidia,enable-input = <1>; nvidia,pull = <1>; }; dmic5_clk { nvidia,pins = "can1_en_pbb1"; nvidia,function = "dmic5"; nvidia,tristate = <0>; nvidia,enable-input = <0>; nvidia,pull = <0>; }; }; }; &tegra_dmic3 { pinctrl-names = "dap_active", "dap_inactive"; pinctrl-0 = <&dmic3_dap_active_state>; pinctrl-1 = <&dmic3_dap_inactive_state>; }; # 21 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-audio-p2822-0000.dtsi" 2 / { aconnect@2a41000 { status = "okay"; agic-controller@2a41000 { status = "okay"; }; adsp@2993000 { status = "okay"; }; }; i2c@c250000 { rt5658: rt5659.7-001a@1a { compatible = "realtek,rt5658"; reg = <0x1a>; realtek,jd-src = <0>; realtek,dmic1-data-pin = <0>; realtek,dmic2-data-pin = <0>; gpios = <&tegra_main_gpio ((18 * 8) + 5) 0>; status = "okay"; }; }; aconnect@2a41000 { ahub { i2s@2901300 { fsync-width = <0>; bclk-ratio = <4>; }; }; }; hda@3510000 { status = "okay"; }; tegra_sound: sound { status = "okay"; compatible = "nvidia,tegra-audio-t186ref-mobile-rt565x"; nvidia,model = "tegra-snd-t19x-mobile-rt565x"; clocks = <&bpmp_clks 93U>, <&bpmp_clks 104U>, <&bpmp_clks 7U>; clock-names = "pll_a", "pll_a_out0", "extern1"; assigned-clocks = <&bpmp_clks 104U>, <&bpmp_clks 7U>; assigned-clock-parents = <&bpmp_clks 93U>, <&bpmp_clks 104U>; nvidia,audio-routing = "x Headphone Jack", "x HPO L Playback", "x Headphone Jack", "x HPO R Playback", "x Headphone Jack", "x LOUTL", "x Headphone Jack", "x LOUTR", "x IN1P", "x Mic Jack", "x IN2P", "x Mic Jack", "x Int Spk", "x SPO Playback", "x DMIC L1", "x Int Mic", "x DMIC L2", "x Int Mic", "x DMIC R1", "x Int Mic", "x DMIC R2", "x Int Mic", "y Headphone", "y OUT", "y IN", "y Mic", "z Headphone", "z OUT", "z IN", "z Mic", "m Headphone", "m OUT", "m IN", "m Mic", "n Headphone", "n OUT", "n IN", "n Mic", "o Headphone", "o OUT", "o IN", "o Mic", "a IN", "a Mic", "b IN", "b Mic", "c IN", "c Mic", "d IN", "d Mic", "d1 Headphone", "d1 OUT", "d2 Headphone", "d2 OUT"; mclk-fs = <256>; # 121 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-audio-p2822-0000.dtsi" nvidia,dai-link-1 { link-name = "rt565x-playback"; codec-dai = <&rt5658>; codec-dai-name = "rt5659-aif1"; }; hdr40_snd_link_i2s: nvidia,dai-link-2 { }; nvidia,dai-link-4 { format = "dsp_a"; tx-mask = <0xFF>; rx-mask = <0xFF>; bitclock-inversion; srate = <8000>; num-channel = <1>; }; }; }; # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-a00.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-disp.dtsi" 1 # 24 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-disp.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/tegra/kernel-include/dt-bindings/display/tegra-panel.h" 1 # 25 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-disp.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-hdmi.dtsi" 1 # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-hdmi.dtsi" &sor0 { nvidia,hpd-gpio = <&tegra_main_gpio ((12 * 8) + 0) 0>; nvidia,ddc-i2c-bus = <&dp_aux_ch0_i2c>; }; &sor1 { nvidia,hpd-gpio = <&tegra_main_gpio ((12 * 8) + 1) 0>; nvidia,ddc-i2c-bus = <&dp_aux_ch1_i2c>; }; &sor2 { nvidia,hpd-gpio = <&tegra_main_gpio ((12 * 8) + 2) 0>; nvidia,ddc-i2c-bus = <&dp_aux_ch2_i2c>; }; &sor3 { nvidia,hpd-gpio = <&tegra_main_gpio ((12 * 8) + 3) 0>; nvidia,ddc-i2c-bus = <&dp_aux_ch3_i2c>; }; &sor0_hdmi_display { generic-infoframe-type = <0x87>; disp-default-out { nvidia,out-type = <1>; nvidia,out-hotplug-state = <0>; nvidia,out-parent-clk = "pll_d"; nvidia,out-xres = <4096>; nvidia,out-yres = <2160>; }; }; &sor1_hdmi_display { generic-infoframe-type = <0x87>; disp-default-out { nvidia,out-type = <1>; nvidia,out-hotplug-state = <0>; nvidia,out-parent-clk = "plld2"; nvidia,out-xres = <4096>; nvidia,out-yres = <2160>; }; }; &sor2_hdmi_display { generic-infoframe-type = <0x87>; disp-default-out { nvidia,out-type = <1>; nvidia,out-hotplug-state = <0>; nvidia,out-parent-clk = "plld3"; nvidia,out-xres = <4096>; nvidia,out-yres = <2160>; }; }; &sor3_hdmi_display { generic-infoframe-type = <0x87>; disp-default-out { nvidia,out-type = <1>; nvidia,out-hotplug-state = <0>; nvidia,out-parent-clk = "plld4"; nvidia,out-xres = <4096>; nvidia,out-yres = <2160>; }; }; # 26 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-disp.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-dp.dtsi" 1 # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-dp.dtsi" &sor0_dp_display { nvidia,is_ext_dp_panel = <1>; nvidia,pc2-disabled; disp-default-out { nvidia,out-type = <3>; nvidia,out-hotplug-state = <0>; nvidia,out-parent-clk = "pll_d"; nvidia,out-xres = <4096>; nvidia,out-yres = <2160>; }; lt-data { tegra-dp-vs-regs { pc2_l0 = < 0x15 0x1c 0x23 0x2d 0x20 0x27 0x2f 0x2c 0x36 0x3c >; pc2_l1 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l2 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l3 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; }; tegra-dp-pe-regs { pc2_l0 = < 0x00 0x0b 0x18 0x2d 0x00 0x0f 0x20 0x01 0x18 0x00 >; pc2_l1 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l2 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l3 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; }; tegra-dp-pc-regs { pc2_l0 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l1 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l2 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l3 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; }; tegra-dp-tx-pu { pc2_l0 = < 0x20 0x30 0x40 0x60 0x30 0x40 0x60 0x40 0x60 0x60 >; pc2_l1 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l2 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l3 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; }; }; }; &sor1_dp_display { nvidia,is_ext_dp_panel = <1>; nvidia,pc2-disabled; disp-default-out { nvidia,out-type = <3>; nvidia,out-hotplug-state = <0>; nvidia,out-parent-clk = "plld2"; nvidia,out-xres = <4096>; nvidia,out-yres = <2160>; }; lt-data { tegra-dp-vs-regs { pc2_l0 = < 0x15 0x1c 0x23 0x2d 0x20 0x27 0x2f 0x2c 0x36 0x3c >; pc2_l1 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l2 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l3 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; }; tegra-dp-pe-regs { pc2_l0 = < 0x00 0x0b 0x18 0x2d 0x00 0x0f 0x20 0x01 0x18 0x00 >; pc2_l1 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l2 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l3 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; }; tegra-dp-pc-regs { pc2_l0 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l1 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l2 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l3 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; }; tegra-dp-tx-pu { pc2_l0 = < 0x20 0x30 0x40 0x60 0x30 0x40 0x60 0x40 0x60 0x60 >; pc2_l1 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l2 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l3 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; }; }; }; &sor2_dp_display { nvidia,is_ext_dp_panel = <1>; nvidia,pc2-disabled; disp-default-out { nvidia,out-type = <3>; nvidia,out-hotplug-state = <0>; nvidia,out-parent-clk = "plld3"; nvidia,out-xres = <4096>; nvidia,out-yres = <2160>; }; lt-data { tegra-dp-vs-regs { pc2_l0 = < 0x15 0x1c 0x23 0x2d 0x20 0x27 0x2f 0x2c 0x36 0x3c >; pc2_l1 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l2 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l3 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; }; tegra-dp-pe-regs { pc2_l0 = < 0x00 0x0b 0x18 0x2d 0x00 0x0f 0x20 0x01 0x18 0x00 >; pc2_l1 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l2 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l3 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; }; tegra-dp-pc-regs { pc2_l0 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l1 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l2 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l3 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; }; tegra-dp-tx-pu { pc2_l0 = < 0x20 0x30 0x40 0x60 0x30 0x40 0x60 0x40 0x60 0x60 >; pc2_l1 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l2 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l3 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; }; }; }; &sor3_dp_display { nvidia,is_ext_dp_panel = <1>; nvidia,pc2-disabled; disp-default-out { nvidia,out-type = <3>; nvidia,out-hotplug-state = <0>; nvidia,out-parent-clk = "plld4"; nvidia,out-xres = <4096>; nvidia,out-yres = <2160>; }; lt-data { tegra-dp-vs-regs { pc2_l0 = < 0x15 0x1c 0x23 0x2d 0x20 0x27 0x2f 0x2c 0x36 0x3c >; pc2_l1 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l2 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l3 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; }; tegra-dp-pe-regs { pc2_l0 = < 0x00 0x0b 0x18 0x2d 0x00 0x0f 0x20 0x01 0x18 0x00 >; pc2_l1 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l2 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l3 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; }; tegra-dp-pc-regs { pc2_l0 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l1 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l2 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l3 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; }; tegra-dp-tx-pu { pc2_l0 = < 0x20 0x30 0x40 0x60 0x30 0x40 0x60 0x40 0x60 0x60 >; pc2_l1 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l2 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; pc2_l3 = < 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 >; }; }; }; # 27 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-disp.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-fixed-regulator-p2822-1000.dtsi" 1 # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-fixed-regulator-p2822-1000.dtsi" / { fixed-regulators { hdr40_vdd_3v3: p2822_vdd_3v3_cvb: regulator@101 { compatible = "regulator-fixed"; reg = <101>; regulator-name = "vdd-3v3-cvb"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; p2822_vdd_1v8_cvb: regulator@102 { compatible = "regulator-fixed"; reg = <102>; regulator-name = "vdd-1v8-cvb"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; p2822_vdd_1v8_sd: regulator@104 { compatible = "regulator-fixed"; reg = <104>; regulator-name = "vdd-1v8-sd"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; gpio = <&tegra_main_gpio ((0 * 8) + 0) 0>; enable-active-high; }; p2822_vdd_epb_1v0: regulator@105 { compatible = "regulator-fixed"; reg = <105>; regulator-name = "vdd-epb-1v0"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; vin-supply = <&p2822_vdd_3v3_cvb>; }; p2822_vdd_sdmmc1_sw: regulator@106 { compatible = "regulator-fixed"; reg = <106>; regulator-name = "vdd-sdmmc1-sw"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&tegra_main_gpio ((0 * 8) + 0) 0>; enable-active-high; }; p2822_avdd_cam_2v8: regulator@107 { compatible = "regulator-fixed"; reg = <107>; regulator-name = "avdd-cam-2v8"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; p2822_vdd_sata_1v5: regulator@108 { compatible = "regulator-fixed"; reg = <108>; regulator-name = "vdd-sata-1v5"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; }; p2822_vdd_1v8_slt: regulator@109 { compatible = "regulator-fixed"; reg = <109>; regulator-name = "vdd-1v8-slt"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; p2822_vdd_3v3_slt: regulator@110 { compatible = "regulator-fixed"; reg = <110>; regulator-name = "vdd-3v3-slt"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; p2822_vdd_fan: regulator@111 { compatible = "regulator-fixed"; reg = <111>; regulator-name = "vdd-fan"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; p2822_vdd_hdmi_5v0: regulator@112 { compatible = "regulator-fixed"; reg = <112>; regulator-name = "vdd-hdmi-5v0"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&tegra_main_gpio ((0 * 8) + 3) 0>; enable-active-high; }; # 142 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-fixed-regulator-p2822-1000.dtsi" p2822_vdd_5v_sata: regulator@114 { compatible = "regulator-fixed"; reg = <114>; regulator-name = "vdd-5v-sata"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; vin-supply = <&battery_reg>; }; p2822_vdd_3v3_pcie: regulator@115 { compatible = "regulator-fixed"; reg = <115>; regulator-name = "vdd-3v3-pcie"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&tegra_main_gpio ((25 * 8) + 2) 0>; regulator-boot-on; enable-active-high; }; p2822_vdd_12v_pcie: regulator@116 { compatible = "regulator-fixed"; reg = <116>; regulator-name = "vdd-12v-pcie"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; gpio = <&tegra_main_gpio ((0 * 8) + 1) 1>; regulator-boot-on; enable-active-low; }; }; }; # 28 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-disp.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-spmic-p2888-0001.dtsi" 1 # 15 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-spmic-p2888-0001.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/tegra/kernel-include/dt-bindings/mfd/max77620.h" 1 # 16 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-spmic-p2888-0001.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/tegra/kernel-include/dt-bindings/regulator/regulator.h" 1 # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-spmic-p2888-0001.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/tegra/kernel-include/dt-bindings/thermal/thermal.h" 1 # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-spmic-p2888-0001.dtsi" 2 / { aliases { rtc0 = &p2888_spmic; rtc1 = &tegra_rtc; }; bpmp_i2c { p2888_spmic: spmic@3c { compatible = "maxim,max20024"; reg = <0x3c>; interrupt-parent = <&tegra_pm_irq>; interrupts = <0 209 0x00000000>; #interrupt-cells = <2>; interrupt-controller; gpio-controller; #gpio-cells = <2>; enable-clock32k-out; system-pmic-power-off; avoid-power-off-commands; hot-die-threshold-temp = <110000>; #thermal-sensor-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&spmic_default>; spmic_default: pinmux@0 { pin_gpio0 { pins = "gpio0"; function = "gpio"; }; pin_gpio1 { pins = "gpio1"; function = "fps-out"; active-fps-source = <4>; }; pin_gpio2 { pins = "gpio2"; function = "fps-out"; active-fps-source = <4>; }; pin_gpio3 { pins = "gpio3"; function = "fps-out"; active-fps-source = <4>; }; pin_gpio4 { pins = "gpio4"; function = "32k-out1"; drive-push-pull = <1>; }; pin_gpio6 { pins = "gpio6"; function = "gpio"; drive-push-pull = <1>; }; pin_gpio7 { pins = "gpio7"; function = "gpio"; drive-push-pull = <0>; }; }; gpio_default { gpio-hog; output-high; gpios = <6 0 7 0>; label = "spmic-gpio6", "spmic-gpio7"; }; p2888_spmic_wdt: watchdog { wdt-boot-timeout = <32>; wdt-suspend-timeout = <120>; status = "disabled"; }; fps { #address-cells = <1>; #size-cells = <0>; fps0 { reg = <0>; fps-event-source = <0>; }; fps1 { reg = <1>; fps-event-source = <1>; device-state-on-disabled-event = <0>; }; fps2 { reg = <2>; fps-event-source = <0>; }; }; backup-battery { backup-battery-charging-current = <100>; backup-battery-charging-voltage = <3000000>; backup-battery-output-resister = <100>; status = "disabled"; }; regulators { in-ldo7-8-supply = <&p2888_spmic_sd2>; p2888_spmic_sd0: sd0 { regulator-name = "vdd-1v0"; regulator-always-on; regulator-boot-on; regulator-init-mode = <0x2>; active-fps-source = <4>; }; p2888_spmic_sd1: sd1 { regulator-name = "vdd-1v8-hs"; regulator-always-on; regulator-boot-on; regulator-init-mode = <0x2>; active-fps-source = <4>; }; p2888_spmic_sd2: sd2 { regulator-name = "vdd-1v8-ls"; regulator-always-on; regulator-boot-on; regulator-init-mode = <0x2>; active-fps-source = <4>; }; p2888_spmic_sd3: sd3 { regulator-name = "vdd-1v8-ao"; regulator-always-on; regulator-boot-on; regulator-init-mode = <0x2>; active-fps-source = <4>; }; p2888_spmic_sd4: sd4 { regulator-name = "vddio-ddr-1v1"; regulator-always-on; regulator-boot-on; regulator-init-mode = <0x2>; active-fps-source = <4>; }; p2888_spmic_ldo0: ldo0 { regulator-name = "vdd-rtc"; regulator-always-on; regulator-boot-on; active-fps-source = <4>; }; p2888_spmic_ldo1: ldo1 { regulator-name = "spmic-ldo1"; active-fps-source = <4>; }; p2888_spmic_ldo2: ldo2 { regulator-name = "vdd-ao-3v3"; regulator-always-on; regulator-boot-on; active-fps-source = <4>; }; p2888_spmic_ldo3: ldo3 { regulator-name = "vddio-emmc-3v3"; regulator-always-on; regulator-boot-on; active-fps-source = <4>; }; p2888_spmic_ldo4: ldo4 { regulator-name = "spmic-ldo4"; active-fps-source = <4>; }; p2888_spmic_ldo5: ldo5 { regulator-name = "vdd-usb-3v3"; regulator-always-on; regulator-boot-on; active-fps-source = <4>; }; p2888_spmic_ldo6: ldo6 { regulator-name = "vddio-sdmmc1-3v3"; regulator-always-on; regulator-boot-on; active-fps-source = <4>; }; p2888_spmic_ldo7: ldo7 { regulator-name = "vdd-csi-1v2"; regulator-always-on; regulator-boot-on; active-fps-source = <4>; }; p2888_spmic_ldo8: ldo8 { regulator-name = "spmic-ldo8"; active-fps-source = <4>; }; }; }; }; dummy_cool_dev: dummy-cool-dev { compatible = "dummy-cooling-dev"; #cooling-cells = <2>; status = "disabled"; }; thermal-zones { PMIC-Die { polling-delay = <0>; polling-delay-passive = <0>; thermal-sensors = <&p2888_spmic>; trips { die_temp_thresh: hot-die { temperature = <120000>; type = "active"; hysteresis = <0>; }; }; cooling-maps { map0 { trip = <&die_temp_thresh>; cooling-device = <&{/bthrot_cdev/emergency_balanced} 0xffffffff 0xffffffff>; contribution = <100>; cdev-type = "emergency-balanced"; }; }; }; }; }; # 29 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-disp.dtsi" 2 &head0 { status = "okay"; nvidia,fb-bpp = <32>; nvidia,fbmem-size = <265420800>; nvidia,fb-flags = <(1 << 0)>; win-mask = <0x3>; nvidia,fb-win = <0>; nvidia,dc-connector = <&sor2>; nvidia,dc-flags = <(1 << 0)>; avdd_hdmi-supply = <&p2888_spmic_sd0>; avdd_hdmi_pll-supply = <&p2888_spmic_sd1>; vdd_hdmi_5v0-supply = <&p2822_vdd_hdmi_5v0>; }; &head1 { status = "okay"; nvidia,fb-bpp = <32>; nvidia,fbmem-size = <265420800>; nvidia,fb-flags = <(1 << 0)>; win-mask = <0xC>; nvidia,fb-win = <2>; nvidia,dc-connector = <&sor0>; nvidia,dc-flags = <(1 << 0)>; vdd-dp-pwr-supply = <&p2888_spmic_sd0>; avdd-dp-pll-supply = <&p2888_spmic_sd1>; vdd-edp-sec-mode-supply = <&battery_reg>; vdd-dp-pad-supply = <&battery_reg>; vdd_hdmi_5v0-supply = <&p2822_vdd_hdmi_5v0>; }; &head2 { status = "okay"; nvidia,fb-bpp = <32>; nvidia,fbmem-size = <265420800>; nvidia,fb-flags = <(1 << 0)>; win-mask = <0x30>; nvidia,fb-win = <4>; nvidia,dc-connector = <&sor1>; nvidia,dc-flags = <(1 << 0)>; vdd-dp-pwr-supply = <&p2888_spmic_sd0>; avdd-dp-pll-supply = <&p2888_spmic_sd1>; vdd-edp-sec-mode-supply = <&battery_reg>; vdd-dp-pad-supply = <&battery_reg>; vdd_hdmi_5v0-supply = <&p2822_vdd_hdmi_5v0>; }; &sor0 { status = "okay"; nvidia,active-panel = <&sor0_dp_display>; }; &sor0_dp_display { status = "okay"; nvidia,is_ext_dp_panel = <1>; }; &sor1 { status = "okay"; nvidia,active-panel = <&sor1_dp_display>; }; &sor1_dp_display { status = "okay"; nvidia,is_ext_dp_panel = <1>; }; &sor2 { status = "okay"; nvidia,active-panel = <&sor2_hdmi_display>; }; &sor2_hdmi_display { status = "okay"; disp-default-out { nvidia,out-flags = <(1 << 1)>; }; }; &dpaux0 { status = "okay"; }; &dpaux1 { status = "okay"; }; &dpaux2 { status = "okay"; }; &tegra_cec { status = "okay"; }; # 19 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-a00.dtsi" 2 / { sdhci@3400000 { mmc-ocr-mask = <0x0>; cd-gpios = <&tegra_main_gpio ((6 * 8) + 7) 0>; nvidia,cd-wakeup-capable; nvidia,vmmc-always-on; status = "okay"; }; gpio-keys { compatible = "gpio-keys"; gpio-keys,name = "gpio-keys"; forcerecovery { label = "force-recovery"; gpios = <&tegra_main_gpio ((6 * 8) + 0) 1>; linux,code = <0x101>; }; power_key { label = "power-key"; gpios = <&tegra_aon_gpio ((4 * 8) + 4) 1>; linux,code = <116>; gpio-key,wakeup; }; }; gpio-leds { compatible = "gpio-leds"; status = "okay"; led-standby{ label = "led-standby"; linux,default-trigger = "none"; gpios = <&tegra_main_gpio ((12 * 8) + 5) 0>; }; led-poweron { label = "led-poweron"; linux,default-trigger = "none"; gpios = <&tegra_main_gpio ((13 * 8) + 0) 0>; default-state = "on"; }; audio-on { label = "audio-on"; linux,default-trigger = "none"; gpios = <&tegra_main_gpio ((25 * 8) + 1) 0>; default-state = "on"; }; }; }; # 21 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0001-p2822-0000-common.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-power-tree-p2888-0001-p2822-1000.dtsi" 1 # 15 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-power-tree-p2888-0001-p2822-1000.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-spmic-p2888-0001.dtsi" 1 # 20 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-spmic-p2888-0001.dtsi" / { aliases { rtc0 = &p2888_spmic; rtc1 = &tegra_rtc; }; bpmp_i2c { p2888_spmic: spmic@3c { compatible = "maxim,max20024"; reg = <0x3c>; interrupt-parent = <&tegra_pm_irq>; interrupts = <0 209 0x00000000>; #interrupt-cells = <2>; interrupt-controller; gpio-controller; #gpio-cells = <2>; enable-clock32k-out; system-pmic-power-off; avoid-power-off-commands; hot-die-threshold-temp = <110000>; #thermal-sensor-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&spmic_default>; spmic_default: pinmux@0 { pin_gpio0 { pins = "gpio0"; function = "gpio"; }; pin_gpio1 { pins = "gpio1"; function = "fps-out"; active-fps-source = <4>; }; pin_gpio2 { pins = "gpio2"; function = "fps-out"; active-fps-source = <4>; }; pin_gpio3 { pins = "gpio3"; function = "fps-out"; active-fps-source = <4>; }; pin_gpio4 { pins = "gpio4"; function = "32k-out1"; drive-push-pull = <1>; }; pin_gpio6 { pins = "gpio6"; function = "gpio"; drive-push-pull = <1>; }; pin_gpio7 { pins = "gpio7"; function = "gpio"; drive-push-pull = <0>; }; }; gpio_default { gpio-hog; output-high; gpios = <6 0 7 0>; label = "spmic-gpio6", "spmic-gpio7"; }; p2888_spmic_wdt: watchdog { wdt-boot-timeout = <32>; wdt-suspend-timeout = <120>; status = "disabled"; }; fps { #address-cells = <1>; #size-cells = <0>; fps0 { reg = <0>; fps-event-source = <0>; }; fps1 { reg = <1>; fps-event-source = <1>; device-state-on-disabled-event = <0>; }; fps2 { reg = <2>; fps-event-source = <0>; }; }; backup-battery { backup-battery-charging-current = <100>; backup-battery-charging-voltage = <3000000>; backup-battery-output-resister = <100>; status = "disabled"; }; regulators { in-ldo7-8-supply = <&p2888_spmic_sd2>; p2888_spmic_sd0: sd0 { regulator-name = "vdd-1v0"; regulator-always-on; regulator-boot-on; regulator-init-mode = <0x2>; active-fps-source = <4>; }; p2888_spmic_sd1: sd1 { regulator-name = "vdd-1v8-hs"; regulator-always-on; regulator-boot-on; regulator-init-mode = <0x2>; active-fps-source = <4>; }; p2888_spmic_sd2: sd2 { regulator-name = "vdd-1v8-ls"; regulator-always-on; regulator-boot-on; regulator-init-mode = <0x2>; active-fps-source = <4>; }; p2888_spmic_sd3: sd3 { regulator-name = "vdd-1v8-ao"; regulator-always-on; regulator-boot-on; regulator-init-mode = <0x2>; active-fps-source = <4>; }; p2888_spmic_sd4: sd4 { regulator-name = "vddio-ddr-1v1"; regulator-always-on; regulator-boot-on; regulator-init-mode = <0x2>; active-fps-source = <4>; }; p2888_spmic_ldo0: ldo0 { regulator-name = "vdd-rtc"; regulator-always-on; regulator-boot-on; active-fps-source = <4>; }; p2888_spmic_ldo1: ldo1 { regulator-name = "spmic-ldo1"; active-fps-source = <4>; }; p2888_spmic_ldo2: ldo2 { regulator-name = "vdd-ao-3v3"; regulator-always-on; regulator-boot-on; active-fps-source = <4>; }; p2888_spmic_ldo3: ldo3 { regulator-name = "vddio-emmc-3v3"; regulator-always-on; regulator-boot-on; active-fps-source = <4>; }; p2888_spmic_ldo4: ldo4 { regulator-name = "spmic-ldo4"; active-fps-source = <4>; }; p2888_spmic_ldo5: ldo5 { regulator-name = "vdd-usb-3v3"; regulator-always-on; regulator-boot-on; active-fps-source = <4>; }; p2888_spmic_ldo6: ldo6 { regulator-name = "vddio-sdmmc1-3v3"; regulator-always-on; regulator-boot-on; active-fps-source = <4>; }; p2888_spmic_ldo7: ldo7 { regulator-name = "vdd-csi-1v2"; regulator-always-on; regulator-boot-on; active-fps-source = <4>; }; p2888_spmic_ldo8: ldo8 { regulator-name = "spmic-ldo8"; active-fps-source = <4>; }; }; }; }; dummy_cool_dev: dummy-cool-dev { compatible = "dummy-cooling-dev"; #cooling-cells = <2>; status = "disabled"; }; thermal-zones { PMIC-Die { polling-delay = <0>; polling-delay-passive = <0>; thermal-sensors = <&p2888_spmic>; trips { die_temp_thresh: hot-die { temperature = <120000>; type = "active"; hysteresis = <0>; }; }; cooling-maps { map0 { trip = <&die_temp_thresh>; cooling-device = <&{/bthrot_cdev/emergency_balanced} 0xffffffff 0xffffffff>; contribution = <100>; cdev-type = "emergency-balanced"; }; }; }; }; }; # 16 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-power-tree-p2888-0001-p2822-1000.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-fixed-regulator-p2888-0001.dtsi" 1 # 15 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-fixed-regulator-p2888-0001.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-platforms-simple-bus.dtsi" 1 # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-platforms-simple-bus.dtsi" / { fixed-regulators { compatible = "simple-bus"; device_type = "fixed-regulators"; #address-cells = <1>; #size-cells = <0>; }; external-connection { compatible = "simple-bus"; device_type = "external-connection"; #address-cells = <1>; #size-cells = <0>; }; }; # 16 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-fixed-regulator-p2888-0001.dtsi" 2 / { fixed-regulators { hdr40_vdd_5v0: battery_reg: regulator@0 { compatible = "regulator-fixed"; reg = <0>; regulator-name = "vdd-ac-bat"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-always-on; }; }; }; # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-power-tree-p2888-0001-p2822-1000.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-fixed-regulator-p2822-1000.dtsi" 1 # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-fixed-regulator-p2822-1000.dtsi" / { fixed-regulators { hdr40_vdd_3v3: p2822_vdd_3v3_cvb: regulator@101 { compatible = "regulator-fixed"; reg = <101>; regulator-name = "vdd-3v3-cvb"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; p2822_vdd_1v8_cvb: regulator@102 { compatible = "regulator-fixed"; reg = <102>; regulator-name = "vdd-1v8-cvb"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; p2822_vdd_1v8_sd: regulator@104 { compatible = "regulator-fixed"; reg = <104>; regulator-name = "vdd-1v8-sd"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; gpio = <&tegra_main_gpio ((0 * 8) + 0) 0>; enable-active-high; }; p2822_vdd_epb_1v0: regulator@105 { compatible = "regulator-fixed"; reg = <105>; regulator-name = "vdd-epb-1v0"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; vin-supply = <&p2822_vdd_3v3_cvb>; }; p2822_vdd_sdmmc1_sw: regulator@106 { compatible = "regulator-fixed"; reg = <106>; regulator-name = "vdd-sdmmc1-sw"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&tegra_main_gpio ((0 * 8) + 0) 0>; enable-active-high; }; p2822_avdd_cam_2v8: regulator@107 { compatible = "regulator-fixed"; reg = <107>; regulator-name = "avdd-cam-2v8"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; p2822_vdd_sata_1v5: regulator@108 { compatible = "regulator-fixed"; reg = <108>; regulator-name = "vdd-sata-1v5"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; }; p2822_vdd_1v8_slt: regulator@109 { compatible = "regulator-fixed"; reg = <109>; regulator-name = "vdd-1v8-slt"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; p2822_vdd_3v3_slt: regulator@110 { compatible = "regulator-fixed"; reg = <110>; regulator-name = "vdd-3v3-slt"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; p2822_vdd_fan: regulator@111 { compatible = "regulator-fixed"; reg = <111>; regulator-name = "vdd-fan"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; p2822_vdd_hdmi_5v0: regulator@112 { compatible = "regulator-fixed"; reg = <112>; regulator-name = "vdd-hdmi-5v0"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&tegra_main_gpio ((0 * 8) + 3) 0>; enable-active-high; }; # 142 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-fixed-regulator-p2822-1000.dtsi" p2822_vdd_5v_sata: regulator@114 { compatible = "regulator-fixed"; reg = <114>; regulator-name = "vdd-5v-sata"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; vin-supply = <&battery_reg>; }; p2822_vdd_3v3_pcie: regulator@115 { compatible = "regulator-fixed"; reg = <115>; regulator-name = "vdd-3v3-pcie"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&tegra_main_gpio ((25 * 8) + 2) 0>; regulator-boot-on; enable-active-high; }; p2822_vdd_12v_pcie: regulator@116 { compatible = "regulator-fixed"; reg = <116>; regulator-name = "vdd-12v-pcie"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; gpio = <&tegra_main_gpio ((0 * 8) + 1) 1>; regulator-boot-on; enable-active-low; }; }; }; # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-power-tree-p2888-0001-p2822-1000.dtsi" 2 / { sdhci@3460000 { vmmc-supply = <&p2888_spmic_ldo3>; vqmmc-supply = <&p2888_spmic_sd2>; }; sdhci@3400000 { vmmc-supply = <&p2822_vdd_sdmmc1_sw>; }; ufshci@2450000 { vcc-supply = <&p2822_vdd_sdmmc1_sw>; vccq-supply = <&p2888_spmic_ldo7>; vccq2-supply = <&p2888_spmic_sd2>; }; ether_qos@2490000 { vddio_sys_enet_bias-supply = <&battery_reg>; vddio_enet-supply = <&battery_reg>; phy_vdd_1v8-supply = <&p2888_spmic_sd2>; phy_ovdd_rgmii-supply = <&p2888_spmic_sd2>; phy_pllvdd-supply = <&battery_reg>; }; xusb_padctl@3520000 { pex_dvdd-supply = <&p2888_spmic_sd0>; pex_hvdd-supply = <&p2888_spmic_sd1>; pex_pll_hvdd-supply = <&p2888_spmic_sd1>; vclamp_usb-supply = <&p2888_spmic_sd3>; avdd_usb-supply = <&p2888_spmic_ldo5>; avdd_pll_nvhs_eutmip-supply = <&p2888_spmic_sd1>; ports { usb2-0 { vbus-supply = <&battery_reg>; }; usb2-1 { vbus-supply = <&battery_reg>; }; usb2-2 { vbus-supply = <&battery_reg>; }; usb2-3 { vbus-supply = <&p2822_vdd_5v_sata>; }; }; }; xudc@3550000 { avdd-usb-supply = <&p2888_spmic_ldo5>; }; pcie@14180000 { vddio-pex-ctl-supply = <&p2888_spmic_sd3>; }; pcie@14100000 { vddio-pex-ctl-supply = <&p2888_spmic_sd3>; }; pcie@14140000 { vddio-pex-ctl-supply = <&p2888_spmic_sd3>; }; pcie@141a0000 { vddio-pex-ctl-supply = <&p2888_spmic_sd3>; vpcie3v3-supply = <&p2822_vdd_3v3_pcie>; vpcie12v-supply = <&p2822_vdd_12v_pcie>; }; pcie_ep@141a0000 { vddio-pex-ctl-supply = <&p2888_spmic_sd3>; }; pwm-fan { vdd-fan-supply = <&p2822_vdd_fan>; }; bpmp_i2c { spmic@3c { regulators { sd0 { regulator-enable-ramp-delay = <3960>; regulator-disable-ramp-delay = <660>; ramp-rate-setting = <27500>; regulator-ramp-delay = <1100>; }; sd1 { regulator-enable-ramp-delay = <3310>; regulator-disable-ramp-delay = <2000>; ramp-rate-setting = <27500>; regulator-ramp-delay = <550>; }; sd2 { regulator-enable-ramp-delay = <3310>; regulator-disable-ramp-delay = <1970>; ramp-rate-setting = <27500>; regulator-ramp-delay = <550>; }; sd3 { regulator-enable-ramp-delay = <2130>; regulator-disable-ramp-delay = <1970>; ramp-rate-setting = <27500>; regulator-ramp-delay = <350>; }; sd4 { regulator-enable-ramp-delay = <2650>; regulator-disable-ramp-delay = <1300>; ramp-rate-setting = <27500>; regulator-ramp-delay = <700>; }; ldo0 { regulator-enable-ramp-delay = <160>; regulator-disable-ramp-delay = <4480>; ramp-rate-setting = <100000>; regulator-ramp-delay = <200>; }; ldo1 { regulator-enable-ramp-delay = <2650>; regulator-disable-ramp-delay = <1300>; ramp-rate-setting = <100000>; regulator-ramp-delay = <1150>; }; ldo2 { regulator-enable-ramp-delay = <4670>; ramp-rate-setting = <100000>; regulator-ramp-delay = <1500>; }; ldo3 { regulator-enable-ramp-delay = <4670>; ramp-rate-setting = <100000>; regulator-ramp-delay = <1500>; }; ldo4 { regulator-enable-ramp-delay = <3310>; regulator-disable-ramp-delay = <1970>; ramp-rate-setting = <100000>; regulator-ramp-delay = <2200>; }; ldo5 { regulator-enable-ramp-delay = <4670>; ramp-rate-setting = <100000>; regulator-ramp-delay = <1500>; }; ldo6 { regulator-enable-ramp-delay = <4690>; ramp-rate-setting = <100000>; regulator-ramp-delay = <1500>; }; ldo7 { regulator-enable-ramp-delay = <3960>; regulator-disable-ramp-delay = <660>; ramp-rate-setting = <100000>; regulator-ramp-delay = <3350>; }; ldo8 { regulator-enable-ramp-delay = <3960>; regulator-disable-ramp-delay = <660>; ramp-rate-setting = <100000>; regulator-ramp-delay = <2250>; }; }; }; }; }; # 22 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0001-p2822-0000-common.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-comms.dtsi" 1 # 20 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-comms.dtsi" / { gpio@2200000 { wifi-enable { gpio-hog; output-high; gpios = <((6 * 8) + 3) 0>; label = "wifi-enable"; status = "okay"; }; }; bcmdhd_pcie_wlan { compatible = "android,bcmdhd_pcie_wlan"; wlan-pwr-gpio = <&tegra_main_gpio ((6 * 8) + 3) 0>; fw_path = "/vendor/firmware/fw_bcmdhd_4356.bin"; nv_path = "/vendor/firmware/nvram_4356.txt"; status = "okay"; }; }; # 23 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0001-p2822-0000-common.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-thermal-p2888.dtsi" 1 # 14 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-thermal-p2888.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-thermal.dtsi" 1 # 20 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-thermal.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-balanced-throttle.dtsi" 1 # 19 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-balanced-throttle.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/t19x/kernel-include/dt-bindings/thermal/nvidia,tegra-thermal-throttle.h" 1 # 20 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-balanced-throttle.dtsi" 2 /{ bthrot_cdev { compatible = "nvidia,tegra-thermal-throttle"; clocks = <&bpmp_clks 280U>, <&bpmp_clks 281U>, <&bpmp_clks 282U>, <&bpmp_clks 283U>, <&bpmp_clks 218U>; clock-names = "cpu0", "cpu1", "cpu2", "cpu3", "gpu"; skin_balanced { cdev-type = "skin-balanced"; #cooling-cells = <2>; nvidia,throttle-clocks = <0 200 0 1 400 0>; }; gpu_balanced { cdev-type = "gpu-balanced"; #cooling-cells = <2>; nvidia,cutoff = <1>; nvidia,throttle-clocks = <0 400 0 1 400 0>; }; cpu_balanced { cdev-type = "cpu-balanced"; #cooling-cells = <2>; nvidia,throttle-clocks = <0 200 0 1 300 365500000>; }; emergency_balanced { cdev-type = "emergency-balanced"; #cooling-cells = <2>; nvidia,throttle-clocks = <0 10 38400000 1 10 25500000>; }; aux_balanced { cdev-type = "aux-balanced"; #cooling-cells = <2>; nvidia,cutoff = <1>; nvidia,throttle-clocks = <0 400 0 1 400 0>; }; }; }; # 21 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-thermal.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-pwm-fan.dtsi" 1 # 14 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-pwm-fan.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/soc/tegra/kernel-include/dt-bindings/pwm/pwm.h" 1 # 15 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-pwm-fan.dtsi" 2 / { pwm_fan_shared_data: pfsd { num_resources = <0>; secret = <47>; active_steps = <10>; active_rpm = <0 1000 2000 3000 4000 5000 6000 7000 10000 11000>; rpm_diff_tolerance = <2>; active_rru = <40 2 1 1 1 1 1 1 1 1>; active_rrd = <40 2 1 1 1 1 1 1 1 1>; state_cap_lookup = <2 2 2 2 3 3 3 4 4 4>; pwm_period = <45334>; pwm_id = <4>; pwm_polarity = <(1 << 0)>; suspend_state = <1>; step_time = <100>; state_cap = <7>; active_pwm_max = <256>; tach_period = <1000>; pwm_gpio = <&tegra_aon_gpio ((2 * 8) + 4) 1>; }; pwm-fan { compatible = "pwm-fan"; status = "okay"; #pwm-cells = <1>; pwms = <&tegra_pwm4 0 45334>; shared_data = <&pwm_fan_shared_data>; profiles { default = "quiet"; quiet { state_cap = <4>; active_pwm = <0 77 120 160 255 255 255 255 255 255>; }; cool { state_cap = <4>; active_pwm = <0 77 120 160 255 255 255 255 255 255>; }; }; }; }; # 22 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-thermal.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-thermal-fan-est.dtsi" 1 # 14 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-thermal-fan-est.dtsi" / { thermal_fan_est_shared_data: tfesd { secret = <37>; toffset = <0>; polling_period = <1100>; ndevs = <3>; cdev_type = "pwm-fan"; tzp_governor_name = "pid_thermal_gov"; dev1 { dev_data = "CPU-therm"; coeffs = <30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; }; dev2 { dev_data = "GPU-therm"; coeffs = <30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; }; dev3 { dev_data = "AUX-therm"; coeffs = <40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; }; }; thermal-fan-est { compatible = "thermal-fan-est"; name = "thermal-fan-est"; status = "okay"; num_resources = <0>; shared_data = <&thermal_fan_est_shared_data>; trip_length = <10>; profiles { default = "quiet"; quiet { active_trip_temps = <0 50000 63000 72000 81000 140000 150000 160000 170000 180000>; active_hysteresis = <0 18000 8000 8000 8000 0 0 0 0 0>; }; cool { active_trip_temps = <0 35000 53000 62000 73000 140000 150000 160000 170000 180000>; active_hysteresis = <0 9000 8000 8000 9000 0 0 0 0 0>; }; }; }; }; # 23 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-thermal.dtsi" 2 / { bpmp { bpmpthermal { status = "okay"; }; }; bpmp_i2c { tegra_tmp451: temp-sensor@4c { status = "okay"; #thermal-sensor-cells = <1>; compatible = "ti,tmp451"; reg = <0x4c>; sensor-name = "tmp451-ext"; supported-hwrev = <1>; offset = <(-38)>; conv-rate = <0x06>; extended-rage = <1>; interrupt-parent = <&tegra_main_gpio>; interrupts = <((7 * 8) + 2) 0x00000008>; temp-alert-gpio = <&tegra_main_gpio ((7 * 8) + 2) 0>; vdd-supply = <&e3360_vdd_slt_1v8>; loc { shutdown-limit = <107>; }; ext { shutdown-limit = <109>; }; }; }; thermal-zones { status = "okay"; Tboard_tegra: Tboard_tegra { status = "okay"; polling-delay = <0>; polling-delay-passive = <1000>; thermal-sensors = <&tegra_tmp451 0>; }; Tdiode_tegra: Tdiode_tegra { status = "okay"; polling-delay = <0>; polling-delay-passive = <1000>; thermal-sensors = <&tegra_tmp451 1>; }; CPU-therm { status = "okay"; polling-delay-passive = <500>; thermal-zone-params { governor-name = "step_wise"; }; trips { trip_critical { temperature = <95500>; type = "critical"; hysteresis = <0>; writable; }; trip_bthrot { temperature = <90000>; type = "passive"; hysteresis = <0>; writable; }; }; cooling-maps { map0 { trip = <&{/thermal-zones/CPU-therm/trips/trip_bthrot}>; cdev-type = "cpu-balanced"; cooling-device = <&{/bthrot_cdev/cpu_balanced} 0xffffffff 0xffffffff>; }; }; }; AUX-therm { status = "okay"; polling-delay-passive = <500>; trips { trip_critical { temperature = <94500>; type = "critical"; hysteresis = <0>; writable; }; trip_bthrot { temperature = <89000>; type = "passive"; hysteresis = <0>; writable; }; }; cooling-maps { map0 { trip = <&{/thermal-zones/AUX-therm/trips/trip_bthrot}>; cdev-type = "aux-balanced"; cooling-device = <&{/bthrot_cdev/aux_balanced} 0xffffffff 0xffffffff>; }; }; }; GPU-therm { status = "okay"; polling-delay-passive = <500>; thermal-zone-params { governor-name = "step_wise"; }; trips { trip_critical { temperature = <98000>; type = "critical"; hysteresis = <0>; writable; }; trip_bthrot { temperature = <92500>; type = "passive"; hysteresis = <0>; writable; }; }; cooling-maps { map0 { trip = <&{/thermal-zones/GPU-therm/trips/trip_bthrot}>; cdev-type = "gpu-balanced"; cooling-device = <&{/bthrot_cdev/gpu_balanced} 0xffffffff 0xffffffff>; }; }; }; AO-therm { status = "okay"; thermal-zone-params { governor-name = "step_wise"; }; trips { trip_dram_refresh { temperature = <85000>; type = "active"; hysteresis = <3000>; writable; }; }; cooling-maps { map0 { trip = <&{/thermal-zones/AO-therm/trips/trip_dram_refresh}>; cdev-type = "bwmgr-therm-handler"; cooling-device = <&bwmgr 0xffffffff 0xffffffff>; }; }; }; }; }; # 15 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-thermal-p2888.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-thermal-userspace-alert.dtsi" 1 # 14 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-thermal-userspace-alert.dtsi" / { cpu_alert: cpu-throttle-alert { compatible = "userspace-therm-alert"; cdev-type = "cpu-throttle-alert"; status = "disabled"; #cooling-cells = <2>; }; gpu_alert: gpu-throttle-alert { compatible = "userspace-therm-alert"; cdev-type = "gpu-throttle-alert"; status = "disabled"; #cooling-cells = <2>; }; aux_alert: aux-throttle-alert { compatible = "userspace-therm-alert"; cdev-type = "aux-throttle-alert"; status = "disabled"; #cooling-cells = <2>; }; thermal-zones { CPU-therm { cooling-maps { user-alert-map0 { trip = <&{/thermal-zones/CPU-therm/trips/trip_bthrot}>; cooling-device = <&cpu_alert 1 1>; }; }; }; AUX-therm { cooling-maps { user-alert-map0 { trip = <&{/thermal-zones/AUX-therm/trips/trip_bthrot}>; cooling-device = <&aux_alert 1 1>; }; }; }; GPU-therm { cooling-maps { user-alert-map0 { trip = <&{/thermal-zones/GPU-therm/trips/trip_bthrot}>; cooling-device = <&gpu_alert 1 1>; }; }; }; }; }; # 16 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-thermal-p2888.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-spmic-p2888-0001.dtsi" 1 # 20 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-spmic-p2888-0001.dtsi" / { aliases { rtc0 = &p2888_spmic; rtc1 = &tegra_rtc; }; bpmp_i2c { p2888_spmic: spmic@3c { compatible = "maxim,max20024"; reg = <0x3c>; interrupt-parent = <&tegra_pm_irq>; interrupts = <0 209 0x00000000>; #interrupt-cells = <2>; interrupt-controller; gpio-controller; #gpio-cells = <2>; enable-clock32k-out; system-pmic-power-off; avoid-power-off-commands; hot-die-threshold-temp = <110000>; #thermal-sensor-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&spmic_default>; spmic_default: pinmux@0 { pin_gpio0 { pins = "gpio0"; function = "gpio"; }; pin_gpio1 { pins = "gpio1"; function = "fps-out"; active-fps-source = <4>; }; pin_gpio2 { pins = "gpio2"; function = "fps-out"; active-fps-source = <4>; }; pin_gpio3 { pins = "gpio3"; function = "fps-out"; active-fps-source = <4>; }; pin_gpio4 { pins = "gpio4"; function = "32k-out1"; drive-push-pull = <1>; }; pin_gpio6 { pins = "gpio6"; function = "gpio"; drive-push-pull = <1>; }; pin_gpio7 { pins = "gpio7"; function = "gpio"; drive-push-pull = <0>; }; }; gpio_default { gpio-hog; output-high; gpios = <6 0 7 0>; label = "spmic-gpio6", "spmic-gpio7"; }; p2888_spmic_wdt: watchdog { wdt-boot-timeout = <32>; wdt-suspend-timeout = <120>; status = "disabled"; }; fps { #address-cells = <1>; #size-cells = <0>; fps0 { reg = <0>; fps-event-source = <0>; }; fps1 { reg = <1>; fps-event-source = <1>; device-state-on-disabled-event = <0>; }; fps2 { reg = <2>; fps-event-source = <0>; }; }; backup-battery { backup-battery-charging-current = <100>; backup-battery-charging-voltage = <3000000>; backup-battery-output-resister = <100>; status = "disabled"; }; regulators { in-ldo7-8-supply = <&p2888_spmic_sd2>; p2888_spmic_sd0: sd0 { regulator-name = "vdd-1v0"; regulator-always-on; regulator-boot-on; regulator-init-mode = <0x2>; active-fps-source = <4>; }; p2888_spmic_sd1: sd1 { regulator-name = "vdd-1v8-hs"; regulator-always-on; regulator-boot-on; regulator-init-mode = <0x2>; active-fps-source = <4>; }; p2888_spmic_sd2: sd2 { regulator-name = "vdd-1v8-ls"; regulator-always-on; regulator-boot-on; regulator-init-mode = <0x2>; active-fps-source = <4>; }; p2888_spmic_sd3: sd3 { regulator-name = "vdd-1v8-ao"; regulator-always-on; regulator-boot-on; regulator-init-mode = <0x2>; active-fps-source = <4>; }; p2888_spmic_sd4: sd4 { regulator-name = "vddio-ddr-1v1"; regulator-always-on; regulator-boot-on; regulator-init-mode = <0x2>; active-fps-source = <4>; }; p2888_spmic_ldo0: ldo0 { regulator-name = "vdd-rtc"; regulator-always-on; regulator-boot-on; active-fps-source = <4>; }; p2888_spmic_ldo1: ldo1 { regulator-name = "spmic-ldo1"; active-fps-source = <4>; }; p2888_spmic_ldo2: ldo2 { regulator-name = "vdd-ao-3v3"; regulator-always-on; regulator-boot-on; active-fps-source = <4>; }; p2888_spmic_ldo3: ldo3 { regulator-name = "vddio-emmc-3v3"; regulator-always-on; regulator-boot-on; active-fps-source = <4>; }; p2888_spmic_ldo4: ldo4 { regulator-name = "spmic-ldo4"; active-fps-source = <4>; }; p2888_spmic_ldo5: ldo5 { regulator-name = "vdd-usb-3v3"; regulator-always-on; regulator-boot-on; active-fps-source = <4>; }; p2888_spmic_ldo6: ldo6 { regulator-name = "vddio-sdmmc1-3v3"; regulator-always-on; regulator-boot-on; active-fps-source = <4>; }; p2888_spmic_ldo7: ldo7 { regulator-name = "vdd-csi-1v2"; regulator-always-on; regulator-boot-on; active-fps-source = <4>; }; p2888_spmic_ldo8: ldo8 { regulator-name = "spmic-ldo8"; active-fps-source = <4>; }; }; }; }; dummy_cool_dev: dummy-cool-dev { compatible = "dummy-cooling-dev"; #cooling-cells = <2>; status = "disabled"; }; thermal-zones { PMIC-Die { polling-delay = <0>; polling-delay-passive = <0>; thermal-sensors = <&p2888_spmic>; trips { die_temp_thresh: hot-die { temperature = <120000>; type = "active"; hysteresis = <0>; }; }; cooling-maps { map0 { trip = <&die_temp_thresh>; cooling-device = <&{/bthrot_cdev/emergency_balanced} 0xffffffff 0xffffffff>; contribution = <100>; cdev-type = "emergency-balanced"; }; }; }; }; }; # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-thermal-p2888.dtsi" 2 / { bpmp_i2c { tegra_tmp451: temp-sensor@4c { vdd-supply = <&p2888_spmic_sd2>; }; }; soctherm-oc-event { status = "okay"; }; cpu_alert: cpu-throttle-alert { status = "okay"; }; gpu_alert: gpu-throttle-alert { status = "okay"; }; aux_alert: aux-throttle-alert { status = "okay"; }; }; # 24 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0001-p2822-0000-common.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-plugin-manager-p2888-0000.dtsi" 1 # 15 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-plugin-manager-p2888-0000.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-p2822-pcie-plugin-manager.dtsi" 1 # 15 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-p2822-pcie-plugin-manager.dtsi" / { plugin-manager { fragment-pcie-c1-rp { ids = "<2822-0000-200"; override@0 { target = <&{/pcie@14100000}>; _overlay_ { nvidia,max-speed = <1>; }; }; }; fragment-pcie-older-than-p2822-B00 { ids = "<2822-0000-400"; override@0 { target = <&{/pcie@14100000}>; _overlay_ { nvidia,disable-aspm-states = <0xf>; }; }; override@1 { target = <&p2822_vdd_3v3_pcie>; _overlay_ { delete-target-property = "gpio"; }; }; override@2 { target = <&p2822_vdd_12v_pcie>; _overlay_ { delete-target-property = "gpio"; }; }; }; fragment-disable-uphy-rx-idle { ids = "<=2822-0000-300"; override@0 { target = <&{/hsio_p2u/p2u@03e10000}>; _overlay_ { append-string-property = "nvidia,disable-uphy-rx-idle"; }; }; }; fragment-pcie-c5-rp { odm-anded-override; odm-data = "disable-pcie-c5-endpoint", "enable-nvhs-uphy-pcie-c5"; override@0 { target = <&{/pcie@141a0000}>; _overlay_ { status = "okay"; }; }; override@1 { target = <&{/pcie_ep@141a0000}>; _overlay_ { status = "disabled"; }; }; override@2 { target = <&{/gpio@c2f0000/pex-refclk-sel-low}>; _overlay_ { status = "okay"; }; }; }; fragment-pcie-c5-ep { odm-anded-override; odm-data = "enable-pcie-c5-endpoint", "enable-nvhs-uphy-pcie-c5"; override@0 { target = <&{/pcie@141a0000}>; _overlay_ { status = "disabled"; }; }; override@1 { target = <&{/pcie_ep@141a0000}>; _overlay_ { status = "okay"; }; }; override@2 { target = <&{/gpio@c2f0000/pex-refclk-sel-high}>; _overlay_ { status = "okay"; }; }; }; }; }; # 16 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-plugin-manager-p2888-0000.dtsi" 2 / { plugin-manager { fragement-pmic-wdt-en { odm-data = "enable-pmic-wdt"; override@0 { target = <&p2888_spmic_wdt>; _overlay_ { status = "okay"; }; }; }; fragement-tegra-wdt-en { odm-data = "enable-denver-wdt"; override@0 { target = <&tegra_wdt>; _overlay_ { status = "okay"; }; }; }; fragemen-tegra-wdt-dis { odm-data = "disable-denver-wdt"; override@0 { target = <&tegra_pmc>; _overlay_ { nvidia,enable-halt-in-fiq; }; }; }; fragment-tegra-ufs-lane10 { odm-data = "enable-ufs-uphy-l10"; override@0 { target = <&tegra_ufs>; _overlay_ { status = "okay"; }; }; }; }; }; # 25 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0001-p2822-0000-common.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-plugin-manager-p2822-0000.dtsi" 1 # 16 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-plugin-manager-p2822-0000.dtsi" / { plugin-manager { pwm-fan-polarity { ids = "<2822-0000-400"; override@0 { target = <&pwm_fan_shared_data>; _overlay_ { pwm_polarity = <(1 << 0)>; }; }; override@1 { target = <&pwm_fan_shared_data>; _overlay_ { suspend_state = <1>; }; }; }; ufs-cd { ids = "<2822-0000-400"; override@0 { target = <&{/ufshci@2450000}>; _overlay_ { status = "disabled"; }; }; }; usb-vbus-en0-gpio-value { ids = "<2822-0000-400"; override@0 { target = <&p2822_vdd_5v_sata>; _overlay_ { delete-target-property = "enable-active-high"; }; }; }; }; }; # 26 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0001-p2822-0000-common.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-super-module-e2614-p2888-0000.dtsi" 1 # 16 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-super-module-e2614-p2888-0000.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-super-module-e2614.dtsi" 1 # 16 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-super-module-e2614.dtsi" / { i2c@31e0000 { e2614_i2c_mux: i2cmux@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; #size-cells = <0>; vcc-pullup-supply = <&battery_reg>; status = "disabled"; i2c@0 { reg = <0>; i2c-mux,deselect-on-exit; #address-cells = <1>; #size-cells = <0>; e2614_tas2552_r:tas2552.9-0040@40 { compatible = "ti,tas2552"; reg = <0x40>; vbat-supply = <&battery_reg>; avdd-supply = <&vdd_1v8_aud2>; tas2552,pdm_edge_select = <0>; }; e2614_tas2552_l:tas2552.9-0041@41 { compatible = "ti,tas2552"; reg = <0x41>; vbat-supply = <&battery_reg>; avdd-supply = <&vdd_1v8_aud2>; tas2552,pdm_edge_select = <1>; }; }; i2c@1 { reg = <1>; i2c-mux,deselect-on-exit; #address-cells = <1>; #size-cells = <0>; ina3221x@40 { compatible = "ti,ina3221x"; reg = <0x40>; ti,trigger-config = <0x7003>; ti,continuous-config = <0x7c07>; ti,enable-forced-continuous; #address-cells = <1>; #size-cells = <0>; channel@0 { reg = <0x0>; ti,rail-name = "VDD_5V"; ti,shunt-resistor-mohm = <10>; }; channel@1 { reg = <0x1>; ti,rail-name = "VDD_3V3"; ti,shunt-resistor-mohm = <10>; }; channel@2 { reg = <0x2>; ti,rail-name = "VDD_1V8"; ti,shunt-resistor-mohm = <1>; }; }; ina3221x@41 { compatible = "ti,ina3221x"; reg = <0x41>; ti,trigger-config = <0x7003>; ti,continuous-config = <0x7c07>; ti,enable-forced-continuous; #address-cells = <1>; #size-cells = <0>; channel@0 { reg = <0x0>; ti,rail-name = "VDD_5V_AUD"; ti,shunt-resistor-mohm = <1>; }; channel@1 { reg = <0x1>; ti,rail-name = "VDD_3V3_AUD"; ti,shunt-resistor-mohm = <10>; }; channel@2 { reg = <0x2>; ti,rail-name = "VDD_1V8_AUD"; ti,shunt-resistor-mohm = <10>; }; }; ina3221x@42 { compatible = "ti,ina3221x"; reg = <0x42>; ti,trigger-config = <0x7003>; ti,continuous-config = <0x7c07>; ti,enable-forced-continuous; #address-cells = <1>; #size-cells = <0>; channel@0 { reg = <0x0>; ti,rail-name = "VDD_3V3_GPS"; ti,shunt-resistor-mohm = <10>; }; channel@1 { reg = <0x1>; ti,rail-name = "VDD_3V3_NFC"; ti,shunt-resistor-mohm = <10>; }; channel@2 { reg = <0x2>; ti,rail-name = "VDD_3V3_GYRO"; ti,shunt-resistor-mohm = <10>; }; }; }; i2c@2 { reg = <2>; i2c-mux,deselect-on-exit; #address-cells = <1>; #size-cells = <0>; }; i2c@3 { reg = <3>; i2c-mux,deselect-on-exit; #address-cells = <1>; #size-cells = <0>; e2614_rt5658_i2c3: rt5659.12-001a@1a { compatible = "realtek,rt5658"; reg = <0x1a>; status = "disabled"; gpios = <&tegra_main_gpio ((17 * 8) + 0) 0>; realtek,jd-src = <1>; realtek,dmic1-data-pin = <2>; }; }; }; e2614_gpio_i2c_1_20: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; vcc-supply = <&battery_reg>; status = "disabled"; }; e2614_rt5658: rt5659.1-001a@1a { compatible = "realtek,rt5658"; reg = <0x1a>; status = "disabled"; gpios = <&tegra_main_gpio ((17 * 8) + 0) 0>; realtek,jd-src = <1>; realtek,dmic1-data-pin = <2>; }; }; fixed-regulators { vdd_1v8_aud2: regulator@200 { compatible = "regulator-fixed-sync"; reg = <200>; regulator-name = "vdd-1v8-aud2"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; gpio = <&e2614_gpio_i2c_1_20 11 1>; enable-active-high; status = "disabled"; }; }; e2614_gps_wake: gps_wake { compatible = "gps-wake"; gps-enable-gpio = <&e2614_gpio_i2c_1_20 8 0>; gps-wakeup-gpio = <&tegra_main_gpio ((0 * 8) + 0) 0>; status = "disabled"; }; plugin-manager { fragment-e2614-common@0 { ids = "2614-0000-*"; overrides@0 { target = <&e2614_i2c_mux>; _overlay_ { status = "okay"; }; }; overrides@1 { target = <&e2614_gpio_i2c_1_20>; _overlay_ { status = "okay"; }; }; overrides@8 { target = <&vdd_1v8_aud2>; _overlay_ { status = "okay"; }; }; overrides@11 { target = <&hdr40_snd_link_i2s>; _overlay_ { link-name = "rt565x-codec-sysclk-bclk1"; codec-dai = <&e2614_rt5658>; codec-dai-name = "rt5659-aif1"; }; }; }; fragment-e2614-a00@1 { ids = "2614-0000-000"; overrides@0 { target = <&e2614_rt5658>; _overlay_ { status = "okay"; }; }; overrides@1 { target = <&hdr40_snd_link_i2s>; _overlay_ { link-name = "rt565x-codec-sysclk-bclk1"; codec-dai = <&e2614_rt5658>; codec-dai-name = "rt5659-aif1"; }; }; }; fragment-e2614-b00@2 { ids = "2614-0000-100"; overrides@0 { target = <&e2614_rt5658_i2c3>; _overlay_ { status = "okay"; }; }; overrides@1 { target = <&hdr40_snd_link_i2s>; _overlay_ { link-name = "rt565x-codec-sysclk-bclk1"; codec-dai = <&e2614_rt5658_i2c3>; codec-dai-name = "rt5659-aif1"; }; }; }; }; }; # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-super-module-e2614-p2888-0000.dtsi" 2 / { i2c@31e0000 { i2cmux@70 { vcc-supply = <&p2822_vdd_3v3_cvb>; i2c@0 { tas2552.9-0040@40 { iovdd-supply = <&p2822_vdd_3v3_cvb>; }; tas2552.9-0041@41 { iovdd-supply = <&p2822_vdd_3v3_cvb>; }; }; }; }; plugin-manager { fragment-e2614-common@0 { overrides@10 { target = <&tegra_sound>; _overlay_ { nvidia,audio-routing = "x Headphone Jack", "x HPO L Playback", "x Headphone Jack", "x HPO R Playback", "x IN1P", "x Mic Jack", "x IN2P", "x Mic Jack", "x Int Spk", "x SPO Playback", "x DMIC L1", "x Int Mic", "x DMIC L2", "x Int Mic", "x DMIC R1", "x Int Mic", "x DMIC R2", "x Int Mic", "y Headphone", "y HPO L Playback", "y Headphone", "y HPO R Playback", "y IN1P", "y Mic", "z Headphone", "z OUT", "z IN", "z Mic", "m Headphone", "m OUT", "m IN", "m Mic", "n Headphone", "n OUT", "n IN", "n Mic", "o Headphone", "o OUT", "o IN", "o Mic", "a IN", "a Mic", "b IN", "b Mic", "c IN", "c Mic", "d IN", "d Mic", "d1 Headphone", "d1 OUT", "d2 Headphone", "d2 OUT"; }; }; }; }; }; # 27 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0001-p2822-0000-common.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-no-pll-aon-clock.dtsi" 1 # 20 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-platforms/tegra194-no-pll-aon-clock.dtsi" /{ spi@c260000 { clocks = <&bpmp_clks 136U>, <&bpmp_clks 91U>; }; mttcan@c310000 { pll_source = "osc"; clocks = <&bpmp_clks 284U>, <&bpmp_clks 10U>, <&bpmp_clks 9U>, <&bpmp_clks 91U>; clock-names = "can_core", "can_host","can", "osc"; }; mttcan@c320000 { pll_source = "osc"; clocks = <&bpmp_clks 285U>, <&bpmp_clks 12U>, <&bpmp_clks 11U>, <&bpmp_clks 91U>; clock-names = "can_core", "can_host","can", "osc"; }; }; # 28 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0001-p2822-0000-common.dtsi" 2 / { nvidia,dtsfilename = "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0001-p2822-0000-common.dtsi"; nvidia,dtbbuildtime = "Oct 29 2021", "09:42:05"; nvidia,fastboot-usb-vid = <0x0955>; nvidia,fastboot-usb-pid = <0xee1e>; model = "Jetson-AGX"; compatible = "nvidia,galen", "nvidia,jetson-xavier", "nvidia,p2822-0000+p2888-0001", "nvidia,tegra194"; chosen { bootargs ="console=ttyTCU0,115200"; board-has-eeprom; }; firmware { android { compatible = "android,firmware"; hardware = "jetson-xavier"; vbmeta { compatible = "android,vbmeta"; parts = "vbmeta,kernel,kernel-dtb,APP,vendor,SOS"; }; fstab { compatible = "android,fstab"; vendor { compatible = "android,vendor"; dev = "/dev/block/platform/3460000.sdhci/by-name/vendor"; type = "ext4"; mnt_flags = "ro"; fsmgr_flags = "wait,avb"; }; odm { compatible = "android,odm"; dev = "/dev/block/platform/3460000.sdhci/by-name/odm"; type = "ext4"; mnt_flags = "ro"; fsmgr_flags = "wait,avb"; }; }; }; }; bluedroid_pm { compatible = "nvidia,tegra-bluedroid_pm"; bluedroid_pm,reset-gpio = <&tegra_main_gpio ((12 * 8) + 6) 0>; bluedroid_pm,host-wake-gpio = <&tegra_main_gpio ((24 * 8) + 0) 0>; bluedroid_pm,ext-wake-gpio = <&tegra_main_gpio ((12 * 8) + 7) 0>; interrupt-parent = <&tegra_main_gpio>; interrupts = <((24 * 8) + 0) 0x01>; }; spi@c260000 { status = "disabled"; # 92 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0001-p2822-0000-common.dtsi" }; spi@3210000 { status = "okay"; prod-settings { #prod-cells = <3>; prod { prod = <0x04 0x0000003f 0x0f>; }; }; spidev: tpm@0{ compatible = "tcg,tpm_tis-spi"; status = "okay"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <500000>; controller-data { nvidia,enable-hw-based-cs; nvidia,cs-setup-clk-count = <0x1e>; nvidia,cs-hold-clk-count = <0x1e>; nvidia,rx-clk-tap-delay = <0x1f>; nvidia,tx-clk-tap-delay = <0x0>; nvidia,cs-inactive-cycles = <0x0>; }; }; spi@1 { compatible = "tegra-spidev"; reg = <0x1>; spi-max-frequency = <33000000>; controller-data { nvidia,enable-hw-based-cs; nvidia,cs-setup-clk-count = <0x1e>; nvidia,cs-hold-clk-count = <0x1e>; nvidia,rx-clk-tap-delay = <0x11>; nvidia,tx-clk-tap-delay = <0x0>; nvidia,cs-inactive-cycles = <0x0>; }; }; }; # 159 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0001-p2822-0000-common.dtsi" spi@3270000 { status = "disabled"; }; spi@3300000 { status = "disabled"; }; pmc@c370000 { nvidia,invert-interrupt; }; hdr40_i2c0: i2c@c240000 { bmi160@69 { compatible = "bmi,bmi160"; reg = <0x69>; interrupt-parent = <&tegra_aon_gpio>; interrupts = <((0 * 8) + 2) 1>; accelerometer_matrix = [01 00 00 00 01 00 00 00 01]; gyroscope_matrix = [01 00 00 00 01 00 00 00 01]; accelerometer_delay_us_min = <1250>; gyroscope_delay_us_min = <1250>; status = "disabled"; }; ucsi_ccg: ucsi_ccg@8 { status = "disabled"; typec-extcon { typec_port0: port-0 { status = "okay"; #extcon-cells = <1>; }; typec_port1: port-1 { status = "okay"; #extcon-cells = <1>; }; }; typec-pd { typec_pd: pd { status = "okay"; #extcon-cells = <1>; }; }; }; }; xusb_padctl: xusb_padctl@3520000 { status = "okay"; pads { usb2 { lanes { usb2-0 { nvidia,function = "xusb"; status = "okay"; }; usb2-1 { nvidia,function = "xusb"; status = "okay"; }; usb2-2 { nvidia,function = "xusb"; status = "okay"; }; usb2-3 { nvidia,function = "xusb"; status = "okay"; }; }; }; usb3 { lanes { usb3-0 { nvidia,function = "xusb"; status = "okay"; }; usb3-1 { nvidia,function = "xusb"; status = "okay"; }; usb3-2 { nvidia,function = "xusb"; status = "okay"; }; usb3-3 { nvidia,function = "xusb"; status = "okay"; }; }; }; }; ports { usb2-0 { mode = "host"; vbus-supply = <&battery_reg>; status = "okay"; }; usb2-1 { mode = "host"; vbus-supply = <&battery_reg>; status = "okay"; }; usb2-2 { mode = "host"; vbus-supply = <&battery_reg>; status = "okay"; }; usb2-3 { mode = "host"; vbus-supply = <&battery_reg>; status = "okay"; }; usb3-0 { nvidia,usb2-companion = <0x0>; vbus-supply = <&battery_reg>; status = "okay"; }; usb3-1 { nvidia,usb2-companion = <0>; vbus-supply = <&battery_reg>; status = "okay"; }; usb3-2 { nvidia,usb2-companion = <0>; vbus-supply = <&battery_reg>; status = "okay"; }; usb3-3 { nvidia,usb2-companion = <3>; nvidia,usb3-gen1-only= <1>; vbus-supply = <&battery_reg>; status = "okay"; }; }; # 337 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0001-p2822-0000-common.dtsi" }; tegra_xudc: xudc@3550000 { # 351 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0001-p2822-0000-common.dtsi" phys = <&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-0}>, <&{/xusb_padctl@3520000/pads/usb3/lanes/usb3-2}>; phy-names = "usb2", "usb3"; nvidia,xusb-padctl = <&xusb_padctl>; nvidia,boost_cpu_freq = <1200>; status = "okay"; }; tegra_xhci: xhci@3610000 { # 371 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0001-p2822-0000-common.dtsi" phys = <&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-0}>, <&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-1}>, <&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-3}>, <&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-2}>, <&{/xusb_padctl@3520000/pads/usb3/lanes/usb3-2}>, <&{/xusb_padctl@3520000/pads/usb3/lanes/usb3-0}>, <&{/xusb_padctl@3520000/pads/usb3/lanes/usb3-1}>, <&{/xusb_padctl@3520000/pads/usb3/lanes/usb3-3}>; phy-names = "usb2-0", "usb2-1", "usb2-3", "usb2-2", "usb3-2", "usb3-0", "usb3-1", "usb3-3"; nvidia,xusb-padctl = <&xusb_padctl>; status = "okay"; }; arm-pmu { status = "okay"; }; power-domain { status = "disabled"; }; interrupt-controller { status = "disabled"; }; mods-simple-bus { status = "disabled"; }; eeprom-manager { status = "disabled"; }; cpuidle { compatible = "nvidia,tegra19x-cpuidle"; status = "okay"; }; thermal-zones { status = "disabled"; }; reserved-memory { ramoops_carveout { status = "okay"; }; }; mttcan@c310000 { status = "okay"; }; mttcan@c320000 { status = "okay"; }; serial@3110000 { status = "okay"; }; pwm@3280000 { status = "okay"; }; pwm@32c0000 { status = "okay"; }; pwm@32f0000 { status = "okay"; }; hdr40_i2c1: i2c@31e0000 { pinctrl-names = "default"; pinctrl-0 = <&dpaux_default>; bmi160@69 { compatible = "bmi,bmi160"; reg = <0x69>; accelerometer_matrix = [01 00 00 00 01 00 00 00 01]; gyroscope_matrix = [01 00 00 00 01 00 00 00 01]; status = "disabled"; }; }; host1x { dpaux@155F0000 { status = "okay"; compatible = "nvidia,tegra194-dpaux3-padctl"; /delete-property/ power-domains; dpaux_default: pinmux@0 { dpaux3_pins { pins = "dpaux3-3"; function = "i2c"; }; }; }; }; ufshci@2450000 { status = "disabled"; nvidia,enable-hs-mode; nvidia,cd-gpios = <&tegra_aon_gpio ((4 * 8) + 0) 0>; nvidia,cd-wakeup-capable; }; pfsd { pwm_polarity= <(0)>; suspend_state = <0>; }; clocks-init { compatible = "nvidia,clocks-config"; status = "okay"; disable { clocks = <&aon_clks 94U>, <&bpmp_clks 9U>, <&bpmp_clks 11U>; }; }; }; # 518 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0001-p2822-0000-common.dtsi" &sor0 { }; &sor1 { }; # 22 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/tegra194-p2888-0001-p2822-0000.dts" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-camera-modules.dtsi" 1 # 15 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-camera-modules.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-e3377-a00.dtsi" 1 # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-e3377-a00.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e3377-a00.dtsi" 1 # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e3377-a00.dtsi" / { host1x { vi@15c10000 { num-channels = <1>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; status = "okay"; e3377_vi_in0: endpoint { port-index = <0>; bus-width = <8>; remote-endpoint = <&e3377_slvs_ec_out0>; }; }; }; }; slvs-ec@15ac0000 { status = "okay"; streams { #address-cells = <1>; #size-cells = <0>; stream@0 { reg = <0>; lanes = <0 1 2 3 4 5 6 7>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; e3377_slvs_ec_in0: endpoint@0 { port-index = <0>; bus-width = <8>; remote-endpoint = <&e3377_imx204_out0>; }; }; port@1 { reg = <1>; e3377_slvs_ec_out0: endpoint@1 { remote-endpoint = <&e3377_vi_in0>; }; }; }; }; }; }; }; spi@c260000 { status = "okay"; spi-max-frequency = <12000000>; imx204@0 { compatible = "nvidia,imx204-spi"; reg = <0>; status = "okay"; spi-max-frequency = <12000000>; physical_w = "4.713"; physical_h = "3.494"; delayed_gain = "true"; devname = "imx204-spi"; sensor_model = "imx204"; focus_macro = "100"; focus_infinity = "208"; focus_max_slew_rate = "180"; min_aperture = "2"; max_aperture = "90"; min_aperture_fnumber = "2000"; max_aperture_fnumber = "22000"; aperture_max_slew_rate = "180"; fnumber_map = <2000 2>, <2800 34>, <4000 49>, <5600 59>, <8000 67>, <11000 71>, <16000 75>, <22000 78>; mode0 { mclk_khz = "72000"; num_lanes = "8"; tegra_sinterface = "serial_a"; phy_mode = "SLVS"; discontinuous_clk = "no"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "5352"; active_h = "3950"; pixel_t = "bayer_rggb"; readout_orientation = "0"; line_length = "6667"; inherent_gain = "1"; mclk_multiplier = "11"; pix_clk_hz = "1320000000"; min_gain_val = "1.0"; max_gain_val = "22.3"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; min_framerate = "1.5"; max_framerate = "60"; min_exp_time = "13"; max_exp_time = "33333"; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; e3377_imx204_out0: endpoint { port-index = <0>; bus-width = <8>; remote-endpoint = <&e3377_slvs_ec_in0>; }; }; }; }; }; tegra-camera-platform { compatible = "nvidia, tegra-camera-platform"; # 156 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e3377-a00.dtsi" modules { module0 { badge = "e3377_rear_IMX204"; position = "rear"; orientation = "1"; drivernode0 { pcl_id = "v4l2_sensor"; devname = "imx204_spi"; proc-device-tree = "/proc/device-tree/spi@c260000/imx204@0"; }; }; }; }; }; # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-e3377-a00.dtsi" 2 / { host1x { slvs-ec@15ac0000 { streams { stream@0 { watchdog-period = <0>; nvidia,symbols = <0x0360AA>; nvidia,uphy-cal-skip; nvidia,uphy-rate-gen2; nvidia,uphy-term-other; nvidia,uphy-aux-term-other; nvidia,uphy-skip-sleep; nvidia,uphy-dedicated-calibration; nvidia,uphy-aux-idle-mode = <3>; nvidia,uphy-aux-idle-detect; nvidia,syncgen = <0>; nvidia,syncgen-xhs-vgp = <1>; nvidia,syncgen-xvs-vgp = <4>; }; }; }; }; spi@c260000 { imx204@0 { reset-gpios = <&tegra_main_gpio ((24 * 8) + 1) 0>; }; }; gpio@2200000 { camera-control-output-low { gpio-hog; output-low; gpios = <((24 * 8) + 1) 0>; label = "slvs-cam0-rst"; }; }; }; # 16 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-camera-modules.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-e3326-a00.dtsi" 1 # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-e3326-a00.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e3326-a00.dtsi" 1 # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e3326-a00.dtsi" / { host1x { vi@15c10000 { num-channels = <1>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; e3326_vi_in0: endpoint { port-index = <2>; bus-width = <2>; remote-endpoint = <&e3326_csi_out0>; }; }; }; }; nvcsi@15a00000 { num-channels = <1>; #address-cells = <1>; #size-cells = <0>; channel@0 { reg = <0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; e3326_csi_in0: endpoint@0 { port-index = <2>; bus-width = <2>; remote-endpoint = <&e3326_ov5693_out0>; }; }; port@1 { reg = <1>; e3326_csi_out0: endpoint@1 { remote-endpoint = <&e3326_vi_in0>; }; }; }; }; }; }; i2c@3180000 { ov5693_c@36 { compatible = "nvidia,ov5693"; reg = <0x36>; devnode = "video0"; physical_w = "3.674"; physical_h = "2.738"; avdd-reg = "vana"; iovdd-reg = "vif"; vertical-flip = "true"; has-eeprom = "1"; # 195 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e3326-a00.dtsi" mode0 { mclk_khz = "24000"; num_lanes = "2"; tegra_sinterface = "serial_c"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "2592"; active_h = "1944"; mode_type = "bayer"; pixel_phase = "bggr"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "2688"; inherent_gain = "1"; mclk_multiplier = "6.67"; pix_clk_hz = "160000000"; gain_factor = "10"; min_gain_val = "10"; max_gain_val = "160"; step_gain_val = "1"; default_gain = "10"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "1816577"; max_framerate = "30000000"; step_framerate = "1"; default_framerate = "30000000"; exposure_factor = "1000000"; min_exp_time = "34"; max_exp_time = "550385"; step_exp_time = "1"; default_exp_time = "33334"; embedded_metadata_height = "0"; }; mode1 { mclk_khz = "24000"; num_lanes = "2"; tegra_sinterface = "serial_c"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "2592"; active_h = "1458"; mode_type = "bayer"; pixel_phase = "bggr"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "2688"; inherent_gain = "1"; mclk_multiplier = "6.67"; pix_clk_hz = "160000000"; gain_factor = "10"; min_gain_val = "10"; max_gain_val = "160"; step_gain_val = "1"; default_gain = "10"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "1816577"; max_framerate = "30000000"; step_framerate = "1"; default_framerate = "30000000"; exposure_factor = "1000000"; min_exp_time = "34"; max_exp_time = "550385"; step_exp_time = "1"; default_exp_time = "33334"; embedded_metadata_height = "0"; }; mode2 { mclk_khz = "24000"; num_lanes = "2"; tegra_sinterface = "serial_c"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "1280"; active_h = "720"; mode_type = "bayer"; pixel_phase = "bggr"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "1752"; inherent_gain = "1"; mclk_multiplier = "6.67"; pix_clk_hz = "160000000"; gain_factor = "10"; min_gain_val = "10"; max_gain_val = "160"; step_gain_val = "1"; default_gain = "10"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "2787078"; max_framerate = "120000000"; step_framerate = "1"; default_framerate = "120000000"; exposure_factor = "1000000"; min_exp_time = "22"; max_exp_time = "358733"; step_exp_time = "1"; default_exp_time = "8334"; embedded_metadata_height = "0"; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; e3326_ov5693_out0: endpoint { port-index = <2>; bus-width = <2>; remote-endpoint = <&e3326_csi_in0>; }; }; }; }; }; e3326_lens_ov5693@P5V27C { min_focus_distance = "0.0"; hyper_focal = "0.0"; focal_length = "2.67"; f_number = "2.0"; aperture = "2.0"; }; tegra-camera-platform { compatible = "nvidia, tegra-camera-platform"; # 368 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e3326-a00.dtsi" num_csi_lanes = <2>; max_lane_speed = <1500000>; min_bits_per_pixel = <10>; vi_peak_byte_per_pixel = <2>; vi_bw_margin_pct = <25>; max_pixel_rate = <160000>; isp_peak_byte_per_pixel = <5>; isp_bw_margin_pct = <25>; # 385 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e3326-a00.dtsi" modules { module0 { badge = "e3326_front_P5V27C"; position = "rear"; orientation = "1"; drivernode0 { pcl_id = "v4l2_sensor"; devname = "ov5693 2-0036"; proc-device-tree = "/proc/device-tree/i2c@3180000/ov5693_c@36"; }; drivernode1 { pcl_id = "v4l2_lens"; proc-device-tree = "/proc/device-tree/e3326_lens_ov5693@P5V27C/"; }; }; }; }; }; # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-e3326-a00.dtsi" 2 / { i2c@3180000 { ov5693_c@36 { clocks = <&bpmp_clks 36U>, <&bpmp_clks 102U>; clock-names = "extperiph1", "pllp_grtba"; mclk = "extperiph1"; clock-frequency = <24000000>; reset-gpios = <&tegra_main_gpio ((7 * 8) + 3) 0>; pwdn-gpios = <&tegra_main_gpio ((7 * 8) + 6) 0>; vif-supply = <&p2822_vdd_1v8_cvb>; }; }; gpio@2200000 { camera-control-output-low { gpio-hog; output-low; gpios = <((7 * 8) + 3) 0 ((7 * 8) + 6) 0>; label = "cam0-rst", "cam0-pwdn"; }; }; }; # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-camera-modules.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-e3333-a00.dtsi" 1 # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-e3333-a00.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e3333-a00.dtsi" 1 # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e3333-a00.dtsi" / { host1x { vi@15c10000 { num-channels = <6>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; e3333_vi_in0: endpoint { port-index = <0>; bus-width = <2>; remote-endpoint = <&e3333_csi_out0>; }; }; port@1 { reg = <1>; e3333_vi_in1: endpoint { port-index = <1>; bus-width = <2>; remote-endpoint = <&e3333_csi_out1>; }; }; port@2 { reg = <2>; e3333_vi_in2: endpoint { port-index = <2>; bus-width = <2>; remote-endpoint = <&e3333_csi_out2>; }; }; port@3 { reg = <3>; e3333_vi_in3: endpoint { port-index = <3>; bus-width = <2>; remote-endpoint = <&e3333_csi_out3>; }; }; port@4 { reg = <4>; e3333_vi_in4: endpoint { port-index = <4>; bus-width = <2>; remote-endpoint = <&e3333_csi_out4>; }; }; port@5 { reg = <5>; e3333_vi_in5: endpoint { port-index = <5>; bus-width = <2>; remote-endpoint = <&e3333_csi_out5>; }; }; }; }; nvcsi@15a00000 { num-channels = <6>; #address-cells = <1>; #size-cells = <0>; status = "okay"; channel@0 { reg = <0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; e3333_csi_in0: endpoint@0 { port-index = <0>; bus-width = <2>; remote-endpoint = <&e3333_ov5693_out0>; }; }; port@1 { reg = <1>; e3333_csi_out0: endpoint@1 { remote-endpoint = <&e3333_vi_in0>; }; }; }; }; channel@1 { reg = <1>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; e3333_csi_in1: endpoint@2 { port-index = <1>; bus-width = <2>; remote-endpoint = <&e3333_ov5693_out1>; }; }; port@1 { reg = <1>; e3333_csi_out1: endpoint@3 { remote-endpoint = <&e3333_vi_in1>; }; }; }; }; channel@2 { reg = <2>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; e3333_csi_in2: endpoint@4 { port-index = <2>; bus-width = <2>; remote-endpoint = <&e3333_ov5693_out2>; }; }; port@1 { reg = <1>; e3333_csi_out2: endpoint@5 { remote-endpoint = <&e3333_vi_in2>; }; }; }; }; channel@3 { reg = <3>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; e3333_csi_in3: endpoint@6 { port-index = <3>; bus-width = <2>; remote-endpoint = <&e3333_ov5693_out3>; }; }; port@1 { reg = <1>; e3333_csi_out3: endpoint@7 { remote-endpoint = <&e3333_vi_in3>; }; }; }; }; channel@4 { reg = <4>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; e3333_csi_in4: endpoint@8 { port-index = <4>; bus-width = <2>; remote-endpoint = <&e3333_ov5693_out4>; }; }; port@1 { reg = <1>; e3333_csi_out4: endpoint@9 { remote-endpoint = <&e3333_vi_in4>; }; }; }; }; channel@5 { reg = <5>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; e3333_csi_in5: endpoint@10 { port-index = <6>; bus-width = <2>; remote-endpoint = <&e3333_ov5693_out5>; }; }; port@1 { reg = <1>; e3333_csi_out5: endpoint@11 { remote-endpoint = <&e3333_vi_in5>; }; }; }; }; }; }; i2c@3180000 { tca9548@77 { i2c@0 { ov5693_a@36 { compatible = "nvidia,ov5693"; reg = <0x36>; devnode = "video0"; physical_w = "3.674"; physical_h = "2.738"; avdd-reg = "vana"; iovdd-reg = "vif"; has-eeprom = "1"; # 304 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e3333-a00.dtsi" mode0 { mclk_khz = "24000"; num_lanes = "2"; tegra_sinterface = "serial_a"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "2592"; active_h = "1944"; mode_type = "bayer"; pixel_phase = "bggr"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "2688"; inherent_gain = "1"; mclk_multiplier = "6.67"; pix_clk_hz = "160000000"; gain_factor = "10"; min_gain_val = "10"; max_gain_val = "160"; step_gain_val = "1"; default_gain = "10"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "1816577"; max_framerate = "30000000"; step_framerate = "1"; default_framerate = "30000000"; exposure_factor = "1000000"; min_exp_time = "34"; max_exp_time = "550385"; step_exp_time = "1"; default_exp_time = "33334"; embedded_metadata_height = "0"; }; mode1 { mclk_khz = "24000"; num_lanes = "2"; tegra_sinterface = "serial_a"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "2592"; active_h = "1458"; mode_type = "bayer"; pixel_phase = "bggr"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "2688"; inherent_gain = "1"; mclk_multiplier = "6.67"; pix_clk_hz = "160000000"; gain_factor = "10"; min_gain_val = "10"; max_gain_val = "160"; step_gain_val = "1"; default_gain = "10"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "1816577"; max_framerate = "30000000"; step_framerate = "1"; default_framerate = "30000000"; exposure_factor = "1000000"; min_exp_time = "34"; max_exp_time = "550385"; step_exp_time = "1"; default_exp_time = "33334"; embedded_metadata_height = "0"; }; mode2 { mclk_khz = "24000"; num_lanes = "2"; tegra_sinterface = "serial_a"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "1280"; active_h = "720"; mode_type = "bayer"; pixel_phase = "bggr"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "1752"; inherent_gain = "1"; mclk_multiplier = "6.67"; pix_clk_hz = "160000000"; gain_factor = "10"; min_gain_val = "10"; max_gain_val = "160"; step_gain_val = "1"; default_gain = "10"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "2787078"; max_framerate = "120000000"; step_framerate = "1"; default_framerate = "120000000"; exposure_factor = "1000000"; min_exp_time = "22"; max_exp_time = "358733"; step_exp_time = "1"; default_exp_time = "8334"; embedded_metadata_height = "0"; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; e3333_ov5693_out0: endpoint { port-index = <0>; bus-width = <2>; remote-endpoint = <&e3333_csi_in0>; }; }; }; }; }; i2c@1 { ov5693_b@36 { compatible = "nvidia,ov5693"; reg = <0x36>; devnode = "video1"; physical_w = "3.674"; physical_h = "2.738"; avdd-reg = "vana"; iovdd-reg = "vif"; has-eeprom = "1"; # 532 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e3333-a00.dtsi" mode0 { mclk_khz = "24000"; num_lanes = "2"; tegra_sinterface = "serial_b"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "2592"; active_h = "1944"; mode_type = "bayer"; pixel_phase = "bggr"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "2688"; inherent_gain = "1"; mclk_multiplier = "6.67"; pix_clk_hz = "160000000"; gain_factor = "10"; min_gain_val = "10"; max_gain_val = "160"; step_gain_val = "1"; default_gain = "10"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "1816577"; max_framerate = "30000000"; step_framerate = "1"; default_framerate = "30000000"; exposure_factor = "1000000"; min_exp_time = "34"; max_exp_time = "550385"; step_exp_time = "1"; default_exp_time = "33334"; embedded_metadata_height = "0"; }; mode1 { mclk_khz = "24000"; num_lanes = "2"; tegra_sinterface = "serial_b"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "2592"; active_h = "1458"; mode_type = "bayer"; pixel_phase = "bggr"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "2688"; inherent_gain = "1"; mclk_multiplier = "6.67"; pix_clk_hz = "160000000"; gain_factor = "10"; min_gain_val = "10"; max_gain_val = "160"; step_gain_val = "1"; default_gain = "10"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "1816577"; max_framerate = "30000000"; step_framerate = "1"; default_framerate = "30000000"; exposure_factor = "1000000"; min_exp_time = "34"; max_exp_time = "550385"; step_exp_time = "1"; default_exp_time = "33334"; embedded_metadata_height = "0"; }; mode2 { mclk_khz = "24000"; num_lanes = "2"; tegra_sinterface = "serial_b"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "1280"; active_h = "720"; mode_type = "bayer"; pixel_phase = "bggr"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "1752"; inherent_gain = "1"; mclk_multiplier = "6.67"; pix_clk_hz = "160000000"; gain_factor = "10"; min_gain_val = "10"; max_gain_val = "160"; step_gain_val = "1"; default_gain = "10"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "2787078"; max_framerate = "120000000"; step_framerate = "1"; default_framerate = "120000000"; exposure_factor = "1000000"; min_exp_time = "22"; max_exp_time = "358733"; step_exp_time = "1"; default_exp_time = "8334"; embedded_metadata_height = "0"; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; e3333_ov5693_out1: endpoint { port-index = <1>; bus-width = <2>; remote-endpoint = <&e3333_csi_in1>; }; }; }; }; }; i2c@2 { ov5693_c@36 { compatible = "nvidia,ov5693"; reg = <0x36>; devnode = "video2"; physical_w = "3.674"; physical_h = "2.738"; avdd-reg = "vana"; iovdd-reg = "vif"; has-eeprom = "1"; # 760 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e3333-a00.dtsi" mode0 { mclk_khz = "24000"; num_lanes = "2"; tegra_sinterface = "serial_c"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "2592"; active_h = "1944"; mode_type = "bayer"; pixel_phase = "bggr"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "2688"; inherent_gain = "1"; mclk_multiplier = "6.67"; pix_clk_hz = "160000000"; gain_factor = "10"; min_gain_val = "10"; max_gain_val = "160"; step_gain_val = "1"; default_gain = "10"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "1816577"; max_framerate = "30000000"; step_framerate = "1"; default_framerate = "30000000"; exposure_factor = "1000000"; min_exp_time = "34"; max_exp_time = "550385"; step_exp_time = "1"; default_exp_time = "33334"; embedded_metadata_height = "0"; }; mode1 { mclk_khz = "24000"; num_lanes = "2"; tegra_sinterface = "serial_c"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "2592"; active_h = "1458"; mode_type = "bayer"; pixel_phase = "bggr"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "2688"; inherent_gain = "1"; mclk_multiplier = "6.67"; pix_clk_hz = "160000000"; gain_factor = "10"; min_gain_val = "10"; max_gain_val = "160"; step_gain_val = "1"; default_gain = "10"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "1816577"; max_framerate = "30000000"; step_framerate = "1"; default_framerate = "30000000"; exposure_factor = "1000000"; min_exp_time = "34"; max_exp_time = "550385"; step_exp_time = "1"; default_exp_time = "33334"; embedded_metadata_height = "0"; }; mode2 { mclk_khz = "24000"; num_lanes = "2"; tegra_sinterface = "serial_c"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "1280"; active_h = "720"; mode_type = "bayer"; pixel_phase = "bggr"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "1752"; inherent_gain = "1"; mclk_multiplier = "6.67"; pix_clk_hz = "160000000"; gain_factor = "10"; min_gain_val = "10"; max_gain_val = "160"; step_gain_val = "1"; default_gain = "10"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "2787078"; max_framerate = "120000000"; step_framerate = "1"; default_framerate = "120000000"; exposure_factor = "1000000"; min_exp_time = "22"; max_exp_time = "358733"; step_exp_time = "1"; default_exp_time = "8334"; embedded_metadata_height = "0"; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; e3333_ov5693_out2: endpoint { port-index = <2>; bus-width = <2>; remote-endpoint = <&e3333_csi_in2>; }; }; }; }; }; i2c@3 { ov5693_d@36 { compatible = "nvidia,ov5693"; reg = <0x36>; devnode = "video3"; physical_w = "3.674"; physical_h = "2.738"; avdd-reg = "vana"; iovdd-reg = "vif"; has-eeprom = "1"; # 988 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e3333-a00.dtsi" mode0 { mclk_khz = "24000"; num_lanes = "2"; tegra_sinterface = "serial_d"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "2592"; active_h = "1944"; mode_type = "bayer"; pixel_phase = "bggr"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "2688"; inherent_gain = "1"; mclk_multiplier = "6.67"; pix_clk_hz = "160000000"; gain_factor = "10"; min_gain_val = "10"; max_gain_val = "160"; step_gain_val = "1"; default_gain = "10"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "1816577"; max_framerate = "30000000"; step_framerate = "1"; default_framerate = "30000000"; exposure_factor = "1000000"; min_exp_time = "34"; max_exp_time = "550385"; step_exp_time = "1"; default_exp_time = "33334"; embedded_metadata_height = "0"; }; mode1 { mclk_khz = "24000"; num_lanes = "2"; tegra_sinterface = "serial_d"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "2592"; active_h = "1458"; mode_type = "bayer"; pixel_phase = "bggr"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "2688"; inherent_gain = "1"; mclk_multiplier = "6.67"; pix_clk_hz = "160000000"; gain_factor = "10"; min_gain_val = "10"; max_gain_val = "160"; step_gain_val = "1"; default_gain = "10"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "1816577"; max_framerate = "30000000"; step_framerate = "1"; default_framerate = "30000000"; exposure_factor = "1000000"; min_exp_time = "34"; max_exp_time = "550385"; step_exp_time = "1"; default_exp_time = "33334"; embedded_metadata_height = "0"; }; mode2 { mclk_khz = "24000"; num_lanes = "2"; tegra_sinterface = "serial_d"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "1280"; active_h = "720"; mode_type = "bayer"; pixel_phase = "bggr"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "1752"; inherent_gain = "1"; mclk_multiplier = "6.67"; pix_clk_hz = "160000000"; gain_factor = "10"; min_gain_val = "10"; max_gain_val = "160"; step_gain_val = "1"; default_gain = "10"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "2787078"; max_framerate = "120000000"; step_framerate = "1"; default_framerate = "120000000"; exposure_factor = "1000000"; min_exp_time = "22"; max_exp_time = "358733"; step_exp_time = "1"; default_exp_time = "8334"; embedded_metadata_height = "0"; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; e3333_ov5693_out3: endpoint { port-index = <3>; bus-width = <2>; remote-endpoint = <&e3333_csi_in3>; }; }; }; }; }; i2c@4 { ov5693_e@36 { compatible = "nvidia,ov5693"; reg = <0x36>; devnode = "video4"; physical_w = "3.674"; physical_h = "2.738"; avdd-reg = "vana"; iovdd-reg = "vif"; has-eeprom = "1"; # 1216 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e3333-a00.dtsi" mode0 { mclk_khz = "24000"; num_lanes = "2"; tegra_sinterface = "serial_e"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "2592"; active_h = "1944"; mode_type = "bayer"; pixel_phase = "bggr"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "2688"; inherent_gain = "1"; mclk_multiplier = "6.67"; pix_clk_hz = "160000000"; gain_factor = "10"; min_gain_val = "10"; max_gain_val = "160"; step_gain_val = "1"; default_gain = "10"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "1816577"; max_framerate = "30000000"; step_framerate = "1"; default_framerate = "30000000"; exposure_factor = "1000000"; min_exp_time = "34"; max_exp_time = "550385"; step_exp_time = "1"; default_exp_time = "33334"; embedded_metadata_height = "0"; }; mode1 { mclk_khz = "24000"; num_lanes = "2"; tegra_sinterface = "serial_e"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "2592"; active_h = "1458"; mode_type = "bayer"; pixel_phase = "bggr"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "2688"; inherent_gain = "1"; mclk_multiplier = "6.67"; pix_clk_hz = "160000000"; gain_factor = "10"; min_gain_val = "10"; max_gain_val = "160"; step_gain_val = "1"; default_gain = "10"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "1816577"; max_framerate = "30000000"; step_framerate = "1"; default_framerate = "30000000"; exposure_factor = "1000000"; min_exp_time = "34"; max_exp_time = "550385"; step_exp_time = "1"; default_exp_time = "33334"; embedded_metadata_height = "0"; }; mode2 { mclk_khz = "24000"; num_lanes = "2"; tegra_sinterface = "serial_e"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "1280"; active_h = "720"; mode_type = "bayer"; pixel_phase = "bggr"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "1752"; inherent_gain = "1"; mclk_multiplier = "6.67"; pix_clk_hz = "160000000"; gain_factor = "10"; min_gain_val = "10"; max_gain_val = "160"; step_gain_val = "1"; default_gain = "10"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "2787078"; max_framerate = "120000000"; step_framerate = "1"; default_framerate = "120000000"; exposure_factor = "1000000"; min_exp_time = "22"; max_exp_time = "358733"; step_exp_time = "1"; default_exp_time = "8334"; embedded_metadata_height = "0"; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; e3333_ov5693_out4: endpoint { port-index = <4>; bus-width = <2>; remote-endpoint = <&e3333_csi_in4>; }; }; }; }; }; i2c@5 { ov5693_g@36 { compatible = "nvidia,ov5693"; reg = <0x36>; devnode = "video5"; physical_w = "3.674"; physical_h = "2.738"; avdd-reg = "vana"; iovdd-reg = "vif"; has-eeprom = "1"; # 1444 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e3333-a00.dtsi" mode0 { mclk_khz = "24000"; num_lanes = "2"; tegra_sinterface = "serial_g"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "2592"; active_h = "1944"; mode_type = "bayer"; pixel_phase = "bggr"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "2688"; inherent_gain = "1"; mclk_multiplier = "6.67"; pix_clk_hz = "160000000"; gain_factor = "10"; min_gain_val = "10"; max_gain_val = "160"; step_gain_val = "1"; default_gain = "10"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "1816577"; max_framerate = "30000000"; step_framerate = "1"; default_framerate = "30000000"; exposure_factor = "1000000"; min_exp_time = "34"; max_exp_time = "550385"; step_exp_time = "1"; default_exp_time = "33334"; embedded_metadata_height = "0"; }; mode1 { mclk_khz = "24000"; num_lanes = "2"; tegra_sinterface = "serial_g"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "2592"; active_h = "1458"; mode_type = "bayer"; pixel_phase = "bggr"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "2688"; inherent_gain = "1"; mclk_multiplier = "6.67"; pix_clk_hz = "160000000"; gain_factor = "10"; min_gain_val = "10"; max_gain_val = "160"; step_gain_val = "1"; default_gain = "10"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "1816577"; max_framerate = "30000000"; step_framerate = "1"; default_framerate = "30000000"; exposure_factor = "1000000"; min_exp_time = "34"; max_exp_time = "550385"; step_exp_time = "1"; default_exp_time = "33334"; embedded_metadata_height = "0"; }; mode2 { mclk_khz = "24000"; num_lanes = "2"; tegra_sinterface = "serial_g"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "1280"; active_h = "720"; mode_type = "bayer"; pixel_phase = "bggr"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "1752"; inherent_gain = "1"; mclk_multiplier = "6.67"; pix_clk_hz = "160000000"; gain_factor = "10"; min_gain_val = "10"; max_gain_val = "160"; step_gain_val = "1"; default_gain = "10"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "2787078"; max_framerate = "120000000"; step_framerate = "1"; default_framerate = "120000000"; exposure_factor = "1000000"; min_exp_time = "22"; max_exp_time = "358733"; step_exp_time = "1"; default_exp_time = "8334"; embedded_metadata_height = "0"; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; e3333_ov5693_out5: endpoint { port-index = <5>; bus-width = <2>; remote-endpoint = <&e3333_csi_in5>; }; }; }; }; }; }; }; e3333_lens_ov5693@P5V27C { min_focus_distance = "0.0"; hyper_focal = "0.0"; focal_length = "2.67"; f_number = "2.0"; aperture = "2.0"; }; tegra-camera-platform { compatible = "nvidia, tegra-camera-platform"; # 1620 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e3333-a00.dtsi" num_csi_lanes = <12>; max_lane_speed = <1500000>; min_bits_per_pixel = <10>; vi_peak_byte_per_pixel = <2>; vi_bw_margin_pct = <25>; max_pixel_rate = <160000>; isp_peak_byte_per_pixel = <5>; isp_bw_margin_pct = <25>; # 1637 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e3333-a00.dtsi" modules { module0 { badge = "e3333_bottomleft_P5V27C"; position = "bottomleft"; orientation = "1"; drivernode0 { pcl_id = "v4l2_sensor"; devname = "ov5693 30-0036"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9548@77/i2c@0/ov5693_a@36"; }; drivernode1 { pcl_id = "v4l2_lens"; proc-device-tree = "/proc/device-tree/e3333_lens_ov5693@P5V27C/"; }; }; module1 { badge = "e3333_centerleft_P5V27C"; position = "centerleft"; orientation = "1"; drivernode0 { pcl_id = "v4l2_sensor"; devname = "ov5693 31-0036"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9548@77/i2c@1/ov5693_b@36"; }; drivernode1 { pcl_id = "v4l2_lens"; proc-device-tree = "/proc/device-tree/e3333_lens_ov5693@P5V27C/"; }; }; module2 { badge = "e3333_centerright_P5V27C"; position = "centerright"; orientation = "1"; drivernode0 { pcl_id = "v4l2_sensor"; devname = "ov5693 32-0036"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9548@77/i2c@2/ov5693_c@36"; }; drivernode1 { pcl_id = "v4l2_lens"; proc-device-tree = "/proc/device-tree/e3333_lens_ov5693@P5V27C/"; }; }; module3 { badge = "e3333_topleft_P5V27C"; position = "topleft"; orientation = "1"; drivernode0 { pcl_id = "v4l2_sensor"; devname = "ov5693 33-0036"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9548@77/i2c@3/ov5693_d@36"; }; drivernode1 { pcl_id = "v4l2_lens"; proc-device-tree = "/proc/device-tree/e3333_lens_ov5693@P5V27C/"; }; }; module4 { badge = "e3333_bottomright_P5V27C"; position = "bottomright"; orientation = "1"; drivernode0 { pcl_id = "v4l2_sensor"; devname = "ov5693 34-0036"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9548@77/i2c@4/ov5693_e@36"; }; drivernode1 { pcl_id = "v4l2_lens"; proc-device-tree = "/proc/device-tree/e3333_lens_ov5693@P5V27C/"; }; }; module5 { badge = "e3333_topright_P5V27C"; position = "topright"; orientation = "1"; drivernode0 { pcl_id = "v4l2_sensor"; devname = "ov5693 35-0036"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9548@77/i2c@5/ov5693_g@36"; }; drivernode1 { pcl_id = "v4l2_lens"; proc-device-tree = "/proc/device-tree/e3333_lens_ov5693@P5V27C/"; }; }; }; }; }; # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-e3333-a00.dtsi" 2 # 26 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-e3333-a00.dtsi" / { gpio@2200000 { camera-control-output-low { gpio-hog; output-low; gpios = <((7 * 8) + 3) 0 ((7 * 8) + 6) 0 ((19 * 8) + 6) 0 ((19 * 8) + 5) 0>; label = "cam0-rst", "cam0-pwdn", "cam1-rst", "cam1-pwdn"; }; }; i2c@3180000 { tca6408_21: tca6408@21 { compatible = "ti,tca6408"; gpio-controller; #gpio-cells = <2>; reg = <0x21>; vcc-supply = <&p2822_vdd_1v8_cvb>; tca6408_21_outlow { # 56 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-e3333-a00.dtsi" gpio-hog; gpios = <0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0>; output-low; label = "tca6408_21_outlow_0", "tca6408_21_outlow_1", "tca6408_21_outlow_2", "tca6408_21_outlow_3", "tca6408_21_outlow_4", "tca6408_21_outlow_5", "tca6408_21_outlow_6", "tca6408_21_outlow_7"; }; tca6408_21_outhigh { status = "disabled"; }; tca6408_21_input { status = "disabled"; }; }; tca9548_77: tca9548@77 { compatible = "nxp,pca9548"; reg = <0x77>; #address-cells = <1>; #size-cells = <0>; vcc-supply = <&p2822_vdd_1v8_cvb>; skip_mux_detect; force_bus_start = <(0x1E + 0)>; i2c@0 { reg = <0>; i2c-mux,deselect-on-exit; #address-cells = <1>; #size-cells = <0>; ov5693_a@36 { clocks = <&bpmp_clks 36U>, <&bpmp_clks 102U>; clock-names = "extperiph1", "pllp_grtba"; mclk = "extperiph1"; clock-frequency = <24000000>; reset-gpios = <&tegra_main_gpio ((7 * 8) + 3) 0>; pwdn-gpios = <&tegra_main_gpio ((7 * 8) + 6) 0>; vif-supply = <&p2822_vdd_1v8_cvb>; }; }; i2c@1 { reg = <1>; i2c-mux,deselect-on-exit; #address-cells = <1>; #size-cells = <0>; ov5693_b@36 { clocks = <&bpmp_clks 36U>, <&bpmp_clks 102U>; clock-names = "extperiph1", "pllp_grtba"; mclk = "extperiph1"; clock-frequency = <24000000>; reset-gpios = <&tegra_main_gpio ((19 * 8) + 6) 0>; pwdn-gpios = <&tegra_main_gpio ((19 * 8) + 5) 0>; vif-supply = <&p2822_vdd_1v8_cvb>; }; }; i2c@2 { reg = <2>; i2c-mux,deselect-on-exit; #address-cells = <1>; #size-cells = <0>; ov5693_c@36 { clocks = <&bpmp_clks 36U>, <&bpmp_clks 102U>; clock-names = "extperiph1", "pllp_grtba"; mclk = "extperiph1"; clock-frequency = <24000000>; pwdn-gpios = <&tca6408_21 0 0>; reset-gpios = <&tca6408_21 1 0>; vif-supply = <&p2822_vdd_1v8_cvb>; }; }; i2c@3 { reg = <3>; i2c-mux,deselect-on-exit; #address-cells = <1>; #size-cells = <0>; ov5693_d@36 { clocks = <&bpmp_clks 37U>, <&bpmp_clks 102U>; clock-names = "extperiph2", "pllp_grtba"; mclk = "extperiph2"; clock-frequency = <24000000>; pwdn-gpios = <&tca6408_21 2 0>; reset-gpios = <&tca6408_21 3 0>; vif-supply = <&p2822_vdd_1v8_cvb>; }; }; i2c@4 { reg = <4>; i2c-mux,deselect-on-exit; #address-cells = <1>; #size-cells = <0>; ov5693_e@36 { clocks = <&bpmp_clks 37U>, <&bpmp_clks 102U>; clock-names = "extperiph2", "pllp_grtba"; mclk = "extperiph2"; clock-frequency = <24000000>; pwdn-gpios = <&tca6408_21 4 0>; reset-gpios = <&tca6408_21 5 0>; vif-supply = <&p2822_vdd_1v8_cvb>; }; }; i2c@5 { reg = <5>; i2c-mux,deselect-on-exit; #address-cells = <1>; #size-cells = <0>; ov5693_g@36 { clocks = <&bpmp_clks 37U>, <&bpmp_clks 102U>; clock-names = "extperiph2", "pllp_grtba"; mclk = "extperiph2"; clock-frequency = <24000000>; pwdn-gpios = <&tca6408_21 6 0>; reset-gpios = <&tca6408_21 7 0>; vif-supply = <&p2822_vdd_1v8_cvb>; }; }; }; }; }; # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-camera-modules.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-e3331-a00.dtsi" 1 # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-e3331-a00.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e3331-a00.dtsi" 1 # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e3331-a00.dtsi" / { host1x { vi@15c10000 { num-channels = <1>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; e3331_vi_in0: endpoint { port-index = <0>; bus-width = <3>; remote-endpoint = <&e3331_csi_out0>; }; }; }; }; nvcsi@15a00000 { num-channels = <1>; channel@0 { reg = <0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; e3331_csi_in0: endpoint@0 { port-index = <0>; bus-width = <3>; remote-endpoint = <&e3331_imx318_out0>; }; }; port@1 { reg = <1>; e3331_csi_out0: endpoint@1 { remote-endpoint = <&e3331_vi_in0>; }; }; }; }; }; }; i2c@3180000 { tca9546@70 { i2c@0 { imx318_a@10 { compatible = "nvidia,imx318"; reg = <0x10>; physical_w = "6.811"; physical_h = "5.254"; sensor_model = "imx318"; avdd-reg = "vana"; iovdd-reg = "vif"; dvdd-reg = "vdig"; has-eeprom; # 163 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e3331-a00.dtsi" mode0 { mclk_khz = "24000"; num_lanes = "3"; phy_mode = "CPHY"; tegra_sinterface = "serial_a"; discontinuous_clk = "no"; dpcm_enable = "false"; cil_settletime = "20"; active_w = "5488"; active_h = "4112"; mode_type = "bayer"; pixel_phase = "bggr"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "5488"; inherent_gain = "1"; mclk_multiplier = "31.25"; pix_clk_hz = "750000000"; gain_factor = "16"; framerate_factor = "1000000"; exposure_factor = "1000000"; min_gain_val = "16"; max_gain_val = "256"; step_gain_val = "1"; default_gain = "16"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; min_framerate = "1500000"; max_framerate = "30000000"; step_framerate = "1"; default_framerate= "30000000"; min_exp_time = "34"; max_exp_time = "550385"; step_exp_time = "1"; default_exp_time = "33334"; embedded_metadata_height = "0"; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; e3331_imx318_out0: endpoint { port-index = <0>; bus-width = <3>; remote-endpoint = <&e3331_csi_in0>; }; }; }; }; }; }; }; tegra-camera-platform { compatible = "nvidia, tegra-camera-platform"; # 252 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e3331-a00.dtsi" num_csi_lanes = <3>; max_lane_speed = <1500000>; min_bits_per_pixel = <10>; vi_peak_byte_per_pixel = <2>; vi_bw_margin_pct = <25>; max_pixel_rate = <800000>; isp_peak_byte_per_pixel = <5>; isp_bw_margin_pct = <25>; # 269 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e3331-a00.dtsi" modules { module0 { badge = "e3331_rear_22N02A"; position = "rear"; orientation = "1"; drivernode0 { pcl_id = "v4l2_sensor"; devname = "imx318 30-0010"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9546@70/i2c@0/imx318_a@10"; }; }; }; }; }; # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-e3331-a00.dtsi" 2 / { gpio@2200000 { camera-control-output-low { gpio-hog; output-low; gpios = <((7 * 8) + 3) 0>; label = "cam0-rst"; }; }; i2c@3180000 { tca9546_70: tca9546@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; #size-cells = <0>; vcc-supply = <&p2822_vdd_1v8_cvb>; skip_mux_detect; force_bus_start = <(0x1E + 0)>; i2c@0 { reg = <0>; i2c-mux,deselect-on-exit; #address-cells = <1>; #size-cells = <0>; imx318_a@10 { clocks = <&bpmp_clks 36U>, <&bpmp_clks 102U>; clock-names = "extperiph1", "pllp_grtba"; mclk = "extperiph1"; clock-frequency = <24000000>; reset-gpios = <&tegra_main_gpio ((7 * 8) + 3) 0>; vif-supply = <&p2822_vdd_1v8_cvb>; }; }; }; }; }; # 19 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-camera-modules.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-imx274-dual.dtsi" 1 # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-imx274-dual.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-imx274-dual.dtsi" 1 # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-imx274-dual.dtsi" / { host1x { vi@15c10000 { num-channels = <2>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; liimx274_vi_in0: endpoint { port-index = <0>; bus-width = <4>; remote-endpoint = <&liimx274_csi_out0>; }; }; port@1 { reg = <1>; liimx274_vi_in1: endpoint { port-index = <2>; bus-width = <4>; remote-endpoint = <&liimx274_csi_out1>; }; }; }; }; nvcsi@15a00000 { num-channels = <2>; #address-cells = <1>; #size-cells = <0>; channel@0 { reg = <0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; liimx274_csi_in0: endpoint@0 { port-index = <0>; bus-width = <4>; remote-endpoint = <&liimx274_imx274_out0>; }; }; port@1 { reg = <1>; liimx274_csi_out0: endpoint@1 { remote-endpoint = <&liimx274_vi_in0>; }; }; }; }; channel@1 { reg = <1>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; liimx274_csi_in1: endpoint@2 { port-index = <2>; bus-width = <4>; remote-endpoint = <&liimx274_imx274_out1>; }; }; port@1 { reg = <1>; liimx274_csi_out1: endpoint@3 { remote-endpoint = <&liimx274_vi_in1>; }; }; }; }; }; }; i2c@3180000 { tca9546@70 { i2c@0 { imx274_a@1a { compatible = "nvidia,imx274"; reg = <0x1a>; devnode = "video0"; physical_w = "3.674"; physical_h = "2.738"; sensor_model = "imx274"; avdd-reg = "vana"; iovdd-reg = "vif"; delayed_gain = "true"; has-eeprom; fuse_id_start_addr = <91>; # 230 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-imx274-dual.dtsi" mode0 { mclk_khz = "24000"; num_lanes = "4"; tegra_sinterface = "serial_a"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "3840"; active_h = "2160"; mode_type = "bayer"; pixel_phase = "rggb"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "4208"; inherent_gain = "1"; mclk_multiplier = "24"; pix_clk_hz = "576000000"; gain_factor = "1000000"; min_gain_val = "1000000"; max_gain_val = "44400000"; step_gain_val = "1"; default_gain = "1000000"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "1500000"; max_framerate = "60000000"; step_framerate = "1"; default_framerate= "60000000"; exposure_factor = "1000000"; min_exp_time = "44"; max_exp_time = "478696"; step_exp_time = "1"; default_exp_time = "16667"; embedded_metadata_height = "1"; }; mode1 { mclk_khz = "24000"; num_lanes = "4"; tegra_sinterface = "serial_a"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; dynamic_pixel_bit_depth = "10"; csi_pixel_bit_depth = "10"; mode_type = "bayer"; pixel_phase = "rggb"; active_w = "1920"; active_h = "1080"; readout_orientation = "0"; line_length = "4160"; inherent_gain = "1"; mclk_multiplier = "24"; pix_clk_hz = "576000000"; gain_factor = "1000000"; min_gain_val = "1000000"; max_gain_val = "177000000"; step_gain_val = "1"; default_gain = "1000000"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "1500000"; max_framerate = "60000000"; step_framerate = "1"; default_framerate= "60000000"; exposure_factor = "1000000"; min_exp_time = "58"; max_exp_time = "184611"; step_exp_time = "1"; default_exp_time = "16667"; embedded_metadata_height = "1"; }; mode2 { mclk_khz = "24000"; num_lanes = "4"; tegra_sinterface = "serial_a"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; dynamic_pixel_bit_depth = "10"; csi_pixel_bit_depth = "10"; mode_type = "bayer_wdr_dol"; pixel_phase = "rggb"; active_w = "3856"; active_h = "4448"; readout_orientation = "0"; line_length = "4208"; inherent_gain = "1"; mclk_multiplier = "24"; pix_clk_hz = "576000000"; gain_factor = "1000000"; min_gain_val = "1000000"; max_gain_val = "30000000"; step_gain_val = "1"; default_gain = "1000000"; min_hdr_ratio = "32"; max_hdr_ratio = "32"; framerate_factor = "1000000"; min_framerate = "1500000"; max_framerate = "30000000"; step_framerate = "1"; default_framerate= "30000000"; exposure_factor = "1000000"; min_exp_time = "864"; max_exp_time = "20480"; step_exp_time = "1"; default_exp_time = "20480"; embedded_metadata_height = "1"; num_of_exposure = "2"; num_of_ignored_lines = "14"; num_of_lines_offset_0 = "50"; num_of_ignored_pixels = "4"; num_of_left_margin_pixels = "12"; num_of_right_margin_pixels = "0"; }; mode3 { mclk_khz = "24000"; num_lanes = "4"; tegra_sinterface = "serial_a"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; dynamic_pixel_bit_depth = "10"; csi_pixel_bit_depth = "10"; mode_type = "bayer_wdr_dol"; pixel_phase = "rggb"; active_w = "1936"; active_h = "2264"; readout_orientation = "0"; line_length = "4160"; inherent_gain = "1"; mclk_multiplier = "24"; pix_clk_hz = "576000000"; gain_factor = "1000000"; min_gain_val = "1000000"; max_gain_val = "177000000"; step_gain_val = "1"; default_gain = "1000000"; min_hdr_ratio = "32"; max_hdr_ratio = "32"; framerate_factor = "1000000"; min_framerate = "1500000"; max_framerate = "60000000"; step_framerate = "1"; default_framerate= "60000000"; exposure_factor = "1000000"; min_exp_time = "859"; max_exp_time = "15649"; step_exp_time = "1"; default_exp_time = "15649"; embedded_metadata_height = "1"; num_of_exposure = "2"; num_of_ignored_lines = "14"; num_of_lines_offset_0 = "38"; num_of_ignored_pixels = "4"; num_of_left_margin_pixels = "6"; num_of_right_margin_pixels = "6"; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; liimx274_imx274_out0: endpoint { port-index = <0>; bus-width = <4>; remote-endpoint = <&liimx274_csi_in0>; }; }; }; }; }; i2c@1 { imx274_c@1a { compatible = "nvidia,imx274"; reg = <0x1a>; devnode = "video1"; physical_w = "3.674"; physical_h = "2.738"; sensor_model = "imx274"; avdd-reg = "vana"; iovdd-reg = "vif"; delayed_gain = "true"; has-eeprom; fuse_id_start_addr = <99>; # 553 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-imx274-dual.dtsi" mode0 { mclk_khz = "24000"; num_lanes = "4"; tegra_sinterface = "serial_c"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "3840"; active_h = "2160"; mode_type = "bayer"; pixel_phase = "rggb"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "4208"; inherent_gain = "1"; mclk_multiplier = "24"; pix_clk_hz = "576000000"; gain_factor = "1000000"; min_gain_val = "1000000"; max_gain_val = "44400000"; step_gain_val = "1"; default_gain = "1000000"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "1500000"; max_framerate = "60000000"; step_framerate = "1"; default_framerate= "60000000"; exposure_factor = "1000000"; min_exp_time = "44"; max_exp_time = "478696"; step_exp_time = "1"; default_exp_time = "16667"; embedded_metadata_height = "1"; }; mode1 { mclk_khz = "24000"; num_lanes = "4"; tegra_sinterface = "serial_c"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; dynamic_pixel_bit_depth = "10"; csi_pixel_bit_depth = "10"; mode_type = "bayer"; pixel_phase = "rggb"; active_w = "1920"; active_h = "1080"; readout_orientation = "0"; line_length = "4160"; inherent_gain = "1"; mclk_multiplier = "24"; pix_clk_hz = "576000000"; gain_factor = "1000000"; min_gain_val = "1000000"; max_gain_val = "177000000"; step_gain_val = "1"; default_gain = "1000000"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "1500000"; max_framerate = "60000000"; step_framerate = "1"; default_framerate= "60000000"; exposure_factor = "1000000"; min_exp_time = "58"; max_exp_time = "184611"; step_exp_time = "1"; default_exp_time = "16667"; embedded_metadata_height = "1"; }; mode2 { mclk_khz = "24000"; num_lanes = "4"; tegra_sinterface = "serial_c"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; dynamic_pixel_bit_depth = "10"; csi_pixel_bit_depth = "10"; mode_type = "bayer_wdr_dol"; pixel_phase = "rggb"; active_w = "3856"; active_h = "4448"; readout_orientation = "0"; line_length = "4208"; inherent_gain = "1"; mclk_multiplier = "24"; pix_clk_hz = "576000000"; gain_factor = "1000000"; min_gain_val = "1000000"; max_gain_val = "30000000"; step_gain_val = "1"; default_gain = "1000000"; min_hdr_ratio = "32"; max_hdr_ratio = "32"; framerate_factor = "1000000"; min_framerate = "1500000"; max_framerate = "30000000"; step_framerate = "1"; default_framerate= "30000000"; exposure_factor = "1000000"; min_exp_time = "864"; max_exp_time = "20480"; step_exp_time = "1"; default_exp_time = "20480"; embedded_metadata_height = "1"; num_of_exposure = "2"; num_of_ignored_lines = "14"; num_of_lines_offset_0 = "50"; num_of_ignored_pixels = "4"; num_of_left_margin_pixels = "12"; num_of_right_margin_pixels = "0"; }; mode3 { mclk_khz = "24000"; num_lanes = "4"; tegra_sinterface = "serial_c"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; dynamic_pixel_bit_depth = "10"; csi_pixel_bit_depth = "10"; mode_type = "bayer_wdr_dol"; pixel_phase = "rggb"; active_w = "1936"; active_h = "2264"; readout_orientation = "0"; line_length = "4160"; inherent_gain = "1"; mclk_multiplier = "24"; pix_clk_hz = "576000000"; gain_factor = "1000000"; min_gain_val = "1000000"; max_gain_val = "177000000"; step_gain_val = "1"; default_gain = "1000000"; min_hdr_ratio = "32"; max_hdr_ratio = "32"; framerate_factor = "1000000"; min_framerate = "1500000"; max_framerate = "60000000"; step_framerate = "1"; default_framerate= "60000000"; exposure_factor = "1000000"; min_exp_time = "859"; max_exp_time = "15649"; step_exp_time = "1"; default_exp_time = "15649"; embedded_metadata_height = "1"; num_of_exposure = "2"; num_of_ignored_lines = "14"; num_of_lines_offset_0 = "38"; num_of_ignored_pixels = "4"; num_of_left_margin_pixels = "6"; num_of_right_margin_pixels = "6"; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; liimx274_imx274_out1: endpoint { port-index = <2>; bus-width = <4>; remote-endpoint = <&liimx274_csi_in1>; }; }; }; }; }; }; }; lens_imx274@A6V26 { min_focus_distance = "0.0"; hyper_focal = "0.0"; focal_length = "5.00"; f_number = "2.0"; aperture = "2.2"; }; }; / { tegra-camera-platform { compatible = "nvidia, tegra-camera-platform"; # 785 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-imx274-dual.dtsi" num_csi_lanes = <8>; max_lane_speed = <1500000>; min_bits_per_pixel = <10>; vi_peak_byte_per_pixel = <2>; vi_bw_margin_pct = <25>; max_pixel_rate = <750000>; isp_peak_byte_per_pixel = <5>; isp_bw_margin_pct = <25>; # 802 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-imx274-dual.dtsi" modules { module0 { badge = "imx274_bottom_A6V26"; position = "bottom"; orientation = "1"; drivernode0 { pcl_id = "v4l2_sensor"; devname = "imx274 30-001a"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9546@70/i2c@0/imx274_a@1a"; }; drivernode1 { pcl_id = "v4l2_lens"; proc-device-tree = "/proc/device-tree/lens_imx274@A6V26/"; }; }; module1 { badge = "imx274_top_A6V26"; position = "top"; orientation = "1"; drivernode0 { pcl_id = "v4l2_sensor"; devname = "imx274 31-001a"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9546@70/i2c@1/imx274_c@1a"; }; drivernode1 { pcl_id = "v4l2_lens"; proc-device-tree = "/proc/device-tree/lens_imx274@A6V26/"; }; }; }; }; }; # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-imx274-dual.dtsi" 2 # 26 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-imx274-dual.dtsi" / { gpio@2200000 { camera-control-output-low { gpio-hog; output-low; gpios = <((7 * 8) + 3) 0 ((7 * 8) + 6) 0>; label = "cam0-rst", "cam0-pwdn"; }; }; i2c@3180000 { tca9546@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; #size-cells = <0>; skip_mux_detect = "yes"; vcc-supply = <&p2822_vdd_1v8_cvb>; vcc_lp = "vcc"; force_bus_start = <(0x1E + 0)>; i2c@0 { reg = <0>; i2c-mux,deselect-on-exit; #address-cells = <1>; #size-cells = <0>; imx274_a@1a { clocks = <&bpmp_clks 36U>, <&bpmp_clks 36U>; clock-names = "extperiph1", "pllp_grtba"; mclk = "extperiph1"; reset-gpios = <&tegra_main_gpio ((7 * 8) + 3) 0>; vif-supply = <&p2822_vdd_1v8_cvb>; }; }; i2c@1 { reg = <1>; i2c-mux,deselect-on-exit; #address-cells = <1>; #size-cells = <0>; imx274_c@1a { clocks = <&bpmp_clks 36U>, <&bpmp_clks 36U>; clock-names = "extperiph1", "pllp_grtba"; mclk = "extperiph1"; reset-gpios = <&tegra_main_gpio ((7 * 8) + 6) 0>; vif-supply = <&p2822_vdd_1v8_cvb>; }; }; }; }; }; # 20 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-camera-modules.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-imx274-a00.dtsi" 1 # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-imx274-a00.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-imx274-a00.dtsi" 1 # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-imx274-a00.dtsi" / { host1x { vi@15c10000 { num-channels = <1>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; liimx274_vi_in0: endpoint { port-index = <0>; bus-width = <4>; remote-endpoint = <&liimx274_csi_out0>; }; }; }; }; nvcsi@15a00000 { num-channels = <1>; #address-cells = <1>; #size-cells = <0>; channel@0 { reg = <0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; liimx274_csi_in0: endpoint@0 { port-index = <0>; bus-width = <4>; remote-endpoint = <&liimx274_imx274_out0>; }; }; port@1 { reg = <1>; liimx274_csi_out0: endpoint@1 { remote-endpoint = <&liimx274_vi_in0>; }; }; }; }; }; }; i2c@3180000 { tca9546@70 { i2c@0 { imx274_a@1a { compatible = "nvidia,imx274"; reg = <0x1a>; devnode = "video0"; physical_w = "3.674"; physical_h = "2.738"; sensor_model = "imx274"; avdd-reg = "vana"; iovdd-reg = "vif"; delayed_gain = "true"; has-eeprom; fuse_id_start_addr = <91>; # 201 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-imx274-a00.dtsi" mode0 { mclk_khz = "24000"; num_lanes = "4"; tegra_sinterface = "serial_a"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "3840"; active_h = "2160"; mode_type = "bayer"; pixel_phase = "rggb"; csi_pixel_bit_depth = "10"; readout_orientation = "0"; line_length = "4208"; inherent_gain = "1"; mclk_multiplier = "24"; pix_clk_hz = "576000000"; gain_factor = "1000000"; min_gain_val = "1000000"; max_gain_val = "44400000"; step_gain_val = "1"; default_gain = "1000000"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "1500000"; max_framerate = "60000000"; step_framerate = "1"; default_framerate= "60000000"; exposure_factor = "1000000"; min_exp_time = "44"; max_exp_time = "478696"; step_exp_time = "1"; default_exp_time = "16667"; embedded_metadata_height = "1"; }; mode1 { mclk_khz = "24000"; num_lanes = "4"; tegra_sinterface = "serial_a"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; dynamic_pixel_bit_depth = "10"; csi_pixel_bit_depth = "10"; mode_type = "bayer"; pixel_phase = "rggb"; active_w = "1920"; active_h = "1080"; readout_orientation = "0"; line_length = "4160"; inherent_gain = "1"; mclk_multiplier = "24"; pix_clk_hz = "576000000"; gain_factor = "1000000"; min_gain_val = "1000000"; max_gain_val = "177000000"; step_gain_val = "1"; default_gain = "1000000"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "1500000"; max_framerate = "60000000"; step_framerate = "1"; default_framerate= "60000000"; exposure_factor = "1000000"; min_exp_time = "58"; max_exp_time = "184611"; step_exp_time = "1"; default_exp_time = "16667"; embedded_metadata_height = "1"; }; mode2 { mclk_khz = "24000"; num_lanes = "4"; tegra_sinterface = "serial_a"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; dynamic_pixel_bit_depth = "10"; csi_pixel_bit_depth = "10"; mode_type = "bayer_wdr_dol"; pixel_phase = "rggb"; active_w = "3856"; active_h = "4448"; readout_orientation = "0"; line_length = "4208"; inherent_gain = "1"; mclk_multiplier = "24"; pix_clk_hz = "576000000"; gain_factor = "1000000"; min_gain_val = "1000000"; max_gain_val = "30000000"; step_gain_val = "1"; default_gain = "1000000"; min_hdr_ratio = "32"; max_hdr_ratio = "32"; framerate_factor = "1000000"; min_framerate = "1500000"; max_framerate = "30000000"; step_framerate = "1"; default_framerate= "30000000"; exposure_factor = "1000000"; min_exp_time = "864"; max_exp_time = "20480"; step_exp_time = "1"; default_exp_time = "20480"; embedded_metadata_height = "1"; num_of_exposure = "2"; num_of_ignored_lines = "14"; num_of_lines_offset_0 = "50"; num_of_ignored_pixels = "4"; num_of_left_margin_pixels = "12"; num_of_right_margin_pixels = "0"; }; mode3 { mclk_khz = "24000"; num_lanes = "4"; tegra_sinterface = "serial_a"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; dynamic_pixel_bit_depth = "10"; csi_pixel_bit_depth = "10"; mode_type = "bayer_wdr_dol"; pixel_phase = "rggb"; active_w = "1936"; active_h = "2264"; readout_orientation = "0"; line_length = "4160"; inherent_gain = "1"; mclk_multiplier = "24"; pix_clk_hz = "576000000"; gain_factor = "1000000"; min_gain_val = "1000000"; max_gain_val = "177000000"; step_gain_val = "1"; default_gain = "1000000"; min_hdr_ratio = "32"; max_hdr_ratio = "32"; framerate_factor = "1000000"; min_framerate = "1500000"; max_framerate = "60000000"; step_framerate = "1"; default_framerate= "60000000"; exposure_factor = "1000000"; min_exp_time = "859"; max_exp_time = "15649"; step_exp_time = "1"; default_exp_time = "15649"; embedded_metadata_height = "1"; num_of_exposure = "2"; num_of_ignored_lines = "14"; num_of_lines_offset_0 = "38"; num_of_ignored_pixels = "4"; num_of_left_margin_pixels = "6"; num_of_right_margin_pixels = "6"; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; liimx274_imx274_out0: endpoint { port-index = <0>; bus-width = <4>; remote-endpoint = <&liimx274_csi_in0>; }; }; }; }; }; }; }; lens_imx274@A6V26 { min_focus_distance = "0.0"; hyper_focal = "0.0"; focal_length = "5.00"; f_number = "2.0"; aperture = "2.2"; }; }; / { tegra-camera-platform { compatible = "nvidia, tegra-camera-platform"; # 433 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-imx274-a00.dtsi" num_csi_lanes = <8>; max_lane_speed = <1500000>; min_bits_per_pixel = <10>; vi_peak_byte_per_pixel = <2>; vi_bw_margin_pct = <25>; max_pixel_rate = <750000>; isp_peak_byte_per_pixel = <5>; isp_bw_margin_pct = <25>; # 450 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-imx274-a00.dtsi" modules { module0 { badge = "imx274_bottom_A6V26"; position = "bottom"; orientation = "1"; drivernode0 { pcl_id = "v4l2_sensor"; devname = "imx274 30-001a"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9546@70/i2c@0/imx274_a@1a"; }; drivernode1 { pcl_id = "v4l2_lens"; proc-device-tree = "/proc/device-tree/lens_imx274@A6V26/"; }; }; }; }; }; # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-imx274-a00.dtsi" 2 # 26 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-imx274-a00.dtsi" / { gpio@2200000 { camera-control-output-low { gpio-hog; output-low; gpios = <((7 * 8) + 3) 0 ((7 * 8) + 6) 0>; label = "cam0-rst", "cam0-pwdn"; }; }; i2c@3180000 { tca9546@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; #size-cells = <0>; skip_mux_detect = "yes"; vcc-supply = <&p2822_vdd_1v8_cvb>; vcc_lp = "vcc"; force_bus_start = <(0x1E + 0)>; i2c@0 { reg = <0>; i2c-mux,deselect-on-exit; #address-cells = <1>; #size-cells = <0>; pca9570_a@24 { compatible = "nvidia,pca9570"; reg = <0x24>; channel = "a"; drive_ic = "DRV8838"; }; imx274_a@1a { clocks = <&bpmp_clks 36U>, <&bpmp_clks 36U>; clock-names = "extperiph1", "pllp_grtba"; mclk = "extperiph1"; reset-gpios = <&tegra_main_gpio ((7 * 8) + 3) 0>; vif-supply = <&p2822_vdd_1v8_cvb>; }; }; }; }; }; # 21 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-camera-modules.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-imx185-a00.dtsi" 1 # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-imx185-a00.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-imx185-a00.dtsi" 1 # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-imx185-a00.dtsi" / { host1x { vi@15c10000 { num-channels = <1>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; liimx185_vi_in0: endpoint { port-index = <0>; bus-width = <4>; remote-endpoint = <&liimx185_csi_out0>; }; }; }; }; nvcsi@15a00000 { num-channels = <1>; #address-cells = <1>; #size-cells = <0>; channel@0 { reg = <0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; liimx185_csi_in0: endpoint@0 { port-index = <0>; bus-width = <4>; remote-endpoint = <&liimx185_imx185_out0>; }; }; port@1 { reg = <1>; liimx185_csi_out0: endpoint@1 { remote-endpoint = <&liimx185_vi_in0>; }; }; }; }; }; }; i2c@3180000 { tca9546@70 { i2c@0 { imx185_a@1a { compatible = "nvidia,imx185"; reg = <0x1a>; devnode = "video0"; physical_w = "15.0"; physical_h = "12.5"; sensor_model ="imx185"; post_crop_frame_drop = "0"; use_decibel_gain = "true"; delayed_gain = "true"; use_sensor_mode_id = "true"; limit_analog_gain = "true"; # 179 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-imx185-a00.dtsi" mode0 { mclk_khz = "37125"; num_lanes = "4"; tegra_sinterface = "serial_a"; phy_mode = "DPHY"; discontinuous_clk = "no"; dpcm_enable = "false"; cil_settletime = "0"; dynamic_pixel_bit_depth = "12"; csi_pixel_bit_depth = "12"; mode_type = "bayer"; pixel_phase = "rggb"; active_w = "1920"; active_h = "1080"; readout_orientation = "0"; line_length = "2200"; inherent_gain = "1"; mclk_multiplier = "2"; pix_clk_hz = "74250000"; gain_factor = "10"; min_gain_val = "0"; max_gain_val = "480"; step_gain_val = "3"; default_gain = "0"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "1500000"; max_framerate = "30000000"; step_framerate = "1"; default_framerate= "30000000"; exposure_factor = "1000000"; min_exp_time = "30"; max_exp_time = "660000"; step_exp_time = "1"; default_exp_time = "33334"; embedded_metadata_height = "1"; }; mode1 { mclk_khz = "37125"; num_lanes = "4"; tegra_sinterface = "serial_a"; phy_mode = "DPHY"; discontinuous_clk = "no"; dpcm_enable = "false"; cil_settletime = "0"; dynamic_pixel_bit_depth = "10"; csi_pixel_bit_depth = "10"; mode_type = "bayer"; pixel_phase = "rggb"; active_w = "1920"; active_h = "1080"; readout_orientation = "0"; line_length = "2640"; inherent_gain = "1"; mclk_multiplier = "2.4"; pix_clk_hz = "89100000"; gain_factor = "10"; min_gain_val = "0"; max_gain_val = "480"; step_gain_val = "3"; default_gain = "0"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "1500000"; max_framerate = "30000000"; step_framerate = "1"; default_framerate= "30000000"; exposure_factor = "1000000"; min_exp_time = "30"; max_exp_time = "660000"; step_exp_time = "1"; default_exp_time = "33334"; embedded_metadata_height = "1"; }; mode2 { mclk_khz = "37125"; num_lanes = "4"; tegra_sinterface = "serial_a"; phy_mode = "DPHY"; discontinuous_clk = "no"; dpcm_enable = "false"; cil_settletime = "0"; dynamic_pixel_bit_depth = "12"; csi_pixel_bit_depth = "12"; mode_type = "bayer"; pixel_phase = "rggb"; active_w = "1920"; active_h = "1080"; readout_orientation = "0"; line_length = "2200"; inherent_gain = "1"; mclk_multiplier = "4"; pix_clk_hz = "148500000"; gain_factor = "10"; min_gain_val = "0"; max_gain_val = "480"; step_gain_val = "3"; default_gain = "0"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "1500000"; max_framerate = "60000000"; step_framerate = "1"; default_framerate= "60000000"; exposure_factor = "1000000"; min_exp_time = "30"; max_exp_time = "660000"; step_exp_time = "1"; default_exp_time = "16667"; embedded_metadata_height = "1"; }; mode3 { mclk_khz = "37125"; num_lanes = "4"; tegra_sinterface = "serial_a"; phy_mode = "DPHY"; discontinuous_clk = "no"; dpcm_enable = "false"; cil_settletime = "0"; dynamic_pixel_bit_depth = "10"; csi_pixel_bit_depth = "10"; mode_type = "bayer"; pixel_phase = "rggb"; active_w = "1920"; active_h = "1080"; readout_orientation = "0"; line_length = "2640"; inherent_gain = "1"; mclk_multiplier = "4.8"; pix_clk_hz = "178200000"; gain_factor = "10"; min_gain_val = "0"; max_gain_val = "480"; step_gain_val = "3"; default_gain = "0"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "1500000"; max_framerate = "60000000"; step_framerate = "1"; default_framerate= "60000000"; exposure_factor = "1000000"; min_exp_time = "30"; max_exp_time = "660000"; step_exp_time = "1"; default_exp_time = "16667"; embedded_metadata_height = "1"; }; mode4 { mclk_khz = "37125"; num_lanes = "4"; tegra_sinterface = "serial_a"; phy_mode = "DPHY"; discontinuous_clk = "no"; dpcm_enable = "false"; cil_settletime = "0"; dynamic_pixel_bit_depth = "16"; csi_pixel_bit_depth = "12"; mode_type = "bayer_wdr_pwl"; pixel_phase = "rggb"; active_w = "1920"; active_h = "1080"; readout_orientation = "0"; line_length = "2200"; inherent_gain = "1"; mclk_multiplier = "2"; pix_clk_hz = "74250000"; gain_factor = "10"; min_gain_val = "0"; max_gain_val = "120"; step_gain_val = "3"; default_gain = "0"; min_hdr_ratio = "16"; max_hdr_ratio = "16"; framerate_factor = "1000000"; min_framerate = "1500000"; max_framerate = "30000000"; step_framerate = "1"; default_framerate= "30000000"; exposure_factor = "1000000"; min_exp_time = "2433"; max_exp_time = "660000"; step_exp_time = "1"; default_exp_time = "33334"; embedded_metadata_height = "1"; num_control_point = "4"; control_point_x_0 = "0"; control_point_x_1 = "2048"; control_point_x_2 = "16384"; control_point_x_3 = "65536"; control_point_y_0 = "0"; control_point_y_1 = "2048"; control_point_y_2 = "2944"; control_point_y_3 = "3712"; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; liimx185_imx185_out0: endpoint { port-index = <0>; bus-width = <4>; remote-endpoint = <&liimx185_csi_in0>; }; }; }; }; }; }; }; }; / { tegra-camera-platform { compatible = "nvidia, tegra-camera-platform"; # 441 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-imx185-a00.dtsi" num_csi_lanes = <4>; max_lane_speed = <1500000>; min_bits_per_pixel = <10>; vi_peak_byte_per_pixel = <2>; vi_bw_margin_pct = <25>; isp_peak_byte_per_pixel = <5>; isp_bw_margin_pct = <25>; # 457 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-imx185-a00.dtsi" modules { module0 { badge = "imx185_bottom_liimx185"; position = "bottom"; orientation = "0"; drivernode0 { pcl_id = "v4l2_sensor"; devname = "imx185 30-001a"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9546@70/i2c@0/imx185_a@1a"; }; }; }; }; }; # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-imx185-a00.dtsi" 2 / { gpio@2200000 { camera-control-output-low { gpio-hog; output-low; gpios = <((7 * 8) + 3) 0>; label = "cam0-rst"; }; }; i2c@3180000 { tca9546@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; #size-cells = <0>; skip_mux_detect = "yes"; vcc-supply = <&p2822_vdd_1v8_cvb>; vcc_lp = "vcc"; force_bus_start = <(0x1E + 0)>; i2c@0 { reg = <0>; i2c-mux,deselect-on-exit; #address-cells = <1>; #size-cells = <0>; pca9570_a@24 { compatible = "nvidia,pca9570"; reg = <0x24>; channel = "a"; drive_ic = "DRV8838"; }; imx185_a@1a { clocks = <&bpmp_clks 36U>, <&bpmp_clks 36U>; clock-names = "extperiph1", "pllp_grtba"; mclk = "extperiph1"; reset-gpios = <&tegra_main_gpio ((7 * 8) + 3) 0>; }; }; }; }; }; # 22 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-camera-modules.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-imx390-a00.dtsi" 1 # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-imx390-a00.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-imx390-a00.dtsi" 1 # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-imx390-a00.dtsi" / { host1x { vi@15c10000 { num-channels = <2>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; imx390_vi_in0: endpoint { vc-id = <0>; port-index = <0>; bus-width = <2>; remote-endpoint = <&imx390_csi_out0>; }; }; port@1 { reg = <1>; imx390_vi_in1: endpoint { vc-id = <1>; port-index = <0>; bus-width = <2>; remote-endpoint = <&imx390_csi_out1>; }; }; }; }; nvcsi@15a00000 { num-channels = <2>; #address-cells = <1>; #size-cells = <0>; channel@0 { reg = <0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; imx390_csi_in0: endpoint@0 { port-index = <0>; bus-width = <2>; remote-endpoint = <&imx390_imx390_out0>; }; }; port@1 { reg = <1>; imx390_csi_out0: endpoint@1 { remote-endpoint = <&imx390_vi_in0>; }; }; }; }; channel@1 { reg = <1>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; imx390_csi_in1: endpoint@2 { port-index = <0>; bus-width = <2>; remote-endpoint = <&imx390_imx390_out1>; }; }; port@1 { reg = <1>; imx390_csi_out1: endpoint@3 { remote-endpoint = <&imx390_vi_in1>; }; }; }; }; }; }; i2c@3180000 { tca9546@70 { i2c@0 { imx390_a@1b { compatible = "nvidia,imx390"; reg = <0x1b>; physical_w = "15.0"; physical_h = "12.5"; sensor_model ="imx390"; post_crop_frame_drop = "0"; use_decibel_gain = "true"; use_sensor_mode_id = "true"; # 205 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-imx390-a00.dtsi" mode0 { mclk_khz = "24000"; num_lanes = "2"; tegra_sinterface = "serial_a"; vc_id = "0"; discontinuous_clk = "no"; dpcm_enable = "false"; cil_settletime = "0"; dynamic_pixel_bit_depth = "12"; csi_pixel_bit_depth = "12"; mode_type = "bayer"; pixel_phase = "rggb"; active_w = "1920"; active_h = "1080"; readout_orientation = "0"; line_length = "2200"; inherent_gain = "1"; pix_clk_hz = "74250000"; serdes_pix_clk_hz = "833333333"; gain_factor = "10"; min_gain_val = "0"; max_gain_val = "300"; step_gain_val = "3"; default_gain = "0"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "30000000"; max_framerate = "30000000"; step_framerate = "1"; default_framerate = "30000000"; exposure_factor = "1000000"; min_exp_time = "59"; max_exp_time = "33333"; step_exp_time = "1"; default_exp_time = "33333"; embedded_metadata_height = "0"; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; imx390_imx390_out0: endpoint { vc-id = <0>; port-index = <0>; bus-width = <2>; remote-endpoint = <&imx390_csi_in0>; }; }; }; gmsl-link { src-csi-port = "b"; dst-csi-port = "a"; serdes-csi-link = "a"; csi-mode = "1x4"; st-vc = <0>; vc-id = <0>; num-lanes = <2>; streams = "ued-u1", "raw12"; }; }; imx390_b@1c { compatible = "nvidia,imx390"; reg = <0x1c>; physical_w = "15.0"; physical_h = "12.5"; sensor_model ="imx390"; post_crop_frame_drop = "0"; use_decibel_gain = "true"; use_sensor_mode_id = "true"; # 377 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-imx390-a00.dtsi" mode0 { mclk_khz = "24000"; num_lanes = "2"; tegra_sinterface = "serial_a"; vc_id = "1"; discontinuous_clk = "no"; dpcm_enable = "false"; cil_settletime = "0"; dynamic_pixel_bit_depth = "12"; csi_pixel_bit_depth = "12"; mode_type = "bayer"; pixel_phase = "rggb"; active_w = "1920"; active_h = "1080"; readout_orientation = "0"; line_length = "2200"; inherent_gain = "1"; pix_clk_hz = "74250000"; serdes_pix_clk_hz = "833333333"; gain_factor = "10"; min_gain_val = "0"; max_gain_val = "300"; step_gain_val = "3"; default_gain = "0"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "30000000"; max_framerate = "30000000"; step_framerate = "1"; default_framerate = "30000000"; exposure_factor = "1000000"; min_exp_time = "59"; max_exp_time = "33333"; step_exp_time = "1"; default_exp_time = "33333"; embedded_metadata_height = "0"; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; imx390_imx390_out1: endpoint { vc-id = <1>; port-index = <0>; bus-width = <2>; remote-endpoint = <&imx390_csi_in1>; }; }; }; gmsl-link { src-csi-port = "b"; dst-csi-port = "a"; serdes-csi-link = "b"; csi-mode = "1x4"; st-vc = <0>; vc-id = <1>; num-lanes = <2>; streams = "ued-u1", "raw12"; }; }; }; }; }; }; / { tegra-camera-platform { compatible = "nvidia, tegra-camera-platform"; # 477 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-imx390-a00.dtsi" num_csi_lanes = <2>; max_lane_speed = <4000000>; min_bits_per_pixel = <10>; vi_peak_byte_per_pixel = <2>; vi_bw_margin_pct = <25>; isp_peak_byte_per_pixel = <5>; isp_bw_margin_pct = <25>; # 493 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-imx390-a00.dtsi" modules { module0 { badge = "imx390_rear"; position = "rear"; orientation = "1"; drivernode0 { pcl_id = "v4l2_sensor"; devname = "imx390 30-001b"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9546@70/i2c@0/imx390_a@1b"; }; }; module1 { badge = "imx390_front"; position = "front"; orientation = "1"; drivernode0 { pcl_id = "v4l2_sensor"; devname = "imx390 30-001c"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9546@70/i2c@0/imx390_b@1c"; }; }; }; }; }; # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-imx390-a00.dtsi" 2 / { i2c@3180000 { tca9546@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; #size-cells = <0>; skip_mux_detect = "yes"; vif-supply = <&p2822_vdd_1v8_cvb>; vcc-supply = <&p2822_vdd_1v8_cvb>; vcc_lp = "vcc"; force_bus_start = <(0x1E + 0)>; i2c@0 { reg = <0>; i2c-mux,deselect-on-exit; #address-cells = <1>; #size-cells = <0>; dser: max9296@48 { compatible = "nvidia,max9296"; reg = <0x48>; csi-mode = "2x4"; max-src = <2>; reset-gpios = <&tegra_main_gpio ((7 * 8) + 3) 0>; }; ser_prim: max9295_prim@62 { compatible = "nvidia,max9295"; reg = <0x62>; is-prim-ser; }; ser_a: max9295_a@40 { compatible = "nvidia,max9295"; reg = <0x40>; nvidia,gmsl-dser-device = <&dser>; }; ser_b: max9295_b@60 { compatible = "nvidia,max9295"; reg = <0x60>; nvidia,gmsl-dser-device = <&dser>; }; imx390_a@1b { def-addr = <0x1a>; clocks = <&bpmp_clks 36U>, <&bpmp_clks 36U>; clock-names = "extperiph1", "pllp_grtba"; mclk = "extperiph1"; nvidia,gmsl-ser-device = <&ser_a>; nvidia,gmsl-dser-device = <&dser>; }; imx390_b@1c { def-addr = <0x1a>; clocks = <&bpmp_clks 36U>, <&bpmp_clks 36U>; clock-names = "extperiph1", "pllp_grtba"; mclk = "extperiph1"; nvidia,gmsl-ser-device = <&ser_b>; nvidia,gmsl-dser-device = <&dser>; }; }; }; }; }; # 23 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-camera-modules.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-e2832-hdmi.dtsi" 1 # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-e2832-hdmi.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e2832.dtsi" 1 # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e2832.dtsi" / { host1x { vi@15c10000 { num-channels = <1>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; e2832_vi_in0: endpoint { port-index = <0>; bus-width = <8>; remote-endpoint = <&e2832_csi_out0>; }; }; }; }; nvcsi@15a00000 { num-channels = <1>; #address-cells = <1>; #size-cells = <0>; channel@0 { reg = <0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; e2832_csi_in0: endpoint@0 { port-index = <0>; bus-width = <8>; remote-endpoint = <&e2832_out0>; }; }; port@1 { reg = <1>; e2832_csi_out0: endpoint@1 { remote-endpoint = <&e2832_vi_in0>; }; }; }; }; }; }; i2c@3180000 { e2832@2b { compatible = "nvidia,lt6911uxc"; reg = <0x2b>; devnode = "video0"; physical_w = "3.674"; physical_h = "2.738"; sensor_model = "e2832"; avdd-reg = "vana"; iovdd-reg = "vif"; dvdd-reg = "vdig"; # 195 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e2832.dtsi" mode0 { mclk_khz = "24000"; num_lanes = "4"; tegra_sinterface = "serial_a"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "1920"; active_h = "1080"; mode_type = "rgb"; pixel_phase = "rgb888"; csi_pixel_bit_depth = "24"; readout_orientation = "0"; line_length = "1920"; inherent_gain = "1"; mclk_multiplier = "24"; pix_clk_hz = "576000000"; gain_factor = "16"; framerate_factor = "1000000"; exposure_factor = "1000000"; min_gain_val = "16"; max_gain_val = "170"; step_gain_val = "1"; default_gain = "16"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; min_framerate = "2000000"; max_framerate = "60000000"; step_framerate = "1"; default_framerate = "60000000"; min_exp_time = "13"; max_exp_time = "683709"; step_exp_time = "1"; default_exp_time = "16667"; }; mode1 { mclk_khz = "24000"; num_lanes = "8"; tegra_sinterface = "serial_a"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "3840"; active_h = "2160"; mode_type = "rgb"; pixel_phase = "rgb888"; csi_pixel_bit_depth = "24"; readout_orientation = "0"; line_length = "3840"; inherent_gain = "1"; mclk_multiplier = "24"; pix_clk_hz = "576000000"; gain_factor = "16"; framerate_factor = "1000000"; exposure_factor = "1000000"; min_gain_val = "16"; max_gain_val = "170"; step_gain_val = "1"; default_gain = "16"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; min_framerate = "2000000"; max_framerate = "60000000"; step_framerate = "1"; default_framerate = "60000000"; min_exp_time = "13"; max_exp_time = "683709"; step_exp_time = "1"; default_exp_time = "16667"; }; mode2 { mclk_khz = "24000"; num_lanes = "4"; tegra_sinterface = "serial_a"; phy_mode = "DPHY"; discontinuous_clk = "yes"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "1280"; active_h = "720"; mode_type = "rgb"; pixel_phase = "rgb888"; csi_pixel_bit_depth = "24"; readout_orientation = "0"; line_length = "1280"; inherent_gain = "1"; mclk_multiplier = "24"; pix_clk_hz = "576000000"; gain_factor = "16"; framerate_factor = "1000000"; exposure_factor = "1000000"; min_gain_val = "16"; max_gain_val = "170"; step_gain_val = "1"; default_gain = "16"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; min_framerate = "2000000"; max_framerate = "60000000"; step_framerate = "1"; default_framerate = "60000000"; min_exp_time = "13"; max_exp_time = "683709"; step_exp_time = "1"; default_exp_time = "16667"; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; e2832_out0: endpoint { port-index = <0>; bus-width = <8>; remote-endpoint = <&e2832_csi_in0>; }; }; }; }; }; }; / { tegra-camera-platform { compatible = "nvidia, tegra-camera-platform"; # 357 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e2832.dtsi" num_csi_lanes = <4>; max_lane_speed = <1500000>; min_bits_per_pixel = <10>; vi_peak_byte_per_pixel = <2>; vi_bw_margin_pct = <25>; max_pixel_rate = <750000>; isp_peak_byte_per_pixel = <5>; isp_bw_margin_pct = <25>; # 374 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e2832.dtsi" modules { module0 { badge = "e2832_ltx6911"; position = "bottom"; orientation = "1"; drivernode0 { pcl_id = "v4l2_sensor"; devname = "e2832 2-002b"; proc-device-tree = "/proc/device-tree/i2c@3180000/e2832@2b"; }; }; }; }; }; # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-e2832-hdmi.dtsi" 2 # 26 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-e2832-hdmi.dtsi" / { gpio@2200000 { camera-control-output-low { gpio-hog; output-low; gpios = <((7 * 8) + 3) 0 ((7 * 8) + 6) 0>; label = "cam0-rst", "cam0-pwdn"; }; }; i2c@3180000 { e2832@2b { clocks = <&bpmp_clks 36U>, <&bpmp_clks 36U>; clock-names = "extperiph1", "pllp_grtba"; mclk = "extperiph1"; reset-gpios = <&tegra_main_gpio ((7 * 8) + 6) 0>; # 54 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-e2832-hdmi.dtsi" }; }; }; # 24 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-camera-modules.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-vivid.dtsi" 1 # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-vivid.dtsi" # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-vivid.dtsi" 1 # 18 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-vivid.dtsi" / { vivid-driver { instance0 { # 104 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-vivid.dtsi" mode0 { tegra_sinterface = "host"; pix_clk_hz = "74250000"; readout_orientation = "90"; active_w = "1920"; active_h = "1080"; pixel_t = "bayer_bggr10"; line_length = "2200"; horz_front_porch = "88"; horz_sync = "44"; horz_back_porch = "148"; vert_front_porch = "4"; vert_sync = "5"; vert_back_porch = "36"; gain_factor = "16"; framerate_factor = "1"; min_gain_val = "1"; max_gain_val = "256"; min_exp_time = "34"; max_exp_time = "999994"; min_framerate = "1"; max_framerate = "30"; embedded_metadata_height = "1"; }; }; }; tegra-virtual-camera-platform { # 148 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-vivid.dtsi" isp_peak_byte_per_pixel = <5>; isp_bw_margin_pct = <25>; modules { module0 { badge = "vivid_front_instance0"; position = "front"; orientation = "1"; drivernode0 { pcl_id = "v4l2_sensor_virtual"; devname = "tegra-vivid-000"; proc-device-tree = "/proc/device-tree/vivid-driver/instances/instance0"; }; }; }; }; }; # 17 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-0000-camera-vivid.dtsi" 2 # 25 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-camera-modules.dtsi" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-camera-psm_amb_gen3_kcku15p.dtsi" 1 # 10 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-camera-psm_amb_gen3_kcku15p.dtsi" / { host1x { vi@15c10000 { num-channels = <2>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; tc358746_vi_in0: endpoint { port-index = <0>; bus-width = <4>; remote-endpoint = <&tc358746_csi_out0>; }; }; port@1 { reg = <1>; tc358746_vi_in1: endpoint { port-index = <2>; bus-width = <4>; remote-endpoint = <&tc358746_csi_out1>; }; }; }; }; nvcsi@15a00000 { num-channels = <2>; #address-cells = <1>; #size-cells = <0>; status = "okay"; channel@0 { reg = <0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; tc358746_csi_in0: endpoint@0 { port-index = <0>; bus-width = <4>; remote-endpoint = <&litc358746_tc358746_out0>; }; }; port@1 { reg = <1>; tc358746_csi_out0: endpoint@1 { remote-endpoint = <&tc358746_vi_in0>; }; }; }; }; channel@1 { reg = <1>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; tc358746_csi_in1: endpoint@2 { port-index = <2>; bus-width = <4>; remote-endpoint = <&litc358746_tc358746_out1>; }; }; port@1 { reg = <1>; tc358746_csi_out1: endpoint@3 { remote-endpoint = <&tc358746_vi_in1>; }; }; }; }; }; }; i2c@3160000 { tc358746_a@1e { status = "okay"; #address-cells = <1>; #size-cells = <0>; compatible = "toshiba,tc358746"; reg = <0x1e>; devnode = "video0"; physical_w = "3.680"; physical_h = "2.760"; # 188 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-camera-psm_amb_gen3_kcku15p.dtsi" mode0 { mclk_khz = "37125"; num_lanes = "2"; tegra_sinterface = "serial_a"; phy_mode = "DPHY"; discontinuous_clk = "no"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "1920"; active_h = "1080"; mode_type = "rgb"; pixel_phase = "rgb888"; csi_pixel_bit_depth = "24"; line_length = "2000"; # 217 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-camera-psm_amb_gen3_kcku15p.dtsi" readout_orientation = "0"; inherent_gain = "1"; mclk_multiplier = "1"; pix_clk_hz = "74250000"; gain_factor = "10"; min_gain_val = "0"; max_gain_val = "480"; step_gain_val = "3"; default_gain = "0"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "30000000"; max_framerate = "30000000"; step_framerate = "1"; default_framerate = "30000000"; exposure_factor = "1000000"; min_exp_time = "30"; max_exp_time = "660000"; step_exp_time = "1"; default_exp_time = "33334"; embedded_metadata_height = "0"; dynamic_pixel_bit_depth = "16"; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; litc358746_tc358746_out0: endpoint { port-index = <0>; bus-width = <4>; remote-endpoint = <&tc358746_csi_in0>; }; }; }; }; tc358746_b@2e { status = "okay"; #address-cells = <1>; #size-cells = <0>; compatible = "toshiba,tc358746"; reg = <0x2e>; devnode = "video1"; physical_w = "3.680"; physical_h = "2.760"; # 348 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-camera-psm_amb_gen3_kcku15p.dtsi" mode0 { mclk_khz = "37125"; num_lanes = "2"; tegra_sinterface = "serial_a"; phy_mode = "DPHY"; discontinuous_clk = "no"; dpcm_enable = "false"; cil_settletime = "0"; active_w = "1920"; active_h = "1080"; mode_type = "rgb"; pixel_phase = "rgb888"; csi_pixel_bit_depth = "24"; line_length = "2000"; # 376 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-camera-psm_amb_gen3_kcku15p.dtsi" readout_orientation = "0"; inherent_gain = "1"; mclk_multiplier = "1"; pix_clk_hz = "74250000"; gain_factor = "10"; min_gain_val = "0"; max_gain_val = "480"; step_gain_val = "3"; default_gain = "0"; min_hdr_ratio = "1"; max_hdr_ratio = "1"; framerate_factor = "1000000"; min_framerate = "30000000"; max_framerate = "30000000"; step_framerate = "1"; default_framerate = "30000000"; exposure_factor = "1000000"; min_exp_time = "30"; max_exp_time = "660000"; step_exp_time = "1"; default_exp_time = "33334"; embedded_metadata_height = "0"; dynamic_pixel_bit_depth = "16"; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; litc358746_tc358746_out1: endpoint { port-index = <2>; bus-width = <4>; remote-endpoint = <&tc358746_csi_in1>; }; }; }; }; }; tegra-camera-platform { compatible = "nvidia, tegra-camera-platform"; # 455 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-camera-psm_amb_gen3_kcku15p.dtsi" num_csi_lanes = <4>; # 464 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-camera-psm_amb_gen3_kcku15p.dtsi" max_lane_speed = <1500000>; min_bits_per_pixel = <8>; vi_peak_byte_per_pixel = <2>; vi_bw_margin_pct = <25>; max_pixel_rate = <750000>; isp_peak_byte_per_pixel = <5>; isp_bw_margin_pct = <25>; # 480 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-camera-psm_amb_gen3_kcku15p.dtsi" modules { module0 { badge = "tc358746_top_i2c0_b"; position = "front"; orientation = "0"; drivernode0 { pcl_id = "v4l2_sensor"; devname = "tc358746_a 0-001e"; proc-device-tree = "/proc/device-tree/i2c@3160000/tc358746_a@1e"; }; }; module1 { badge = "tc358746_top_i2c1_b"; position = "centerleft"; orientation = "0"; drivernode0 { pcl_id = "v4l2_sensor"; devname = "tc358746_b 0-002e"; proc-device-tree = "/proc/device-tree/i2c@3160000/tc358746_b@2e"; }; }; }; }; }; # 30 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-camera-modules.dtsi" 2 # 39 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-camera-modules.dtsi" / { tegra-camera-platform { tpg_max_iso = <3916800>; }; gpio@2200000 { camera-control-output-low { gpio-hog; output-low; gpios = <((7 * 8) + 3) 0 ((7 * 8) + 6) 0 ((19 * 8) + 6) 0 ((19 * 8) + 5) 0 ((24 * 8) + 1) 0>; label = "cam0-rst", "cam0-pwdn", "cam1-rst", "cam1-pwdn", "slvs-cam0-rst"; }; }; host1x { vi_base: vi@15c10000 { ports { vi_port0: port@0 { status = "okay"; vi_in0: endpoint { vc-id = <0>; status = "okay"; }; }; vi_port1: port@1 { status = "okay"; vi_in1: endpoint { vc-id = <0>; status = "okay"; }; }; # 100 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-camera-modules.dtsi" vi_port2: port@2 { status = "disabled"; vi_in2: endpoint { vc-id = <0>; status = "disabled"; }; }; vi_port3: port@3 { status = "disabled"; vi_in3: endpoint { vc-id = <0>; status = "disabled"; }; }; vi_port4: port@4 { status = "disabled"; vi_in4: endpoint { vc-id = <0>; status = "disabled"; }; }; vi_port5: port@5 { status = "disabled"; vi_in5: endpoint { vc-id = <0>; status = "disabled"; }; }; }; }; csi_base: nvcsi@15a00000 { num-tpg-channels = <36>; csi_chan0: channel@0 { status = "okay"; ports { csi_chan0_port0: port@0 { status = "okay"; csi_in0: endpoint@0 { status = "okay"; }; }; csi_chan0_port1: port@1 { status = "okay"; csi_out0: endpoint@1 { status = "okay"; }; }; }; }; csi_chan1: channel@1 { status = "okay"; ports { csi_chan1_port0: port@0 { status = "okay"; csi_in1: endpoint@2 { status = "okay"; }; }; csi_chan1_port1: port@1 { status = "okay"; csi_out1: endpoint@3 { status = "okay"; }; }; }; }; # 204 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-camera-modules.dtsi" csi_chan2: channel@2 { status = "disabled"; ports { csi_chan2_port0: port@0 { status = "disabled"; csi_in2: endpoint@4 { status = "disabled"; }; }; csi_chan2_port1: port@1 { status = "disabled"; csi_out2: endpoint@5 { status = "disabled"; }; }; }; }; csi_chan3: channel@3 { status = "disabled"; ports { csi_chan3_port0: port@0 { status = "disabled"; csi_in3: endpoint@6 { status = "disabled"; }; }; csi_chan3_port1: port@1 { status = "disabled"; csi_out3: endpoint@7 { status = "disabled"; }; }; }; }; csi_chan4: channel@4 { status = "disabled"; ports { csi_chan4_port0: port@0 { status = "disabled"; csi_in4: endpoint@8 { status = "disabled"; }; }; csi_chan4_port1: port@1 { status = "disabled"; csi_out4: endpoint@9 { status = "disabled"; }; }; }; }; csi_chan5: channel@5 { status = "disabled"; ports { csi_chan5_port0: port@0 { status = "disabled"; csi_in5: endpoint@10 { status = "disabled"; }; }; csi_chan5_port1: port@1 { status = "disabled"; csi_out5: endpoint@11 { status = "disabled"; }; }; }; }; }; slvs_ec_base: slvs-ec@15ac0000 { status = "disabled"; streams { slvs_ec_stream0: stream@0 { status = "disabled"; ports { slvs_ec_stream0_port0: port@0 { status = "disabled"; e3377_slvs_ec_in0: endpoint@0 { status = "disabled"; }; }; slvs_ec_stream0_port1: port@1 { status = "disabled"; e3377_slvs_ec_out0: endpoint@1 { status = "disabled"; }; }; }; }; }; }; }; i2c@3180000 { e3326_cam0: ov5693_c@36 { status = "disabled"; }; e2832_cam0: e2832@2b { status = "disabled"; }; tca6408@21 { status = "disabled"; }; tca9548@77 { status = "disabled"; i2c@0 { e3333_cam0: ov5693_a@36 { status = "disabled"; }; }; i2c@1 { e3333_cam1: ov5693_b@36 { status = "disabled"; }; }; i2c@2 { e3333_cam2: ov5693_c@36 { status = "disabled"; }; }; i2c@3 { e3333_cam3: ov5693_d@36 { status = "disabled"; }; }; i2c@4 { e3333_cam4: ov5693_e@36 { status = "disabled"; }; }; i2c@5 { e3333_cam5: ov5693_g@36 { status = "disabled"; }; }; }; tca9546_70: tca9546@70 { status = "disabled"; i2c@0 { pca9570_a_24: pca9570_a@24 { status = "disabled"; }; imx274_cam0: imx274_a@1a { status = "disabled"; }; imx185_cam0: imx185_a@1a { status = "disabled"; }; e3331_cam0: imx318_a@10 { status = "disable"; }; max9296_dser: max9296@48 { status = "disabled"; }; max9295_prim: max9295_prim@62 { status = "disabled"; }; max9295_ser0: max9295_a@40 { status = "disabled"; }; max9295_ser1: max9295_b@60 { status = "disabled"; }; imx390_cam0: imx390_a@1b { status = "disabled"; }; imx390_cam1: imx390_b@1c { status = "disabled"; }; }; i2c@1 { imx274_cam1: imx274_c@1a { status = "disabled"; }; }; }; }; spi_cam0: spi@c260000 { e3377_cam0: imx204@0 { status = "disabled"; }; }; tcp: tegra-camera-platform { compatible = "nvidia, tegra-camera-platform"; modules { cam_module0: module0 { status = "okay"; cam_module0_drivernode0: drivernode0 { status = "okay"; }; cam_module0_drivernode1: drivernode1 { status = "okay"; pcl_id = "v4l2_lens"; }; }; cam_module1: module1 { status = "okay"; cam_module1_drivernode0: drivernode0 { status = "okay"; }; cam_module1_drivernode1: drivernode1 { status = "okay"; pcl_id = "v4l2_lens"; }; }; # 435 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2822-camera-modules.dtsi" cam_module2: module2 { status = "disabled"; cam_module2_drivernode0: drivernode0 { status = "disabled"; }; cam_module2_drivernode1: drivernode1 { status = "disabled"; pcl_id = "v4l2_lens"; }; }; cam_module3: module3 { status = "disabled"; cam_module3_drivernode0: drivernode0 { status = "disabled"; }; cam_module3_drivernode1: drivernode1 { status = "disabled"; pcl_id = "v4l2_lens"; }; }; cam_module4: module4 { status = "disabled"; cam_module4_drivernode0: drivernode0 { status = "disabled"; }; cam_module4_drivernode1: drivernode1 { status = "disabled"; pcl_id = "v4l2_lens"; }; }; cam_module5: module5 { status = "disabled"; cam_module5_drivernode0: drivernode0 { status = "disabled"; }; cam_module5_drivernode1: drivernode1 { status = "disabled"; pcl_id = "v4l2_lens"; }; }; }; }; }; # 23 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/tegra194-p2888-0001-p2822-0000.dts" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-plugin-manager.dtsi" 1 # 21 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/../../hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-plugin-manager.dtsi" / { gpio@2200000 { camera-control-output-low { status = "disabled"; }; camera-control-output-high { status = "disabled"; }; camera-control-input { status = "disabled"; }; }; plugin-manager { fragment-imx390@0 { ids = "LPRD-001"; override@0 { target = <&imx390_cam0>; _overlay_ { status = "okay"; }; }; override@1 { target = <&cam_module0>; _overlay_ { status = "okay"; badge = "imx390_rear"; position = "rear"; orientation = "1"; }; }; override@2 { target = <&cam_module0_drivernode0>; _overlay_ { status = "okay"; pcl_id = "v4l2_sensor"; devname = "imx390 30-001b"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9546@70/i2c@0/imx390_a@1b"; }; }; override@3 { target = <&imx390_cam1>; _overlay_ { status = "okay"; }; }; override@4 { target = <&cam_module1>; _overlay_ { status = "okay"; badge = "imx390_front"; position = "front"; orientation = "1"; }; }; override@5 { target = <&cam_module1_drivernode0>; _overlay_ { status = "okay"; pcl_id = "v4l2_sensor"; devname = "imx390 30-001c"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9546@70/i2c@0/imx390_b@1c"; }; }; override@6 { target = <&vi_base>; _overlay_ { num-channels=<2>; }; }; override@7 { target = <&vi_port0>; _overlay_ { status = "okay"; }; }; override@8 { target = <&vi_port1>; _overlay_ { status = "okay"; }; }; override@9 { target = <&imx390_vi_in0>; _overlay_ { status = "okay"; vc-id = <0>; port-index = <0>; bus-width = <2>; remote-endpoint = <&imx390_csi_out0>; }; }; override@10 { target = <&imx390_vi_in1>; _overlay_ { status = "okay"; vc-id = <1>; port-index = <0>; bus-width = <2>; remote-endpoint = <&imx390_csi_out1>; }; }; override@11{ target = <&csi_base>; _overlay_ { num-channels=<2>; }; }; override@12 { target = <&csi_chan0>; _overlay_ { status = "okay"; }; }; override@13 { target = <&csi_chan0_port0>; _overlay_ { status = "okay"; }; }; override@14 { target = <&imx390_csi_in0>; _overlay_ { status = "okay"; port-index = <0>; bus-width = <2>; remote-endpoint = <&imx390_imx390_out0>; }; }; override@15 { target = <&csi_chan0_port1>; _overlay_ { status = "okay"; }; }; override@16 { target = <&imx390_csi_out0>; _overlay_ { status = "okay"; }; }; override@17 { target = <&csi_chan1>; _overlay_ { status = "okay"; }; }; override@18 { target = <&csi_chan1_port0>; _overlay_ { status = "okay"; }; }; override@19 { target = <&imx390_csi_in1>; _overlay_ { status = "okay"; port-index = <0>; bus-width = <2>; remote-endpoint = <&imx390_imx390_out1>; }; }; override@20 { target = <&csi_chan1_port1>; _overlay_ { status = "okay"; }; }; override@21 { target = <&imx390_csi_out1>; _overlay_ { status = "okay"; }; }; override@22 { target = <&tcp>; _overlay_ { num_csi_lanes = <2>; max_lane_speed = <4000000>; min_bits_per_pixel = <10>; vi_peak_byte_per_pixel = <2>; vi_bw_margin_pct = <25>; isp_peak_byte_per_pixel = <5>; isp_bw_margin_pct = <25>; }; }; override@23 { target = <&tca9546_70>; _overlay_ { status = "okay"; }; }; override@24 { target = <&max9296_dser>; _overlay_ { status = "okay"; }; }; override@25 { target = <&max9295_prim>; _overlay_ { status = "okay"; }; }; override@26 { target = <&max9295_ser0>; _overlay_ { status = "okay"; }; }; override@27 { target = <&max9295_ser1>; _overlay_ { status = "okay"; }; }; }; fragment-e2832@0 { ids = "2832-*"; override@0 { target = <&e2832_cam0>; _overlay_ { status = "okay"; }; }; override@1 { target = <&cam_module0>; _overlay_ { status = "okay"; badge = "e2832_ltx6911"; position = "bottom"; orientation = "0"; }; }; override@2 { target = <&cam_module0_drivernode0>; _overlay_ { status = "okay"; pcl_id = "v4l2_sensor"; devname = "e2832 2-002b"; proc-device-tree = "/proc/device-tree/i2c@3180000/e2832@2b"; }; }; override@4 { target = <&vi_base>; _overlay_ { num-channels=<1>; }; }; override@5 { target = <&vi_port0>; _overlay_ { status = "okay"; }; }; override@6 { target = <&e2832_vi_in0>; _overlay_ { status = "okay"; port-index = <0>; bus-width = <8>; remote-endpoint = <&e2832_csi_out0>; }; }; override@7 { target = <&csi_base>; _overlay_ { num-channels=<1>; }; }; override@8 { target = <&csi_chan0>; _overlay_ { status = "okay"; }; }; override@9 { target = <&csi_chan0_port0>; _overlay_ { status = "okay"; }; }; override@10 { target = <&e2832_csi_in0>; _overlay_ { status = "okay"; port-index = <0>; bus-width = <8>; remote-endpoint = <&e2832_out0>; }; }; override@11 { target = <&csi_chan0_port1>; _overlay_ { status = "okay"; }; }; override@12 { target = <&e2832_csi_out0>; _overlay_ { status = "okay"; remote-endpoint = <&e2832_vi_in0>; }; }; override@13 { target = <&tcp>; _overlay_ { num_csi_lanes = <8>; max_lane_speed = <1500000>; min_bits_per_pixel = <10>; vi_peak_byte_per_pixel = <2>; vi_bw_margin_pct = <25>; isp_peak_byte_per_pixel = <5>; isp_bw_margin_pct = <25>; }; }; override@15 { target = <&{/gpio@2200000}>; _overlay_ { camera-control-input { status = "disabled"; }; camera-control-output-low { status = "disabled"; }; camera-control-output-high { gpio-hog; gpios = <((7 * 8) + 3) 0>; label = "cam0-rst"; output-high; status = "okay"; }; }; }; }; fragment-e3326@0 { ids = "3326-*"; override@0 { target = <&e3326_cam0>; _overlay_ { status = "okay"; }; }; override@1 { target = <&cam_module0>; _overlay_ { status = "okay"; badge = "e3326_front_P5V27C"; position = "rear"; orientation = "1"; }; }; override@2 { target = <&cam_module0_drivernode0>; _overlay_ { status = "okay"; pcl_id = "v4l2_sensor"; devname = "ov5693 2-0036"; proc-device-tree = "/proc/device-tree/i2c@3180000/ov5693_c@36"; }; }; override@3 { target = <&cam_module0_drivernode1>; _overlay_ { status = "okay"; pcl_id = "v4l2_lens"; proc-device-tree = "/proc/device-tree/e3326_lens_ov5693@P5V27C/"; }; }; override@4 { target = <&vi_base>; _overlay_ { num-channels=<1>; }; }; override@5 { target = <&vi_port0>; _overlay_ { status = "okay"; }; }; override@6 { target = <&e3326_vi_in0>; _overlay_ { status = "okay"; port-index = <2>; bus-width = <2>; remote-endpoint = <&e3326_csi_out0>; }; }; override@7 { target = <&csi_base>; _overlay_ { num-channels=<1>; }; }; override@8 { target = <&csi_chan0>; _overlay_ { status = "okay"; }; }; override@9 { target = <&csi_chan0_port0>; _overlay_ { status = "okay"; }; }; override@10 { target = <&e3326_csi_in0>; _overlay_ { status = "okay"; port-index = <2>; bus-width = <2>; remote-endpoint = <&e3326_ov5693_out0>; }; }; override@11 { target = <&csi_chan0_port1>; _overlay_ { status = "okay"; }; }; override@12 { target = <&e3326_csi_out0>; _overlay_ { status = "okay"; remote-endpoint = <&e3326_vi_in0>; }; }; override@13 { target = <&tcp>; _overlay_ { num_csi_lanes = <4>; max_lane_speed = <1500000>; min_bits_per_pixel = <10>; vi_peak_byte_per_pixel = <2>; vi_bw_margin_pct = <25>; isp_peak_byte_per_pixel = <5>; isp_bw_margin_pct = <25>; }; }; override@14 { target = <&{/gpio@2200000}>; _overlay_ { camera-control-input { status = "disabled"; }; camera-control-output-low { gpio-hog; gpios = <((7 * 8) + 3) 0 ((7 * 8) + 6) 0>; label = "cam0-rst", "cam0-pwdn"; output-low; status = "okay"; }; camera-control-output-high { status = "disabled"; }; }; }; override@15 { target = <&{/gpio@c2f0000}>; _overlay_ { camera-control-input { status = "disabled"; }; }; }; }; fragment-e3333@0 { ids = "3333-*"; override@0 { target = <&vi_base>; _overlay_ { num-channels=<6>; }; }; override@1 { target = <&csi_base>; _overlay_ { num-channels=<6>; }; }; override@2 { target = <&tcp>; _overlay_ { num_csi_lanes = <12>; max_lane_speed = <1500000>; min_bits_per_pixel = <10>; vi_peak_byte_per_pixel = <2>; vi_bw_margin_pct = <25>; max_pixel_rate = <200000>; isp_peak_byte_per_pixel = <5>; isp_bw_margin_pct = <25>; }; }; override@3 { target = <&tca6408_21>; _overlay_ { status = "okay"; }; }; override@4 { target = <&tca9548_77>; _overlay_ { status = "okay"; }; }; override@5 { target = <&e3333_cam0>; _overlay_ { status = "okay"; }; }; override@6 { target = <&cam_module0>; _overlay_ { status = "okay"; badge = "e3333_bottomleft_P5V27C"; position = "bottomleft"; orientation = "1"; }; }; override@7 { target = <&cam_module0_drivernode0>; _overlay_ { status = "okay"; pcl_id = "v4l2_sensor"; devname = "ov5693 30-0036"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9548@77/i2c@0/ov5693_a@36"; }; }; override@8 { target = <&cam_module0_drivernode1>; _overlay_ { status = "okay"; pcl_id = "v4l2_lens"; proc-device-tree = "/proc/device-tree/e3333_lens_ov5693@P5V27C/"; }; }; override@9 { target = <&vi_port0>; _overlay_ { status = "okay"; }; }; override@10 { target = <&e3333_vi_in0>; _overlay_ { status = "okay"; port-index = <0>; bus-width = <2>; remote-endpoint = <&e3333_csi_out0>; }; }; override@11 { target = <&csi_chan0>; _overlay_ { status = "okay"; }; }; override@12 { target = <&csi_chan0_port0>; _overlay_ { status = "okay"; }; }; override@13 { target = <&e3333_csi_in0>; _overlay_ { status = "okay"; port-index = <0>; bus-width = <2>; remote-endpoint = <&e3333_ov5693_out0>; }; }; override@14 { target = <&csi_chan0_port1>; _overlay_ { status = "okay"; }; }; override@15 { target = <&e3333_csi_out0>; _overlay_ { status = "okay"; remote-endpoint = <&e3333_vi_in0>; }; }; override@16 { target = <&e3333_cam1>; _overlay_ { status = "okay"; }; }; override@17 { target = <&cam_module1>; _overlay_ { status = "okay"; badge = "e3333_centerleft_P5V27C"; position = "centerleft"; orientation = "1"; }; }; override@18 { target = <&cam_module1_drivernode0>; _overlay_ { status = "okay"; pcl_id = "v4l2_sensor"; devname = "ov5693 31-0036"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9548@77/i2c@1/ov5693_b@36"; }; }; override@19 { target = <&cam_module1_drivernode1>; _overlay_ { status = "okay"; pcl_id = "v4l2_lens"; proc-device-tree = "/proc/device-tree/e3333_lens_ov5693@P5V27C/"; }; }; override@20 { target = <&vi_port1>; _overlay_ { status = "okay"; }; }; override@21 { target = <&e3333_vi_in1>; _overlay_ { status = "okay"; port-index = <1>; bus-width = <2>; remote-endpoint = <&e3333_csi_out1>; }; }; override@22 { target = <&csi_chan1>; _overlay_ { status = "okay"; }; }; override@23 { target = <&csi_chan1_port0>; _overlay_ { status = "okay"; }; }; override@24 { target = <&e3333_csi_in1>; _overlay_ { status = "okay"; port-index = <1>; bus-width = <2>; remote-endpoint = <&e3333_ov5693_out1>; }; }; override@25 { target = <&csi_chan1_port1>; _overlay_ { status = "okay"; }; }; override@26 { target = <&e3333_csi_out1>; _overlay_ { status = "okay"; remote-endpoint = <&e3333_vi_in1>; }; }; override@27 { target = <&e3333_cam2>; _overlay_ { status = "okay"; }; }; override@28 { target = <&cam_module2>; _overlay_ { status = "okay"; badge = "e3333_centerright_P5V27C"; position = "centerright"; orientation = "1"; }; }; override@29 { target = <&cam_module2_drivernode0>; _overlay_ { status = "okay"; pcl_id = "v4l2_sensor"; devname = "ov5693 32-0036"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9548@77/i2c@2/ov5693_c@36"; }; }; override@30 { target = <&cam_module2_drivernode1>; _overlay_ { status = "okay"; pcl_id = "v4l2_lens"; proc-device-tree = "/proc/device-tree/e3333_lens_ov5693@P5V27C/"; }; }; override@31 { target = <&vi_port2>; _overlay_ { status = "okay"; }; }; override@32 { target = <&e3333_vi_in2>; _overlay_ { status = "okay"; port-index = <2>; bus-width = <2>; remote-endpoint = <&e3333_csi_out2>; }; }; override@33 { target = <&csi_chan2>; _overlay_ { status = "okay"; }; }; override@34 { target = <&csi_chan2_port0>; _overlay_ { status = "okay"; }; }; override@35 { target = <&e3333_csi_in2>; _overlay_ { status = "okay"; port-index = <2>; bus-width = <2>; remote-endpoint = <&e3333_ov5693_out2>; }; }; override@36 { target = <&csi_chan2_port1>; _overlay_ { status = "okay"; }; }; override@37 { target = <&e3333_csi_out2>; _overlay_ { status = "okay"; remote-endpoint = <&e3333_vi_in2>; }; }; override@38 { target = <&e3333_cam3>; _overlay_ { status = "okay"; }; }; override@39 { target = <&cam_module3>; _overlay_ { status = "okay"; badge = "e3333_topleft_P5V27C"; position = "topleft"; orientation = "1"; }; }; override@40 { target = <&cam_module3_drivernode0>; _overlay_ { status = "okay"; pcl_id = "v4l2_sensor"; devname = "ov5693 33-0036"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9548@77/i2c@3/ov5693_d@36"; }; }; override@41 { target = <&cam_module3_drivernode1>; _overlay_ { status = "okay"; pcl_id = "v4l2_lens"; proc-device-tree = "/proc/device-tree/e3333_lens_ov5693@P5V27C/"; }; }; override@42 { target = <&vi_port3>; _overlay_ { status = "okay"; }; }; override@43 { target = <&e3333_vi_in3>; _overlay_ { status = "okay"; port-index = <3>; bus-width = <2>; remote-endpoint = <&e3333_csi_out3>; }; }; override@44 { target = <&csi_chan3>; _overlay_ { status = "okay"; }; }; override@45 { target = <&csi_chan3_port0>; _overlay_ { status = "okay"; }; }; override@46 { target = <&e3333_csi_in3>; _overlay_ { status = "okay"; port-index = <3>; bus-width = <2>; remote-endpoint = <&e3333_ov5693_out3>; }; }; override@47 { target = <&csi_chan3_port1>; _overlay_ { status = "okay"; }; }; override@48 { target = <&e3333_csi_out3>; _overlay_ { status = "okay"; remote-endpoint = <&e3333_vi_in3>; }; }; override@49 { target = <&e3333_cam4>; _overlay_ { status = "okay"; }; }; override@50 { target = <&cam_module4>; _overlay_ { status = "okay"; badge = "e3333_bottomright_P5V27C"; position = "bottomright"; orientation = "1"; }; }; override@51 { target = <&cam_module4_drivernode0>; _overlay_ { status = "okay"; pcl_id = "v4l2_sensor"; devname = "ov5693 34-0036"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9548@77/i2c@4/ov5693_e@36"; }; }; override@52 { target = <&cam_module4_drivernode1>; _overlay_ { status = "okay"; pcl_id = "v4l2_lens"; proc-device-tree = "/proc/device-tree/e3333_lens_ov5693@P5V27C/"; }; }; override@53 { target = <&vi_port4>; _overlay_ { status = "okay"; }; }; override@54 { target = <&e3333_vi_in4>; _overlay_ { status = "okay"; port-index = <4>; bus-width = <2>; remote-endpoint = <&e3333_csi_out4>; }; }; override@55 { target = <&csi_chan4>; _overlay_ { status = "okay"; }; }; override@56 { target = <&csi_chan4_port0>; _overlay_ { status = "okay"; }; }; override@57 { target = <&e3333_csi_in4>; _overlay_ { status = "okay"; port-index = <4>; bus-width = <2>; remote-endpoint = <&e3333_ov5693_out4>; }; }; override@58 { target = <&csi_chan4_port1>; _overlay_ { status = "okay"; }; }; override@59 { target = <&e3333_csi_out4>; _overlay_ { status = "okay"; remote-endpoint = <&e3333_vi_in4>; }; }; override@60 { target = <&e3333_cam5>; _overlay_ { status = "okay"; }; }; override@61 { target = <&cam_module5>; _overlay_ { status = "okay"; badge = "e3333_topright_P5V27C"; position = "topright"; orientation = "1"; }; }; override@62 { target = <&cam_module5_drivernode0>; _overlay_ { status = "okay"; pcl_id = "v4l2_sensor"; devname = "ov5693 35-0036"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9548@77/i2c@5/ov5693_g@36"; }; }; override@63 { target = <&cam_module5_drivernode1>; _overlay_ { status = "okay"; pcl_id = "v4l2_lens"; proc-device-tree = "/proc/device-tree/e3333_lens_ov5693@P5V27C/"; }; }; override@64 { target = <&vi_port5>; _overlay_ { status = "okay"; }; }; override@65 { target = <&e3333_vi_in5>; _overlay_ { status = "okay"; port-index = <5>; bus-width = <2>; remote-endpoint = <&e3333_csi_out5>; }; }; override@66 { target = <&csi_chan5>; _overlay_ { status = "okay"; }; }; override@67 { target = <&csi_chan5_port0>; _overlay_ { status = "okay"; }; }; override@68 { target = <&e3333_csi_in5>; _overlay_ { status = "okay"; port-index = <6>; bus-width = <2>; remote-endpoint = <&e3333_ov5693_out5>; }; }; override@69 { target = <&csi_chan5_port1>; _overlay_ { status = "okay"; }; }; override@70 { target = <&e3333_csi_out5>; _overlay_ { status = "okay"; remote-endpoint = <&e3333_vi_in5>; }; }; override@71 { target = <&{/gpio@2200000}>; _overlay_ { camera-control-input { status = "disabled"; }; camera-control-output-low { gpio-hog; gpios = <((7 * 8) + 3) 0 ((7 * 8) + 6) 0 ((19 * 8) + 6) 0 ((19 * 8) + 5) 0>; label = "cam0-rst", "cam0-pwdn", "cam1-rst", "cam1-pwdn"; output-low; status = "okay"; }; camera-control-output-high { status = "disabled"; }; }; }; override@72 { target = <&tca6408_21>; _overlay_ { tca6408_21_input { status = "disabled"; }; tca6408_21_outlow { gpio-hog; gpios = <0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0>; output-low; label = "tca6408_21_outlow_0", "tca6408_21_outlow_1", "tca6408_21_outlow_2", "tca6408_21_outlow_3", "tca6408_21_outlow_4", "tca6408_21_outlow_5", "tca6408_21_outlow_6", "tca6408_21_outlow_7"; status = "okay"; }; tca6408_21_outhigh { status = "disabled"; }; }; }; override@73 { target = <&cam_i2c>; _overlay_ { compatible = "nvidia,tegra194-i2c"; }; }; }; fragment-imx274@0 { ids = "LPRD-002002"; override@0 { target = <&imx274_cam0>; _overlay_ { status = "okay"; }; }; override@1 { target = <&cam_module0>; _overlay_ { status = "okay"; badge = "imx274_bottom_A6V26"; position = "bottom"; orientation = "0"; }; }; override@2 { target = <&cam_module0_drivernode0>; _overlay_ { status = "okay"; pcl_id = "v4l2_sensor"; devname = "imx274 30-001a"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9546@70/i2c@0/imx274_a@1a"; }; }; override@3 { target = <&cam_module0_drivernode1>; _overlay_ { status = "okay"; pcl_id = "v4l2_lens"; proc-device-tree = "/proc/device-tree/lens_imx274@A6V26/"; }; }; override@4 { target = <&vi_base>; _overlay_ { num-channels=<1>; }; }; override@5 { target = <&vi_port0>; _overlay_ { status = "okay"; }; }; override@6 { target = <&liimx274_vi_in0>; _overlay_ { status = "okay"; port-index = <0>; bus-width = <4>; remote-endpoint = <&liimx274_csi_out0>; }; }; override@7 { target = <&csi_base>; _overlay_ { num-channels=<1>; }; }; override@8 { target = <&csi_chan0>; _overlay_ { status = "okay"; }; }; override@9 { target = <&csi_chan0_port0>; _overlay_ { status = "okay"; }; }; override@10 { target = <&liimx274_csi_in0>; _overlay_ { status = "okay"; port-index = <0>; bus-width = <4>; remote-endpoint = <&liimx274_imx274_out0>; }; }; override@11 { target = <&csi_chan0_port1>; _overlay_ { status = "okay"; }; }; override@12 { target = <&liimx274_csi_out0>; _overlay_ { status = "okay"; remote-endpoint = <&liimx274_vi_in0>; }; }; override@13 { target = <&tcp>; _overlay_ { num_csi_lanes = <4>; max_lane_speed = <1500000>; min_bits_per_pixel = <10>; vi_peak_byte_per_pixel = <2>; vi_bw_margin_pct = <25>; isp_peak_byte_per_pixel = <5>; isp_bw_margin_pct = <25>; }; }; override@14 { target = <&tca9546_70>; _overlay_ { status = "okay"; }; }; override@15 { target = <&{/gpio@2200000}>; _overlay_ { camera-control-input { status = "disabled"; }; camera-control-output-low { status = "disabled"; }; camera-control-output-high { gpio-hog; gpios = <((7 * 8) + 3) 0>; label = "cam0-rst"; output-high; status = "okay"; }; }; }; override@16 { target = <&pca9570_a_24>; _overlay_ { status = "okay"; }; }; override@17 { target = <&imx390_cam0>; _overlay_ { status = "disabled"; }; }; override@18 { target = <&imx390_cam1>; _overlay_ { status = "disabled"; }; }; override@19 { target = <&cam_module1>; _overlay_ { status = "disabled"; }; }; }; fragment-imx274-dual@0 { ids = "LPRD-dual-imx274-002"; override@0 { target = <&imx274_cam0>; _overlay_ { status = "okay"; }; }; override@1 { target = <&cam_module0>; _overlay_ { status = "okay"; badge = "imx274_bottom_A6V26"; position = "bottom"; orientation = "0"; }; }; override@2 { target = <&cam_module0_drivernode0>; _overlay_ { status = "okay"; pcl_id = "v4l2_sensor"; devname = "imx274 30-001a"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9546@70/i2c@0/imx274_a@1a"; }; }; override@3 { target = <&cam_module0_drivernode1>; _overlay_ { status = "okay"; pcl_id = "v4l2_lens"; proc-device-tree = "/proc/device-tree/lens_imx274@A6V26/"; }; }; override@4 { target = <&imx274_cam1>; _overlay_ { status = "okay"; }; }; override@5 { target = <&cam_module1>; _overlay_ { status = "okay"; badge = "imx274_top_A6V26"; position = "top"; orientation = "0"; }; }; override@6 { target = <&cam_module1_drivernode0>; _overlay_ { status = "okay"; pcl_id = "v4l2_sensor"; devname = "imx274 31-001a"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9546@70/i2c@1/imx274_c@1a"; }; }; override@7 { target = <&cam_module1_drivernode1>; _overlay_ { status = "okay"; pcl_id = "v4l2_lens"; proc-device-tree = "/proc/device-tree/lens_imx274@A6V26/"; }; }; override@8 { target = <&vi_base>; _overlay_ { num-channels=<2>; }; }; override@9 { target = <&vi_port0>; _overlay_ { status = "okay"; }; }; override@10 { target = <&vi_port1>; _overlay_ { status = "okay"; }; }; override@11 { target = <&liimx274_vi_in0>; _overlay_ { status = "okay"; port-index = <0>; bus-width = <4>; remote-endpoint = <&liimx274_csi_out0>; }; }; override@12 { target = <&liimx274_vi_in1>; _overlay_ { status = "okay"; port-index = <2>; bus-width = <4>; remote-endpoint = <&liimx274_csi_out1>; }; }; override@13{ target = <&csi_base>; _overlay_ { num-channels=<2>; }; }; override@14 { target = <&csi_chan0>; _overlay_ { status = "okay"; }; }; override@15 { target = <&csi_chan0_port0>; _overlay_ { status = "okay"; }; }; override@16 { target = <&liimx274_csi_in0>; _overlay_ { status = "okay"; port-index = <0>; bus-width = <4>; remote-endpoint = <&liimx274_imx274_out0>; }; }; override@17 { target = <&csi_chan0_port1>; _overlay_ { status = "okay"; }; }; override@18 { target = <&liimx274_csi_out0>; _overlay_ { status = "okay"; }; }; override@19 { target = <&csi_chan1>; _overlay_ { status = "okay"; }; }; override@20 { target = <&csi_chan1_port0>; _overlay_ { status = "okay"; }; }; override@21 { target = <&liimx274_csi_in1>; _overlay_ { status = "okay"; port-index = <2>; bus-width = <4>; remote-endpoint = <&liimx274_imx274_out1>; }; }; override@22 { target = <&csi_chan1_port1>; _overlay_ { status = "okay"; }; }; override@23 { target = <&liimx274_csi_out1>; _overlay_ { status = "okay"; }; }; override@24 { target = <&tcp>; _overlay_ { num_csi_lanes = <8>; max_lane_speed = <1500000>; min_bits_per_pixel = <10>; vi_peak_byte_per_pixel = <2>; vi_bw_margin_pct = <25>; isp_peak_byte_per_pixel = <5>; isp_bw_margin_pct = <25>; }; }; override@25 { target = <&tca9546_70>; _overlay_ { status = "okay"; }; }; override@26 { target = <&{/gpio@2200000}>; _overlay_ { camera-control-input { status = "disabled"; }; camera-control-output-low { status = "disabled"; }; camera-control-output-high { gpio-hog; gpios = <((7 * 8) + 3) 0 ((7 * 8) + 6) 0>; label = "cam0-rst", "cam1-rst"; output-high; status = "okay"; }; }; }; }; fragment-e3331@0 { ids = "3331-*"; override@0 { target = <&vi_base>; _overlay_ { num-channels=<1>; }; }; override@1 { target = <&csi_base>; _overlay_ { num-channels=<1>; }; }; override@2 { target = <&tcp>; _overlay_ { num_csi_lanes = <3>; max_lane_speed = <1500000>; min_bits_per_pixel = <10>; vi_peak_byte_per_pixel = <2>; vi_bw_margin_pct = <25>; max_pixel_rate = <160000>; isp_peak_byte_per_pixel = <5>; isp_bw_margin_pct = <25>; }; }; override@4 { target = <&tca9546_70>; _overlay_ { status = "okay"; }; }; override@5 { target = <&e3331_cam0>; _overlay_ { status = "okay"; }; }; override@6 { target = <&cam_module0>; _overlay_ { status = "okay"; badge = "e3331_rear_22N02A"; position = "rear"; orientation = "1"; }; }; override@7 { target = <&cam_module0_drivernode0>; _overlay_ { status = "okay"; pcl_id = "v4l2_sensor"; devname = "imx318 30-0010"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9546@70/i2c@0/imx318_a@10"; }; }; override@9 { target = <&vi_port0>; _overlay_ { status = "okay"; }; }; override@10 { target = <&e3331_vi_in0>; _overlay_ { status = "okay"; port-index = <0>; bus-width = <3>; remote-endpoint = <&e3331_csi_out0>; }; }; override@11 { target = <&csi_chan0>; _overlay_ { status = "okay"; }; }; override@12 { target = <&csi_chan0_port0>; _overlay_ { status = "okay"; }; }; override@13 { target = <&e3331_csi_in0>; _overlay_ { status = "okay"; port-index = <0>; bus-width = <3>; remote-endpoint = <&e3331_imx318_out0>; }; }; override@14 { target = <&csi_chan0_port1>; _overlay_ { status = "okay"; }; }; override@15 { target = <&e3331_csi_out0>; _overlay_ { status = "okay"; remote-endpoint = <&e3331_vi_in0>; }; }; override@71 { target = <&{/gpio@2200000}>; _overlay_ { camera-control-input { status = "disabled"; }; camera-control-output-low { gpio-hog; gpios = <((7 * 8) + 3) 0>; label = "cam0-rst"; output-low; status = "okay"; }; camera-control-output-high { status = "disabled"; }; }; }; }; fragment-e3377@0 { ids = "3377-1000-*"; override@0 { target = <&e3377_cam0>; _overlay_ { status = "okay"; }; }; override@1 { target = <&cam_module0>; _overlay_ { status = "okay"; badge = "e3377_rear_IMX204"; position = "rear"; orientation = "1"; }; }; override@2 { target = <&cam_module0_drivernode0>; _overlay_ { status = "okay"; pcl_id = "v4l2_sensor"; devname = "imx204_spi"; proc-device-tree = "/proc/device-tree/spi@c260000/imx204@0"; }; }; override@4 { target = <&vi_base>; _overlay_ { num-channels=<1>; }; }; override@5 { target = <&vi_port0>; _overlay_ { status = "okay"; }; }; override@6 { target = <&e3377_vi_in0>; _overlay_ { status = "okay"; port-index = <0>; bus-width = <8>; remote-endpoint = <&e3377_slvs_ec_out0>; }; }; override@8 { target = <&slvs_ec_stream0>; _overlay_ { status = "okay"; }; }; override@9 { target = <&slvs_ec_stream0_port0>; _overlay_ { status = "okay"; }; }; override@10 { target = <&e3377_slvs_ec_in0>; _overlay_ { status = "okay"; port-index = <0>; bus-width = <8>; remote-endpoint = <&e3377_imx204_out0>; }; }; override@11 { target = <&slvs_ec_stream0_port1>; _overlay_ { status = "okay"; }; }; override@12 { target = <&e3377_slvs_ec_out0>; _overlay_ { status = "okay"; remote-endpoint = <&e3377_vi_in0>; }; }; override@13 { target = <&slvs_ec_base>; _overlay_ { status = "okay"; }; }; override@14 { target = <&{/gpio@2200000}>; _overlay_ { camera-control-input { status = "disabled"; }; camera-control-output-low { gpio-hog; gpios = <((24 * 8) + 1) 0>; label = "slvs-cam0-rst"; output-low; status = "okay"; }; camera-control-output-high { status = "disabled"; }; }; }; override@15 { target = <&spi_cam0>; _overlay_ { status = "okay"; }; }; }; fragment-imx185@0 { ids = "LPRD-002001"; override@0 { target = <&imx185_cam0>; _overlay_ { status = "okay"; }; }; override@1 { target = <&cam_module0>; _overlay_ { status = "okay"; badge = "imx185_bottom_liimx185"; position = "bottom"; orientation = "0"; }; }; override@2 { target = <&cam_module0_drivernode0>; _overlay_ { status = "okay"; pcl_id = "v4l2_sensor"; devname = "imx185 30-001a"; proc-device-tree = "/proc/device-tree/i2c@3180000/tca9546@70/i2c@0/imx185_a@1a"; }; }; override@3 { target = <&cam_module0_drivernode1>; _overlay_ { status = "okay"; pcl_id = "v4l2_lens"; }; }; override@4 { target = <&vi_base>; _overlay_ { num-channels=<1>; }; }; override@5 { target = <&vi_port0>; _overlay_ { status = "okay"; }; }; override@6 { target = <&liimx185_vi_in0>; _overlay_ { status = "okay"; port-index = <0>; bus-width = <4>; remote-endpoint = <&liimx185_csi_out0>; }; }; override@7 { target = <&csi_base>; _overlay_ { num-channels=<1>; }; }; override@8 { target = <&csi_chan0>; _overlay_ { status = "okay"; }; }; override@9 { target = <&csi_chan0_port0>; _overlay_ { status = "okay"; }; }; override@10 { target = <&liimx185_csi_in0>; _overlay_ { status = "okay"; port-index = <0>; bus-width = <4>; remote-endpoint = <&liimx185_imx185_out0>; }; }; override@11 { target = <&csi_chan0_port1>; _overlay_ { status = "okay"; }; }; override@12 { target = <&liimx185_csi_out0>; _overlay_ { status = "okay"; remote-endpoint = <&liimx185_vi_in0>; }; }; override@13 { target = <&tcp>; _overlay_ { num_csi_lanes = <4>; max_lane_speed = <1500000>; min_bits_per_pixel = <10>; vi_peak_byte_per_pixel = <2>; vi_bw_margin_pct = <25>; isp_peak_byte_per_pixel = <5>; isp_bw_margin_pct = <25>; }; }; override@14 { target = <&tca9546_70>; _overlay_ { status = "okay"; }; }; override@15 { target = <&pca9570_a_24>; _overlay_ { status = "okay"; }; }; override@16 { target = <&imx390_cam0>; _overlay_ { status = "disabled"; }; }; override@17 { target = <&imx390_cam1>; _overlay_ { status = "disabled"; }; }; override@18 { target = <&cam_module1>; _overlay_ { status = "disabled"; }; }; }; fragment-p2822-cam0-rst@0 { ids = "<2822-0000-500"; override@0 { target = <&{/gpio@2200000/camera-control-output-low}>; _overlay_ { gpios = <((7 * 8) + 4) 0 ((7 * 8) + 6) 0 ((19 * 8) + 6) 0 ((19 * 8) + 5) 0 ((24 * 8) + 1) 0>; label = "cam0-rst", "cam0-pwdn", "cam1-rst", "cam1-pwdn", "slvs-cam0-rst"; }; }; override@1 { target = <&{/gpio@2200000/camera-control-output-high}>; _overlay_ { gpios = <((7 * 8) + 4) 0 ((7 * 8) + 6) 0>; label = "cam0-rst", "cam1-rst"; }; }; override@2 { target = <&{/i2c@3180000/ov5693_c@36}>; _overlay_ { reset-gpios = <&tegra_main_gpio ((7 * 8) + 4) 0>; }; }; override@3 { target = <&{/i2c@3180000/tca9546@70/i2c@0/imx318_a@10}>; _overlay_ { reset-gpios = <&tegra_main_gpio ((7 * 8) + 4) 0>; }; }; override@4 { target = <&{/i2c@3180000/tca9548@77/i2c@0/ov5693_a@36}>; _overlay_ { reset-gpios = <&tegra_main_gpio ((7 * 8) + 4) 0>; }; }; override@5 { target = <&{/i2c@3180000/tca9546@70/i2c@0/imx185_a@1a}>; _overlay_ { reset-gpios = <&tegra_main_gpio ((7 * 8) + 4) 0>; }; }; override@6 { target = <&{/i2c@3180000/tca9546@70/i2c@0/imx274_a@1a}>; _overlay_ { reset-gpios = <&tegra_main_gpio ((7 * 8) + 4) 0>; }; }; override@7 { target = <&{/i2c@3180000/tca9546@70/i2c@0/imx390_a@1b}>; _overlay_ { reset-gpios = <&tegra_main_gpio ((7 * 8) + 4) 0>; }; }; }; }; }; # 24 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/tegra194-p2888-0001-p2822-0000.dts" 2 # 1 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/iei_psm_amb_gen3.dtsi" 1 # 36 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/iei_psm_amb_gen3.dtsi" &head0 { avdd_hdmi-supply = <&p2888_spmic_sd0>; avdd_hdmi_pll-supply = <&p2888_spmic_sd1>; # 55 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/iei_psm_amb_gen3.dtsi" nvidia,dc-connector = <&sor1>; status = "okay"; }; &head1 { avdd_hdmi-supply = <&p2888_spmic_sd0>; avdd_hdmi_pll-supply = <&p2888_spmic_sd1>; nvidia,dc-connector = <&sor0>; status = "okay"; }; &head2 { avdd_hdmi-supply = <&p2888_spmic_sd0>; avdd_hdmi_pll-supply = <&p2888_spmic_sd1>; # 100 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/iei_psm_amb_gen3.dtsi" status = "okay"; nvidia,dc-connector = <&sor2>; }; &sor1_hdmi_display { status = "okay"; disp-default-out { nvidia,out-flags = <(1 << 1)>; }; }; # 147 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/iei_psm_amb_gen3.dtsi" &sor0 { status = "okay"; nvidia,active-panel = <&sor0_hdmi_display>; }; &sor0_dp_display { status = "disabled"; }; &sor0_hdmi_display { status = "okay"; }; &sor1 { status = "okay"; nvidia,active-panel = <&sor1_hdmi_display>; }; &sor1_dp_display { status = "disabled"; }; &sor1_hdmi_display { status = "okay"; }; &sor2 { status = "okay"; nvidia,active-panel = <&sor2_hdmi_display>; }; &sor2_dp_display { status = "disabled"; }; &sor2_hdmi_display { status = "okay"; }; # 24 "/home/share/NVDIA_DATA/Tegra186_git_3261_org/tegra186/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/galen/kernel-dts/tegra194-p2888-0001-p2822-0000.dts" 2