/*
* imx490_mode_tbls.h - imx490 sensor mode tables
*
* Copyright (c) 2021, Leopard Imaging Inc. All rights reserved.
*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*/
#ifndef __IMX490_I2C_TABLES__
#define __IMX490_I2C_TABLES__
#include
#define IMX490_TABLE_WAIT_MS 0xff00
#define IMX490_TABLE_END 0xff01
#define IMX490_MAX_RETRIES 3
#define IMX490_WAIT_MS_STOP 1
#define IMX490_WAIT_MS_START 30
/* #define INIT_ET_INSETTING 1 */
struct index_reg_8 {
u16 source;
u16 addr;
u8 val;
};
#define imx490_reg struct index_reg_8
static imx490_reg imx490_start[] = {
// {0x06, 0x3C00, 0x5C},
// {0x06, 0x3C00, 0xA3},
// {0x00, IMX490_TABLE_END, 0x00}
{0x90, 0x0313, 0x00},
{0x80, 0x02BE, 0x10},
{0x80, 0x0057, 0x12},
{0x80, 0x005B, 0x11},
{0x80, 0x0318, 0x5E},
{0x80, 0x02D3, 0x10},
// {0x82, 0x2D3, 0x00},
{0x80, 0x2D3, 0x00},
{0x90, 0x0320, 0x2c},
{0x90, 0x0313, 0x02},
// {0x00, IMX490_TABLE_END, 0x00}
};
static imx490_reg imx490_stop[] = {
// {0x00, IMX490_TABLE_END, 0x00}
};
static imx490_reg imx490_Double_Dser_Ser1[] = {
// {0x90, 0x0313, 0x00},
// {0x90, 0x003, 0x40},//disable uart
// {0x80, 0x02BE, 0x10},
// {0x80, 0x0057, 0x12},
// {0x80, 0x005B, 0x11},
// {0x80, 0x0318, 0x5E},
// {0x80, 0x02D3, 0x10},
};
static imx490_reg imx490_Double_Dser_Ser[] = {
// {0x90, 0x0313, 0x00},
// {0x90, 0x003, 0x40},//disable uart
// {0x80, 0x000, 0x82},
// {0x82, 0x02BE, 0x10},
// {0x82, 0x0057, 0x12},
// {0x82, 0x005B, 0x11},
// {0x82, 0x0318, 0x5E},
// {0x82, 0x02D3, 0x10},
// {0x90, 0x010, 0x22},// Disable auto-link on Des
// {0x80, 0x000, 0x88},//change serializer address on Link B
// {0x90, 0x010, 0x23},//#-9295B-trigger-#
// {0x80, 0x02BE, 0x10},
// {0x80, 0x0057, 0x12},
// {0x80, 0x005B, 0x11},
// {0x80, 0x0318, 0x5E},
// {0x80, 0x02D3, 0x10},
// {0xC0, 0x006B, 0x12},
// {0xC0, 0x0073, 0x13},
// {0xC0, 0x007B, 0x32},
// {0xC0, 0x0083, 0x32},
// {0xC0, 0x008B, 0x32},
// {0xC0, 0x0093, 0x32},
// {0xC0, 0x009B, 0x32},
// {0xC0, 0x00A3, 0x32},
// {0xC0, 0x00AB, 0x32},
// {0x90, 0x0010, 0x23},
// {0xc0, 0x0010, 0x21},
// {0x80, 0x0010, 0x21},
// /* {0xc0, 0x0010, 0x31}, // Apply Reset Oneshot for changes */
// /* Serializer MIPI} CSI-2 PHY settings */
// /* configure for linkA */
// {0xc0, 0x0330, 0x10}, /* Set SER to 1x4 mode (phy_config = 0) */
// {0xc0, 0x0332, 0xEE}, // Verify lane map is at its default (phy1_lane_map = 4'hE, phy2_lane_map = 4'h4 )
// {0xc0, 0x0333, 0xE4}, /* Additional lane map */
// {0xc0, 0x0331, 0x30}, /* Set 4 lanes for serializer (ctrl1_num_lanes = 3) */
// {0xc0, 0x0311, 0x30}, /* Start video from both port A and port B. */
// {0xc0, 0x0308, 0x63}, /* Enable info lines. Additional start bits for Port A and B. Use data from port B for all pipelines. */
// /* Serializer Data}type to Video Pipe routing */
// {0xc0, 0x0314, 0x5e}, //0x22/* Route 16bit DCG (DT = 0x30) to VIDEO_X (Bit 6 enable) */
// {0xc0, 0x0316, 0x62}, //0x6C /* Route 12bit RAW (DT = 0x2C) to VIDEO_Y (Bit 6 enable) */
// {0xc0, 0x0318, 0x62}, //0x22/* Route EMBEDDED8 to VIDEO_Z (Bit 6 enable) */
// {0xc0, 0x031A, 0x62}, /* Unused VIDEO_U */
// /* Serializer enab}le video data transmission from serializer to deserializer. */
// {0xc0, 0x0002, 0x33}, /* Make sure all pipelines start transmission (VID_TX_EN_X/Y/Z/U = 1) */
// {0xc0, 0x0042, 0x36},//0x1b
// {0xc0, 0x0043, 0x34},//0x1A
// {0xc0, 0x02be, 0x90}, /* Enable sensor power down pin. */
// {0xc0, 0x02bf, 0x60}, /* Enable sensor reset pin. */
// {0xc0, 0x03F1, 0x89}, /* Output RCLK to senso */
// /* {0x90, 0x0010, 0x31}, // Apply Reset Oneshot for changes */
// /* {0x80, 0x0010, 0x21}, // Apply Reset Oneshot for changes */
// /* Serializer MIPI} CSI-2 PHY settings */
// {0x80, 0x0330, 0x10}, /* Set SER to 1x4 mode (phy_config = 0) */
// {0x80, 0x0332, 0xEE}, // Verify lane map is at its default (phy1_lane_map = 4'hE, phy2_lane_map = 4'h4 )
// {0x80, 0x0333, 0xE4}, /* Additional lane map */
// {0x80, 0x0331, 0x30}, /* Set 4 lanes for serializer (ctrl1_num_lanes = 3) */
// {0x80, 0x0311, 0xc0}, /* Start video from and port B. */
// {0x80, 0x0308, 0x6c}, /* Enable info lines. Additional start bits for Port A and B. Use data from port B for all pipelines. */
// /* Serializer Data}type to Video Pipe routing */
// {0x80, 0x0314, 0x62}, /* Route 16bit DCG (DT = 0x30) to VIDEO_X (Bit 6 enable) */
// {0x80, 0x0316, 0x62}, /* Route 12bit RAW (DT = 0x2C) to VIDEO_Y (Bit 6 enable) */
// {0x80, 0x0318, 0x5e}, //0x6C/* Route EMBEDDED8 to VIDEO_Z (Bit 6 enable) */
// {0x80, 0x031A, 0x62}, /* Unused VIDEO_U */
// /* Serializer enab}le video data transmission from serializer to deserializer. */
// {0x80, 0x0002, 0xc3}, /* Make sure all pipelines start transmission (VID_TX_EN_X/Y/Z/U = 1) */
// {0x80, 0x0042, 0x38},//0x1c
// {0x80, 0x0043, 0x34},//0x1A
// {0x80, 0x02be, 0x90}, /* Enable sensor power down pin. */
// {0x80, 0x02bf, 0x60}, /* Enable sensor reset pin. */
// {0x80, 0x03F1, 0x89}, /* Output RCLK to senso */
// {0x90, 0x0330, 0x04}, /* Set MIPI Phy Mode: 2x(1x4) mode */
// {0x90, 0x0333, 0x4E}, /* lane maps - all 4 ports mapped straight */
// {0x90, 0x0334, 0xE4}, /* Additional lane map */
// {0x90, 0x040A, 0x00}, /* lane count - 0 lanes striping on controller 0 (Port A slave in 2x1x4 mode). */
// {0x90, 0x044A, 0x40}, /* lane count - 2 lanes striping on controller 1 (Port A master in 2x1x4 mode). */
// {0x90, 0x048A, 0x40}, /* lane count - 2 lanes striping on controller 2 (Port B master in 2x1x4 mode). */
// {0x90, 0x04CA, 0x00}, /* lane count - 0 lanes striping on controller 3 (Port B slave in 2x1x4 mode). */
// /* Deserializer MI}PI CSI-2 clock rate settings. */
// {0x90, 0x031D, 0x2f}, /* MIPI clock rate - 1.5Gbps from controller 0 clock (Port A slave in 2x1x4 mode). */
// {0x90, 0x0320, 0x2f}, /* MIPI clock rate - 1.5Gbps from controller 1 clock (Port A master in 2x1x4 mode). */
// {0x90, 0x0323, 0x2f}, /* MIPI clock rate - 1.5Gbps from controller 2 clock (Port B master in 2x1x4 mode). */
// {0x90, 0x0326, 0x2f}, /* MIPI clock rate - 1.5Gbps from controller 2 clock (Port B slave in 2x1x4 mode). */
// /* Deserializer st}ream select programming. */
// /* {0x90, 0x0050, 0x03}, // Route data from stream 0 to pipe X */
// {0x90, 0x0051, 0x01}, /* Route data from stream 0 to pipe Y MAXIM INTEGRATED CONFIDENTIAL */
// {0x90, 0x0052, 0x02}, /* Route data from stream 0 to pipe Z */
// /* {0xD4, 0x0053, 0x00}, Route data from stream 0 to pipe U */
// {0x90, 0x0332, 0xF0}, /* Enable all PHYS. */
// // {0x90, 0x0332, 0x00}, /* Disable all PHYS. */
// {0x00, IMX490_TABLE_END, 0x00 }
// {0x90, 0x313, 0x00},
// {0x90, 0x003, 0x40},//disable uart
// // {0x90, 0x010, 0x21},// Disable auto-link on Des
// {0x80, 0x000, 0x82},//change serializer address on Link A
// {0x82, 0x06b, 0x16},// set TX_SRC_ID on serializer to mimic that of what config setting 13 would have, change packet IDs for one Ser,
// {0x82, 0x073, 0x17},
// {0x82, 0x07b, 0x36},
// {0x82, 0x083, 0x36},
// {0x82, 0x093, 0x36},
// {0x82, 0x09b, 0x36},
// {0x82, 0x0a3, 0x36},
// {0x82, 0x0ab, 0x36},
// {0x82, 0x08b, 0x36},
// {0x90, 0x010, 0x22},// Disable auto-link on Des
// // {0x80, 0x000, 0x88},//change serializer address on Link B
// {0x90, 0x010, 0x23},//#-9295B-trigger-#
// //set deserializer into reverse-splitter mode important!!!!!! 0x21 ---> link A 0x22---> linkļ¼¢ 0x23--->spiliter mode
// {0x80, 0x2D3, 0x00},//trigger map mfp7_9295
// {0x80, 0x2D3, 0x10},
// {0x82, 0x2D3, 0x00},
// {0x82, 0x2D3, 0x10},
// {0x90, 0x010, 0x23},//set deserializer into reverse-splitter mode important!!!!!! 0x21 ---> link A 0x22---> linkļ¼¢ 0x23--->spiliter mode
// {0x80, 0x330, 0x00},//Make sure that the SER is in 1x4 mode (phy_config = 0) max9295A has one four lane port
// {0x80, 0x332, 0xee},
// {0x80, 0x333, 0xe4},
// {0x80, 0x331, 0x33},
// {0x80, 0x311, 0xf0},
// {0x80, 0x308, 0x7f},
// {0x80, 0x314, 0x5e},
// {0x80, 0x316, 0x62},
// {0x80, 0x318, 0x62},
// {0x80, 0x31a, 0x62},
// {0x80, 0x002, 0xf3},
// {0x80, 0x2be, 0x10},
// {0x82, 0x330, 0x00},
// {0x82, 0x332, 0xee},
// {0x82, 0x333, 0xe4},
// {0x82, 0x331, 0x33},
// {0x82, 0x311, 0xf0},
// {0x82, 0x308, 0x7f},
// {0x82, 0x314, 0x62},
// {0x82, 0x316, 0x62},
// {0x82, 0x318, 0x5e},
// {0x82, 0x31a, 0x62},
// {0x82, 0x002, 0xf3},
// {0x82, 0x2be, 0x10},
// {0x90, 0x330, 0x04},
// {0x90, 0x332, 0xf0},
// {0x90, 0x333, 0x4e},
// // {0x90, 0x040A, 0x00}, /* lane count - 0 lanes striping on controller 0 (Port A slave in 2x1x4 mode). */
// // {0x90, 0x044A, 0x40}, /* lane count - 2 lanes striping on controller 1 (Port A master in 2x1x4 mode). */
// // {0x90, 0x048A, 0x40}, /* lane count - 2 lanes striping on controller 2 (Port B master in 2x1x4 mode). */
// // {0x90, 0x04CA, 0x00}, /* lane count - 0 lanes striping on controller 3 (Port B slave in 2x1x4 mode). */
// {0x90, 0x320, 0x38},
// {0x90, 0x323, 0x38},
// // {0x90, 0x031D, 0x2c}, /* MIPI clock rate - 1.5Gbps from controller 0 clock (Port A slave in 2x1x4 mode). */
// // {0x90, 0x0320, 0x2c}, /* MIPI clock rate - 1.5Gbps from controller 1 clock (Port A master in 2x1x4 mode). */
// // {0x90, 0x0323, 0x2c}, /* MIPI clock rate - 1.5Gbps from controller 2 clock (Port B master in 2x1x4 mode). */
// // {0x90, 0x0326, 0x2c}, /* MIPI clock rate - 1.5Gbps from controller 2 clock (Port B slave in 2x1x4 mode). */
// {0x90, 0x050, 0x00},
// {0x90, 0x051, 0x01},
// {0x90, 0x052, 0x02},
// {0x90, 0x053, 0x03},
// {0x90, 0x002, 0xf3},
// {0x90, 0x40b, 0x07},
// {0x90, 0x42d, 0x15},
// {0x90, 0x40d, 0x1e},
// {0x90, 0x40e, 0x5e},
// {0x90, 0x40f, 0x00},
// {0x90, 0x410, 0x40},
// {0x90, 0x411, 0x01},
// {0x90, 0x412, 0x41},
// {0x90, 0x48b, 0x07},
// {0x90, 0x4ad, 0x15},
// {0x90, 0x48d, 0x1e},
// {0x90, 0x48e, 0x1e},
// {0x90, 0x48f, 0x00},
// {0x90, 0x490, 0x00},
// {0x90, 0x491, 0x01},
// {0x90, 0x492, 0x01},
// {0x90, 0x010, 0x33},
// {0x90, 0x313, 0x02}
};
static imx490_reg imx490_2880x1860_crop_30fps[] = {
};
enum {
IMX490_MODE_2880x1860_CROP_30FPS,
IMX490_MODE_START_STREAM,
IMX490_MODE_STOP_STREAM,
IMX490_MODE_Dser_Ser,
IMX490_MODE_START_STREAM1,
};
static imx490_reg *mode_table[] = {
[IMX490_MODE_2880x1860_CROP_30FPS]
= imx490_2880x1860_crop_30fps,
[IMX490_MODE_START_STREAM]
= imx490_start,
[IMX490_MODE_STOP_STREAM]
= imx490_stop,
[IMX490_MODE_Dser_Ser]
= imx490_Double_Dser_Ser,
[IMX490_MODE_START_STREAM1]
= imx490_Double_Dser_Ser1,
};
static const int imx490_30fps[] = {
30,
};
static const struct camera_common_frmfmt imx490_frmfmt[] = {
// {{2880, 1860}, imx490_30fps, 1, 0, IMX490_MODE_2880x1860_CROP_30FPS},
};
#endif /* __IMX490_I2C_TABLES__ */