From 0670976b5cce1c7d2b86b6efd251cadc93f5f998 Mon Sep 17 00:00:00 2001 From: Mohan Kumar Date: Fri, 17 Apr 2020 13:13:39 +0530 Subject: [PATCH] soc: t18x: Configure I2S4 as sync clock for I2S1 Considering Tegra I2S4 operating as Slave and Tegra I2S1 configured as Master involves two different clock domains, which may lead to glitches. To avoid the drift in clock use I2S4 sync input clock as source for I2S1. Also this avoids extra changes to set right rate for PLLA and PLLA_OUT0, if I2S4 Capture is directly connected to I2S1 Capture without aplay/arecord. Change-Id: I5ccabaeeb7cfba8cc7da317a966fe6aa1bf50590 Signed-off-by: Mohan Kumar --- kernel-dts/tegra186-soc/tegra186-soc-base.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/kernel-dts/tegra186-soc/tegra186-soc-base.dtsi b/kernel-dts/tegra186-soc/tegra186-soc-base.dtsi index ac76509..0387bd0 100644 --- a/kernel-dts/tegra186-soc/tegra186-soc-base.dtsi +++ b/kernel-dts/tegra186-soc/tegra186-soc-base.dtsi @@ -2128,9 +2128,11 @@ <&tegra_car TEGRA186_CLK_I2S1_SYNC_INPUT>; clock-names = "i2s", "i2s_clk_parent", "ext_audio_sync", "audio_sync", "clk_sync_input"; - assigned-clocks = <&tegra_car TEGRA186_CLK_I2S1>; + assigned-clocks = <&tegra_car TEGRA186_CLK_I2S1>, + <&tegra_car TEGRA186_CLK_SYNC_I2S1>; assigned-clock-parents = - <&tegra_car TEGRA186_CLK_PLL_A_OUT0>; + <&tegra_car TEGRA186_CLK_SYNC_I2S1>, + <&tegra_car TEGRA186_CLK_I2S4_SYNC_INPUT>; assigned-clock-rates = <1536000>; pinctrl-names = "dap_active", "dap_inactive"; pinctrl-0 = <>; -- 2.17.1