diff --git a/bootloader/partner/t18x/cboot/app/logo.c b/bootloader/partner/t18x/cboot/app/logo.c
new file mode 100644
index 0000000..8f91a07
--- /dev/null
+++ b/bootloader/partner/t18x/cboot/app/logo.c
@@ -0,0 +1,202 @@
+#include <app.h>
+#include <debug.h>
+#include <err.h>
+#include <trace.h>
+#include <string.h>
+#include <sys/types.h>
+#include <assert.h>
+#include <kernel/thread.h>
+#include <tegrabl_gpio.h>
+#include <tegrabl_error.h>
+#include <soc/t194/tegrabl_gpio_hw.h>
+#include <address_map_new.h>
+#include <tegrabl_io.h>
+
+#define SPI_CPOL 0
+#define SPI_CPHA 0
+
+typedef enum {
+    OLED_GPIO_CLK       = 0,
+    OLED_GPIO_DIN       = 1,
+    OLED_GPIO_CS        = 2,
+    OLED_GPIO_DC        = 3,
+    OLED_GPIO_RST       = 4,
+    OLED_GPIO_ENUM_SIZE = 5
+} oled_gpio_t;
+
+static struct gpio_driver *gpio_main_drv, *gpio_aon_drv;
+
+static tegrabl_error_t pin_write(oled_gpio_t pin, gpio_pin_state_t state)
+{
+    struct gpio_driver *drv;
+    uint32_t tegra_pin;
+
+    switch (pin) {
+    case OLED_GPIO_CLK:
+        drv = gpio_main_drv;
+        tegra_pin = TEGRA_GPIO(Z, 3);
+        break;
+    case OLED_GPIO_DIN:
+        drv = gpio_main_drv;
+        tegra_pin = TEGRA_GPIO(Z, 5);
+        break;
+    case OLED_GPIO_CS:
+        drv = gpio_main_drv;
+        tegra_pin = TEGRA_GPIO(Z, 6);
+        break;
+    case OLED_GPIO_DC:
+        drv = gpio_main_drv;
+        tegra_pin = TEGRA_GPIO(Q, 5);
+        break;
+    case OLED_GPIO_RST:
+        drv = gpio_aon_drv;
+        tegra_pin = TEGRA_GPIO(CC, 4);
+        break;
+    default:
+        return TEGRABL_ERR_BAD_PARAMETER;
+    }
+
+    return gpio_write(drv, tegra_pin, state);
+}
+
+static tegrabl_error_t pin_config(oled_gpio_t pin, gpio_pin_mode_t mode)
+{
+    struct gpio_driver *drv;
+    uint32_t tegra_pin;
+
+    switch (pin) {
+    case OLED_GPIO_CLK:
+        drv = gpio_main_drv;
+        tegra_pin = TEGRA_GPIO(Z, 3);
+        break;
+    case OLED_GPIO_DIN:
+        drv = gpio_main_drv;
+        tegra_pin = TEGRA_GPIO(Z, 5);
+        break;
+    case OLED_GPIO_CS:
+        drv = gpio_main_drv;
+        tegra_pin = TEGRA_GPIO(Z, 6);
+        break;
+    case OLED_GPIO_DC:
+        drv = gpio_main_drv;
+        tegra_pin = TEGRA_GPIO(Q, 5);
+        break;
+    case OLED_GPIO_RST:
+        drv = gpio_aon_drv;
+        tegra_pin = TEGRA_GPIO(CC, 4);
+        break;
+    default:
+        return TEGRABL_ERR_BAD_PARAMETER;
+    }
+
+    return gpio_config(drv, tegra_pin, mode);
+}
+
+static void logo_init(const struct app_descriptor *app)
+{
+    tegrabl_error_t ret = TEGRABL_NO_ERROR;
+
+    NV_WRITE32(NV_ADDRESS_MAP_PADCTL_A0_BASE + 0xd040, 0x00000005); // Z3
+    NV_WRITE32(NV_ADDRESS_MAP_PADCTL_A0_BASE + 0xd058, 0x00000005); // Z5
+    NV_WRITE32(NV_ADDRESS_MAP_PADCTL_A0_BASE + 0xd010, 0x00000009); // Z6
+    NV_WRITE32(NV_ADDRESS_MAP_PADCTL_A0_BASE + 0x0028, 0x0000000a); // Q5
+
+    pr_info("OLED: init gpios\n");
+    // Get driver instances
+    ret = tegrabl_gpio_driver_get(TEGRA_GPIO_MAIN_CHIPID, &gpio_main_drv);
+    if (ret != TEGRABL_NO_ERROR) {
+        pr_error("Failed to get MAIN GPIO driver!\n");
+        //TEGRABL_SET_HIGHEST_MODULE(ret);
+        return;
+    }
+
+    ret = tegrabl_gpio_driver_get(TEGRA_GPIO_AON_CHIPID, &gpio_aon_drv);
+    if (ret != TEGRABL_NO_ERROR) {
+        pr_error("Failed to get AON GPIO driver!\n");
+        //TEGRABL_SET_HIGHEST_MODULE(ret);
+        return;
+    }
+
+    // Config pins
+    for (int i = 0; i < OLED_GPIO_ENUM_SIZE; i++) {
+        ret = pin_config(i, GPIO_PINMODE_OUTPUT);
+        if (ret != TEGRABL_NO_ERROR) {
+             pr_error("OLED: Failed to config GPIO pin %d\n", i);
+             //TEGRABL_SET_HIGHEST_MODULE(ret);
+             return;
+        }
+    }
+}
+
+static tegrabl_error_t write_byte(uint8_t byte)
+{
+    tegrabl_error_t ret = TEGRABL_NO_ERROR;
+    oled_gpio_t pin;
+    uint8_t bit;
+
+    pin = OLED_GPIO_CLK;
+    ret = pin_write(pin, SPI_CPOL != 0 ? GPIO_PIN_STATE_HIGH : GPIO_PIN_STATE_LOW);
+    if (ret != TEGRABL_NO_ERROR) {
+        goto fail;
+    }
+
+    pin = OLED_GPIO_CS;
+    ret = pin_write(pin, GPIO_PIN_STATE_LOW);
+    if (ret != TEGRABL_NO_ERROR) {
+        goto fail;
+    }
+
+    for (int bit_n = 7; bit_n > -1; bit_n--) {
+        bit = (byte >> bit_n) & 1u;
+
+        pin = OLED_GPIO_DIN;
+        ret = pin_write(pin, bit != 0u ? GPIO_PIN_STATE_HIGH : GPIO_PIN_STATE_LOW);
+        if (ret != TEGRABL_NO_ERROR) {
+            goto fail;
+        }
+
+        pin = OLED_GPIO_CLK;
+        ret = pin_write(pin, SPI_CPOL != 0 ? GPIO_PIN_STATE_LOW : GPIO_PIN_STATE_HIGH);
+        if (ret != TEGRABL_NO_ERROR) {
+            goto fail;
+        }
+        ret = pin_write(pin, SPI_CPOL != 0 ? GPIO_PIN_STATE_HIGH : GPIO_PIN_STATE_LOW);
+        if (ret != TEGRABL_NO_ERROR) {
+            goto fail;
+        }
+    }
+
+    pin = OLED_GPIO_CS;
+    ret = pin_write(pin, GPIO_PIN_STATE_HIGH);
+    if (ret != TEGRABL_NO_ERROR) {
+        goto fail;
+    }
+
+    return ret;
+
+fail:
+    pr_error("OLED: %s: Failed to write GPIO pin: %d err: %d\n", __func__, pin, ret);
+    //TEGRABL_SET_HIGHEST_MODULE(ret);
+    return ret;
+}
+
+static void logo_entry(const struct app_descriptor *app, void *args)
+{
+    // tegrabl_error_t ret = TEGRABL_NO_ERROR;
+    
+    for (;;) {
+        write_byte(0b01010011);
+        thread_sleep(10);
+    }
+}
+
+APP_START(logo_app)
+	.init = logo_init,
+	.entry = logo_entry,
+#if defined(CONFIG_ENABLE_DTB_OVERLAY)
+	.stack_size = 32768,
+	.flags = APP_FLAG_CUSTOM_STACK_SIZE,
+#endif
+APP_END
+
+
diff --git a/bootloader/partner/t18x/cboot/app/rules.mk b/bootloader/partner/t18x/cboot/app/rules.mk
index 7de33dd..3c974b8 100644
--- a/bootloader/partner/t18x/cboot/app/rules.mk
+++ b/bootloader/partner/t18x/cboot/app/rules.mk
@@ -3,6 +3,7 @@ LOCAL_DIR := $(GET_LOCAL_DIR)
 MODULE := $(LOCAL_DIR)
 
 MODULE_SRCS += \
-	$(LOCAL_DIR)/app.c
+	$(LOCAL_DIR)/app.c \
+	$(LOCAL_DIR)/logo.c
 
 include make/module.mk
