From 73d3401e493fea4877a4658a4504b831039a223b Mon Sep 17 00:00:00 2001
From: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Date: Thu, 20 Jul 2017 20:37:17 +0530
Subject: [PATCH] spi: tegra: Fix hardware timing programming

Setup and Hold time programming does not retain existing
values of other chip selects.
Also if cs is programmed through dt and is set to 0,
wrongly 0xF will be programmed

Fixed these errors.

Change-Id: I6fdb7c96f7e1d4d449dddc4b03dab5700e178277
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
---

diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index 9f84b622..93f4ca2 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -84,8 +84,8 @@
 #define SPI_RX_TAP_DELAY(x)			(((x) & 0x3F) << 0)
 
 #define SPI_CS_TIMING1				0x008
-#define SPI_SETUP_HOLD(setup, hold)		(((setup - 1) << 4) |	\
-						(hold - 1))
+#define SPI_SETUP_HOLD(setup, hold)		(((setup) << 4) |	\
+						(hold))
 #define SPI_CS_SETUP_HOLD(reg, cs, val)			\
 		((((val) & 0xFFu) << ((cs) * 8)) |	\
 		((reg) & ~(0xFFu << ((cs) * 8))))
@@ -875,7 +875,7 @@
 	struct tegra_spi_client_ctl_data *cdata = spi->controller_data;
 	u32 set_count;
 	u32 hold_count;
-	u32 spi_cs_timing;
+	u32 spi_cs_timing = tspi->spi_cs_timing;
 	u32 spi_cs_setup;
 
 	if (!cdata || tspi->prod_list)
@@ -902,7 +902,7 @@
 {
 	struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 	struct tegra_spi_client_ctl_data *cdata = spi->controller_data;
-	u32 spi_cs_timing2 = 0;
+	u32 spi_cs_timing2 = tspi->spi_cs_timing2;
 
 	if (!cdata || tspi->prod_list)
 		return;
@@ -1096,9 +1096,7 @@
 				tegra_spi_writel(tspi, command1, SPI_COMMAND1);
 
 		tspi->is_hw_based_cs = false;
-		if (cdata && cdata->is_hw_based_cs && is_single_xfer &&
-		    ((tspi->curr_dma_words * tspi->bytes_per_word) ==
-		     (t->len - tspi->cur_pos))) {
+		if (cdata && cdata->is_hw_based_cs && is_single_xfer) {
 			tegra_spi_set_timing1(spi);
 			tspi->is_hw_based_cs = true;
 		}
@@ -2002,6 +2000,8 @@
 	tspi->def_command1_reg |= SPI_CS_SEL(tspi->def_chip_select);
 	tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
 	tspi->command2_reg = tegra_spi_readl(tspi, SPI_COMMAND2);
+	tspi->spi_cs_timing = tegra_spi_readl(tspi, SPI_CS_TIMING1);
+	tspi->spi_cs_timing2 = tegra_spi_readl(tspi, SPI_CS_TIMING2);
 	tegra_spi_set_slcg(tspi);
 	pm_runtime_put(&pdev->dev);