/*
* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see .
*/
#include "tegra194-camera-rbpcv2-iraytek.dtsi"
#include "tegra194-fixed-regulator-p3509-0000-a00.dtsi"
#define MUX_RESET TEGRA194_AON_GPIO(CC, 2)
#define CAM0_PWDN TEGRA194_MAIN_GPIO(P, 4)
#define CAM1_PWDN TEGRA194_MAIN_GPIO(P, 5)
#define CAM_I2C_MUX TEGRA194_AON_GPIO(CC, 3)
#define CAMERA_I2C_MUX_BUS(x) (0x1E + x)
/ {
i2c@3160000{
tca9548_70: tca9548@70 {
compatible = "nxp,pca9548";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
vcc-supply = <&p3509_vdd_1v8_cvb>;
reset-gpios = <&tegra_aon_gpio MUX_RESET GPIO_ACTIVE_LOW>; /*reset-gpios ,reset两个属性都需要*/
reset = <&tegra_aon_gpio MUX_RESET GPIO_ACTIVE_LOW>;
skip_mux_detect;
force_bus_start = ;
/*todo:LT9211 init set*/
/* i2c@0 {
* reg = <0>;
* i2c-mux,deselect-on-exit;
* #address-cells = <1>;
* #size-cells = <0>;
*
* rbpcv2_iraytek_a@10 {
* clocks = <&bpmp_clks TEGRA194_CLK_EXTPERIPH1>,
* <&bpmp_clks TEGRA194_CLK_PLLP_OUT0>;
* clock-names = "extperiph1", "pllp_grtba";
* mclk = "extperiph1";
* clock-frequency = <24000000>;
* reset-gpios = <&tegra_main_gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
* };
*
* };
*/
};
};
cam_i2cmux{
compatible = "i2c-mux-gpio";
#address-cells = <1>;
#size-cells = <0>;
i2c-parent = <&cam_i2c>;
mux-gpios = <&tegra_aon_gpio CAM_I2C_MUX GPIO_ACTIVE_HIGH>;
i2c@0 {
reg = <0>; /*device/channel- i2c-bus register*/
#address-cells = <1>;
#size-cells = <0>;
rbpcv2_iraytek_a@29 {
/* reset-gpios = <&tegra_main_gpio CAM0_PWDN GPIO_ACTIVE_HIGH>; */
};
};
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
rbpcv2_iraytek_b@30 {
/* reset-gpios = <&tegra_main_gpio CAM1_PWDN GPIO_ACTIVE_HIGH>; */
};
};
i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
rbpcv2_iraytek_c@31 {
/* reset-gpios = <&tegra_main_gpio CAM0_PWDN GPIO_ACTIVE_HIGH>; */
};
};
i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
rbpcv2_iraytek_d@32 {
/* reset-gpios = <&tegra_main_gpio CAM0_PWDN GPIO_ACTIVE_HIGH>; */
};
};
i2c@4 {
reg = <4>;
#address-cells = <1>;
#size-cells = <0>;
rbpcv2_iraytek_e@33 {
/* reset-gpios = <&tegra_main_gpio CAM0_PWDN GPIO_ACTIVE_HIGH>; */
};
};
i2c@5 {
reg = <5>;
#address-cells = <1>;
#size-cells = <0>;
rbpcv2_iraytek_f@34 {
/* reset-gpios = <&tegra_main_gpio CAM0_PWDN GPIO_ACTIVE_HIGH>; */
};
};
};
gpio@2200000 {
camera-control-output-low {
gpio-hog;
output-low;
gpios = ;
label = "cam0-pwdn","cam1-pwdn";
};
};
};