Does sm__ops_path_tensor_src_fp16_dst_fp32_sparsity_off.sum report actual hardware executed tensor core FLOPs, or is it computed analytically from M×N

Developer Tools Nsight Compute
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I’m profiling a tensor-core GEMM kernel using :

ncu --metrics sm__ops_path_tensor_src_fp16_dst_fp32_sparsity_off.sum ./my_kernel

Across multiple runs with different M, N, K, the value returned by this metric exactly matches the analytical formula for FLOPs given the matrix dimensions (M×K times K×N). The match is exact, not approximate - down to the last digit, every time.

Is this metric genuinely derived from hardware performance-counter events, or does NCU compute it analytically from the known matrix dimensions in some cases?

The reason I’m asking: I’d naively expect a real instruction-level hardware counter to sometimes diverge from the pure analytical M×N×K formula

Is there documentation, or can someone from the Nsight Compute team confirm, how sm__ops_path_tensor_* metrics are actually computed under the hood?

Thanks in advance.

2

Moved to Nsight Compute

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In what cases would you expect it to diverge?