Hiding memory read latency

[alex.barnell]

Hi,

Section 5.1.1.3 of the CUDA Programming Manual (1.0) says in relation to device memory read latency:

Much of this global memory latency can be hidden by the thread scheduler if there are sufficient independent arithmetic instructions that can be issued while waiting for the global memory access to complete.

Does anyone know

• How much is “much”?

• How many memory access be in progress whilst other independent instructions are executing? More than one I presume!

• Does this also apply to memory writes?

Thanks,

Alex