I recommend testing under gtkterm. An example command line for 115200 8N1 to ttyTHS6 on a TX2:
# Use "sudo" if your user isn't a member of group "dialout".
gtkterm -b 8 -t 1 -s 115200 -p /dev/ttyTHS6
Minicom was designed to initialize modems using the AT command set. Gtkterm is simpler if you aren’t using a modem.
The result is same as the minicom!!!
ksv198
January 11, 2019, 9:24am
38
Hi ksv198:
I still get some strange info when doing loop testing
OPTIONS: I18n
Compiled on Feb 7 2016, 13:35:57.
Port /dev/ttyTHS6, 03:04:48
Press CTRL-A Z for help on special keys
f
error: line too long
command not found
]
command not found
] ]
error: line too long
command not found
] ]
error: line too long
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error: line too long
Hello!
I think you need disconnect uart7 from internal debugger.
See thread: Internal TX2 traffic on UART7 ? - Jetson TX2 - NVIDIA Developer Forums
You need decompile tegra186-a02-bpmp-quill-p3310-1000-c04-00-te770d-ucm2.dtb and change this:
serial {
port = <0xff>; port = <0x7>;
has_input;
};
then compile, run apply_binaries.sh and flash:
sudo ./flash.sh jetson-tx2 mmcblk0p1
Good luck!
1 Like
Hello JerryChang,
I used your setting of UART7 on my custom board. It didn’t work. There some error message will shown on console when booted. The kernel message as below:
[ 1.181133] OF: /serial@c290000: could not get #clock-cells for /cpus/l2-cache0
[ 1.188613] ERROR: could not get clock /serial@c290000:serial(0)
[ 1.194704] serial-tegra c290000.serial: Couldn’t get the clock
By the way, I used L4T 32.3.1.
hello williamho,
may I know what’s the modification you’d done, did you change the port properties as port = <0xff>;
?
Hello JerryChang,
Thanks for your reply. My modifications are:
Change the port properties as port = <0xff>; in {my_path}/Linux_for_Tegra/bootloader/t186ref/tegra186-a02-bpmp-quill-p3310-1000-c04-00-te770d-ucm2.dts (decompile the tegra186-a02-bpmp-quill-p3310-1000-c04-00-te770d-ucm2.dtb)
Add the setting as below in {my_path}/hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-common.dtsi
serial@c290000 {
compatible = "nvidia,tegra186-hsuart";
#stream-id-cells = <0x1>;
reg = <0x0 0xc290000 0x0 0x40>;
reg-shift = <0x2>;
interrupts = <0x0 0x76 0x4>;
nvidia,memory-clients = <0xe>;
dmas = <0x19 0x2 0x19 0x2>;
dma-names = "rx", "tx";
clocks = <0xd 0xd8 0xd 0x10d>;
clock-names = "serial", "parent";
resets = <0xd 0x70>;
reset-names = "serial";
status = "okay";
nvidia,adjust-baud-rates = <0x1c200 0x1c200 0x64>;
linux,phandle = <0x89>;
phandle = <0x89>;
};
Hi JerryChang
Do you have any suggestion regarding how to set the UART 7 alive? thx a lot.
hello williamho,
could you please share the details boot logs for reference,
thanks
Hi JerryChang,
This is my detail boot logs.
thanks
boot.log (21.8 KB)
Can you try with below serial node with exact values and add it to the hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-common.dtsi ?
serial@c290000 {
compatible = "nvidia,tegra186-hsuart";
iommus = <0x11 0x20>;
reg = <0x0 0xc290000 0x0 0x40>;
reg-shift = <0x2>;
interrupts = <0x0 0x76 0x4>;
nvidia,memory-clients = <0xe>;
dmas = <0x25 0x2 0x25 0x2>;
dma-names = "rx", "tx";
clocks = <0x10 0xd8 0x10 0x10d>;
clock-names = "serial", "parent";
resets = <0x10 0x70>;
reset-names = "serial";
status = "okay";
nvidia,tolerance-low-range = <0x0>;
nvidia,tolerance-high-range = <0x4>;
nvidia,adjust-baud-rates = <0x1c200 0x1c200 0x64>;
linux,phandle = <0x194>;
phandle = <0x194>;
};
And check it with BPMP dts change as mentioned in previous comments.
Hi JerryChang,
The UART7 can work fine after used the latest setting you provided. Thanks again.
hello williamho,
glad to know it works,
to help other rel-32 forum developer to find the solutions easier, could you please help to point-out which comment shows the instruction, or, you might share your steps in detail to make UART-7 works.
thanks
Hi JerryChang,
OK, no problem. This is my H/W & L4T information and the steps of enabling UART7 as below:
[Information]
H/W: TX2 SOM board (P3310) + custom CA board
L4T: 32.3.1
UART7: connected with GPS
[Steps]
1.Modify the BPMP dts
a.cd /{$path}/nvidia_sdk/JetPack_4.3_Linux_P3310/Linux_for_Tegra/bootloader/t186ref
b.dtc -I dtb -O dts tegra186-a02-bpmp-quill-p3310-1000-c04-00-te770d-ucm2.dtb > tegra186-a02-bpmp-quill-p3310-1000-c04-00-te770d-ucm2.dts
c.Modify area as below:
serial {
port = <0xff>; #port = <0x7>;
has_input;
};
d.dtc -I dts -O dtb tegra186-a02-bpmp-quill-p3310-1000-c04-00-te770d-ucm2.dts > tegra186-a02-bpmp-quill-p3310-1000-c04-00-te770d-ucm2.dtb
2.Modify the dts
a.cd /${path}/kernel/hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms
b.added area as below in tegra186-quill-common.dtsi
serial@c290000 {
compatible = "nvidia,tegra186-hsuart";
iommus = <0x11 0x20>;
reg = <0x0 0xc290000 0x0 0x40>;
reg-shift = <0x2>;
interrupts = <0x0 0x76 0x4>;
nvidia,memory-clients = <0xe>;
dmas = <0x25 0x2 0x25 0x2>;
dma-names = "rx", "tx";
clocks = <0x10 0xd8 0x10 0x10d>;
clock-names = "serial", "parent";
resets = <0x10 0x70>;
reset-names = "serial";
status = "okay";
nvidia,tolerance-low-range = <0x0>;
nvidia,tolerance-high-range = <0x4>;
nvidia,adjust-baud-rates = <0x1c200 0x1c200 0x64>;
linux,phandle = <0x194>;
phandle = <0x194>;
};
3.Compile the dts (ready your compile environment)
make ARCH=arm64 O=$TEGRA_KERNEL_OUT CROSS_COMPILE=${CROSS_COMPILE} -j4 dtbs
4.Flash dtb
sudo ./flash.sh -r -k kernel-dtb jetson-tx2 mmcblk0p1
1 Like
did I miss something or did you forget to flash the bpmp device tree in this writeup?
Terry
does flashing the kernel-dtb also flash the bpmp dtb?
Terry
Flash the bpmp DTB partition:
sudo ./flash.sh -r -k bpmp-fw-dtb jetson-tx2 mmcblk0p1
Question for understanding:
The BPMP-DTB change
serial {
port = <0xff>; #port = <0x7>;
has_input;
};
prevents the BPMP from sending stuff to UART7 port, right?