All right. So, is there a way to resolve the payload CRC error?
I would suggest consult with the sensor or serdes chip vendor.
Thanks
Hi, ShaneCCC
I contacted the vendor and asked, and they responded that they had given me the wrong resolution. After correcting the resolution, many of the previous errors disappeared. Do you know how to resolve this error?
here is my trace log
# tracer: nop
#
# entries-in-buffer/entries-written: 26/26 #P:8
#
# _-----=> irqs-off
# / _----=> need-resched
# | / _---=> hardirq/softirq
# || / _--=> preempt-depth
# ||| / delay
# TASK-PID CPU# |||| TIMESTAMP FUNCTION
# | | | |||| | |
kworker/0:5-161 [000] .... 79.355137: rtcpu_string: tstamp:3638856696 id:0x04010000 str:"VM0 deactivating."
v4l2-ctl-2513 [005] .... 80.460327: tegra_channel_open: vi-output, max96724 7-0027
v4l2-ctl-2513 [005] .... 80.468727: tegra_channel_set_power: max96724 7-0027 : 0x1
v4l2-ctl-2513 [005] .... 80.468777: tegra_channel_set_power: 13e40000.host1x:nvcsi@15a00000- : 0x1
v4l2-ctl-2513 [005] .... 80.468783: csi_s_power: enable : 0x1
v4l2-ctl-2513 [000] .... 80.470327: tegra_channel_capture_setup: vnc_id 0 W 1920 H 1080 fmt c4
kworker/0:5-161 [000] .... 80.479066: rtcpu_string: tstamp:3674911198 id:0x04010000 str:"VM0 activating."
v4l2-ctl-2513 [002] .... 80.480943: tegra_channel_set_stream: enable : 0x1
v4l2-ctl-2513 [002] .... 80.497966: tegra_channel_set_stream: 13e40000.host1x:nvcsi@15a00000- : 0x1
v4l2-ctl-2513 [002] .... 80.497969: csi_s_stream: enable : 0x1
v4l2-ctl-2513 [002] .... 80.498283: tegra_channel_set_stream: max96724 7-0027 : 0x1
kworker/0:5-161 [000] .... 80.535062: rtcpu_vinotify_event: tstamp:3675631951 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:117604586272 data:0x359e300010000000
kworker/0:5-161 [000] .... 80.535063: rtcpu_vinotify_event: tstamp:3675632120 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:117604592832 data:0x0000000031000001
kworker/0:5-161 [000] .... 80.535064: rtcpu_vinotify_event: tstamp:3675632311 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:117604659616 data:0x359e2d0010000000
kworker/0:5-161 [000] .... 80.535064: rtcpu_vinotify_event: tstamp:3675632470 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:117604666272 data:0x0000000031000002
kworker/0:5-161 [000] .... 80.535066: rtcpu_nvcsi_intr: tstamp:3676251264 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x0e000000
v4l2-ctl-2513 [002] .... 81.048581: tegra_channel_close: vi-output, max96724 7-0027
vi-output, max9-2515 [007] .... 85.778935: tegra_channel_capture_setup: vnc_id 0 W 1920 H 1080 fmt c4
v4l2-ctl-2513 [002] .... 85.788597: tegra_channel_set_stream: enable : 0x0
v4l2-ctl-2513 [002] .... 85.788600: tegra_channel_set_stream: max96724 7-0027 : 0x0
v4l2-ctl-2513 [002] .... 85.788818: tegra_channel_set_stream: 13e40000.host1x:nvcsi@15a00000- : 0x0
v4l2-ctl-2513 [002] .... 85.788820: csi_s_stream: enable : 0x0
v4l2-ctl-2513 [002] .... 85.802161: tegra_channel_set_power: max96724 7-0027 : 0x0
v4l2-ctl-2513 [002] .... 85.805812: tegra_channel_set_power: 13e40000.host1x:nvcsi@15a00000- : 0x0
v4l2-ctl-2513 [002] .... 85.805816: csi_s_power: enable : 0x0
kworker/0:5-161 [000] .... 90.866856: rtcpu_string: tstamp:3998343896 id:0x04010000 str:"VM0 deactivating."
And, it’s my devicetree
max96724@3 {
compatible = "nvidia,max96724";
status = "okay";
devnode = "video2";
reg = <0x03>;
physical_w = "15.0";
physical_h = "12.5";
reset-gpios = <0x04 0x3b 0x00>;
sensor_model = "max96724b";
post_crop_frame_drop = [30 00];
use_decibel_gain = "false";
use_sensor_mode_id = "false";
clocks = <0x02 0x24 0x02 0x24>;
clock-names = "extperiph1\0pllp_grtba";
mclk = "extperiph1";
mode0 {
mclk_khz = "25000";
num_lanes = [32 00];
tegra_sinterface = "serial_c";
vc_id = [33 00];
phy_mode = "DPHY";
discontinuous_clk = "no";
dpcm_enable = "false";
//cil_settletime = [68 00];
cil_settletime = [40 00];
dynamic_pixel_bit_depth = "12";
csi_pixel_bit_depth = "16";
mode_type = "yuv";
pixel_phase = "uyvy";
lane_polarity = [30 00];
active_w = "1920";
active_h = "1080";
readout_orientation = [30 00];
line_length = "3448";
inherent_gain = [31 00];
pix_clk_hz = "8000000";
serdes_pix_clk_hz = "160000000";
gain_factor = "10";
min_gain_val = [30 00];
max_gain_val = "300";
step_gain_val = [33 00];
default_gain = [30 00];
min_hdr_ratio = [31 00];
max_hdr_ratio = [31 00];
framerate_factor = "1000000";
min_framerate = "30000000";
max_framerate = "30000000";
step_framerate = [31 00];
default_framerate = "30000000";
exposure_factor = "1000000";
min_exp_time = "59";
max_exp_time = "33333";
step_exp_time = [31 00];
default_exp_time = "33333";
embedded_metadata_height = [30 00];
};
ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
reg = <0x00>;
endpoint {
vc-id = <0x00>;
port-index = <0x02>;
bus-width = <0x02>;
remote-endpoint = <0x11>;
phandle = <0x2b6>;
};
};
};
};
tegra-capture-vi {
compatible = "nvidia,tegra-camrtc-capture-vi";
nvidia,vi-devices = <0x269 0x26b>;
nvidia,vi-mapping-size = <0x06>;
nvidia,vi-mapping = <0x00 0x00 0x01 0x00 0x02 0x01 0x03 0x01 0x04 0x00 0x05 0x01>;
nvidia,vi-mapping-names = "csi-stream-id\0vi-unit-id";
nvidia,vi-max-channels = <0x48>;
num-channels = <0x03>;
phandle = <0x49d>;
ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
reg = <0x00>;
status = "okay";
phandle = <0x49e>;
endpoint {
vc-id = <0x00>;
port-index = <0x00>;
bus-width = <0x02>;
remote-endpoint = <0x26c>;
status = "okay";
phandle = <0x2b3>;
};
};
port@1 {
reg = <0x01>;
status = "okay";
phandle = <0x49f>;
endpoint {
vc-id = <0x00>;
port-index = <0x01>;
bus-width = <0x02>;
remote-endpoint = <0x26d>;
status = "okay";
phandle = <0x2b5>;
};
};
port@2 {
reg = <0x02>;
status = "okay";
phandle = <0x4a0>;
endpoint {
vc-id = <0x00>;
port-index = <0x02>;
bus-width = <0x02>;
remote-endpoint = <0x26e>;
status = "okay";
phandle = <0x2b7>;
};
};
};
nvcsi@15a00000 {
compatible = "nvidia,tegra194-nvcsi";
clocks = <0x02 0x51>;
clock-names = "nvcsi";
status = "okay";
num-channels = <0x03>;
#address-cells = <0x01>;
#size-cells = <0x00>;
num-tpg-channels = <0x24>;
phandle = <0x4c6>;
channel@0 {
reg = <0x00>;
status = "okay";
phandle = <0x4c7>;
ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
reg = <0x00>;
status = "okay";
phandle = <0x4c8>;
endpoint@0 {
port-index = <0x00>;
bus-width = <0x02>;
remote-endpoint = <0x2b2>;
status = "okay";
phandle = <0x0a>;
};
};
port@1 {
reg = <0x01>;
status = "okay";
phandle = <0x4c9>;
endpoint@1 {
remote-endpoint = <0x2b3>;
status = "okay";
phandle = <0x26c>;
};
};
};
};
channel@1 {
reg = <0x01>;
status = "okay";
phandle = <0x4ca>;
ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
reg = <0x00>;
status = "okay";
phandle = <0x4cb>;
endpoint@2 {
port-index = <0x01>;
bus-width = <0x02>;
remote-endpoint = <0x2b4>;
status = "okay";
phandle = <0x0b>;
};
};
port@1 {
reg = <0x01>;
status = "okay";
phandle = <0x4cc>;
endpoint@3 {
remote-endpoint = <0x2b5>;
status = "okay";
phandle = <0x26d>;
};
};
};
};
channel@2 {
reg = <0x02>;
status = "okay";
phandle = <0x4cd>;
ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
reg = <0x00>;
status = "okay";
phandle = <0x4ce>;
endpoint@4 {
port-index = <0x02>;
bus-width = <0x02>;
remote-endpoint = <0x2b6>;
status = "okay";
phandle = <0x11>;
};
};
port@1 {
reg = <0x01>;
status = "okay";
phandle = <0x4cf>;
endpoint@5 {
remote-endpoint = <0x2b7>;
status = "okay";
phandle = <0x26e>;
};
};
};
};
tegra-camera-platform {
compatible = "nvidia, tegra-camera-platform";
num_csi_lanes = <0x02>;
max_lane_speed = <0x16e360>;
min_bits_per_pixel = <0x0a>;
vi_peak_byte_per_pixel = <0x02>;
vi_bw_margin_pct = <0x19>;
isp_peak_byte_per_pixel = <0x05>;
isp_bw_margin_pct = <0x19>;
max_pixel_rate = <0x27100>;
tpg_max_iso = <0x3bc400>;
phandle = <0x53b>;
modules {
module0 {
badge = "max96724_bottom";
position = "bottom";
orientation = [31 00];
status = "okay";
phandle = <0x53c>;
drivernode0 {
pcl_id = "v4l2_sensor";
devname = "max96724 70-0001";
proc-device-tree = "/proc/device-tree/i2c@c250000/max96724@1";
status = "okay";
phandle = <0x53d>;
};
drivernode1 {
pcl_id = "v4l2_lens";
proc-device-tree = "/proc/device-tree/e3333_lens_ov5693@P5V27C/";
status = "disabled";
phandle = <0x53e>;
};
};
module1 {
badge = "max96724_top";
position = "top";
orientation = [31 00];
status = "okay";
phandle = <0x53f>;
drivernode0 {
pcl_id = "v4l2_sensor";
devname = "max96724 70-0002";
proc-device-tree = "/proc/device-tree/i2c@c250000/max96724@2";
status = "okay";
phandle = <0x540>;
};
drivernode1 {
pcl_id = "v4l2_lens";
proc-device-tree = "/proc/device-tree/e3333_lens_ov5693@P5V27C/";
status = "disabled";
phandle = <0x541>;
};
};
module2 {
badge = "max96724_left";
position = "left";
orientation = [31 00];
status = "okay";
phandle = <0x542>;
drivernode0 {
pcl_id = "v4l2_sensor";
devname = "max96724 70-0003";
proc-device-tree = "/proc/device-tree/i2c@c250000/max96724@3";
status = "okay";
phandle = <0x543>;
};
drivernode1 {
pcl_id = "v4l2_lens";
proc-device-tree = "/proc/device-tree/e3333_lens_ov5693@P5V27C/";
status = "disabled";
phandle = <0x544>;
};
};
Thanks
Looks like didn’t receive any validate data from the sensor.
VIFALC_TDSTATE Is the error part of the validated data?
If it is true, can you provide a way to solve it?
This message for the RCE firmware capture request status doesn’t means any error.
There was a way to ignore the CRC, so I referenced it, modified it, and printed the image. But a staircase phenomenon is occurring. How can I solve this?
The command I wrote is as follows.
gst-launch-1.0 nvv4l2camerasrc device=/dev/video2 ! 'video/x-raw(memory:NVMM),foo
rmat=UYVY,width=2560,height=1984,framerate=30/1' ! nvvidconv ! 'video/x-raw(memoo
ry:NVMM),format=GRAY8' ! nvvidconv ! 'video/x-raw(memory:NVMM),format=I420' ! nvv
vidconv ! xvimagesink
Please dump to file by v4l2-ctl --stream-to to check by 7yuv
Thanks
Even if you check it with yuv viewer, the output is the same.
Is this related to the current image sensor outputting rgb-ir raw 12bit?
Hi, ShaneCCC
I have additional questions.
There is a pixelformat written in the pixel_phase item in the device tree. Is it created by passing through the internal ISP based on that value?
Or is the image that comes out after ISP confirmed?
What’s the YUV output format? It’s uyvy 16bit in your device tree.
My devicetree has uyvy 16bit.
The yuvview results re-checked in 16bit are below.
If uyvy 16bit is set in devicetree, is it correct for the internal ISP to convert the raw image to uyvy?
There’s no internal ISP involve when you use v4l2 capture.
You need to make sure the sensor output format to define the pixel_phase and bit depth.
In my devicetree, pixel phase and bit_depth are already set.
I don’t know why it shows up like that in yuvview. Do you know anything? Or even a method of action??
dynamic_pixel_bit_depth = “12”;
csi_pixel_bit_depth = “16”;
mode_type = “yuv”;
pixel_phase = “uyvy”;
Thanks
There’s no problem if the sensor output format is YUV422-8bit for this device tree configuration. That’s why need to confirm the sensor output format.
The sensor output format is RGB-IR raw 12bit.
Can VB1940, which has an ISP inside output YUV format?
If not you need to modify the device tree to any of bayer 12 raw format then debayer by software debayer for your case.
Are you saying to implement and apply debayer code in python or C++ without using an ISP?
Yes, if the output data is 12bit RAW data.
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