Jetson TX1 Cache Policy/ System Profiler info

I’m looking at the L1/L2 cache misses and trying to extrapolate that to effective main memory access. What is the write policy of the cache? Is main memory accessed on a write cache hit(write-through) or only when the cache experiences a miss? Any guidance or references would be helpful. Thanks.

You’ll probably find out part of the answer via the ARM Cortex A57 TRM. Go here (may need a free login):
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.subset.swdev.abi/index.html

On the left go to the “Cortex-A series processors”, then choose “Cortex-A57”. So far as how cache works within the CPU this may provide some hints or answers…I don’t know to what extent the Linux kernel deals with hits versus misses and the memory controller.

Thank you for the reference I was able to determine that it uses a write-back write-allocate. Thanks again.