I wonder the association between logical and physical memory organization in CUDA enabled cards. I understand registers and shared memory are on-chip areas and local memory, global memory, constant memory and texture memory are on-device memory areas. I guess latter happens in a single memory structure (what we call 512MB memory?). So following are my questions:
registers are register in the sense of digital electronics or it is an high-speed, probably multi-port on-chip memory sharing the same resources with shared memory ? If so, there is no access speed difference between them ?
local memory, global memory, constant memory and texture memory is inside the memory chips of device ? so they share the same resource ? If so, why constant and texture memory is read-only ? If so, are they dynamically partitioned (before runtime or during runtime) or have fixed amounts e.g. 1/2 is global memory, 1/2 is texture memory etc.