That’s a lot of questions External Media I’ll just try to answer two…
On G80 to GT200 architectures, 32-bit GDDR3 RAM chips are grouped in pairs, and every transaction is routed to a pair of chips put in parallel. This is why bus widths of NVidia GPUs are all 64-bit multiples.
Then, each GDDR3 chip only accept burst accesses of 4 consecutive words (see http://en.wikipedia.org/wiki/GDDR3). This is what allows them to reach high frequencies. GDDR-5 doubles the burst length again, so the trend is toward still larger transactions.
As a consequence, the minimal transaction size for the DRAM is 32 bytes. (This doesn’t imply that it is the minimal transaction size for the on-chip interconnect, which may be smaller, nor the minimal size for the memory controller, which may be larger…)
BTW, the size of a texture cache line is 256 bytes, so memory controllers are likely optimized for this granularity. (this is reflected in benchmarks accessing coalesced memory)
All DRAM technologies are based on the same principles, so yes. Each memory channel is 64-bit wide as on NVidia GPUs, and the typical burst length is 4, so the minimal transaction size is also 32 bytes.