Occasionally `14160000.pcie: Phy link never came up`

[WayneWWW]

Could you go to kernel/nvidia/drivers/pci/dwc/pcie-tegra.c and directly hardcoded the init_speed variable to 1 and see if that works?

[BenSung]

I find that CONFIG_ARCH_TEGRA_19x_SOC is not enabled and it cannot be enabled through menuconfig.

It seems that we use kernel-5.10/drivers/pci/controller/pci-tegra.c instead of kernel/nvidia/drivers/pci/dwc/pcie-tegra.c

[BenSung]

Hi WayneWWW! If the above is failed to work. I wonder that how to use setpci command to operate registers and upgrade the pcie from gen1 to gen3.

[kayccc]

Is this still an issue to support? Any result can be shared?

[BenSung]

Sorry for late reply.

We’ve tried writing some testing code. With rebooting thousands time, the problem not shows up again. But I have no time to clean up the code and share the changes here till middle of the May. Here is what I’ve found: The start of the problem is at tegra_pcie_dw_host_init at drivers/pci/controller/dwc/pcie-tegra194.c. In this function there is tegra_pcie_prepare_host, and it will finally call the dw_pcie_link_set_max_speed which is located at drivers/pci/controller/dwc/pcie-designware.c. This function set the link speed to be equal to link capacity, which does not meet the requirement of the AQC113C controller.

What I’ve done is by handle the 14160000.pcie separately:

1. force the link speed to be gen-1 in the dw_pcie_link_set_max_speed, while keeping the link capacity to be the origin value.
2. change the link speed to be gen-3 after tegra_pcie_prepare_host in tegra_pcie_dw_host_init. The "change link speed“ function is modified from apply_speed_change which is in the same file.

[BenSung]

Here is my rough patch for anyone met the same problem.

To skip a lot useless retries, please add the max-link-speed = <0x3>; in pcie@14160000 node.

0001-pcie-fixed-14160000-AQC113C-failed-to-link-up.patch.txt (10.5 KB)