hello suengpyo.shin,
it’s might due to you’re calling 3 gst pipelines with v4l2src plugins, as you’re using the same sensor driver, it’s 1st start to enable video0, 2nd for video1 and 3rd for launching video2.
that’s an error has detected in the PHY partition, some lanes detected sync words while other lanes.
yes, your device tree settings, imx390_a@1b, which connected to CSI-1 it looks correct.
Hello Jerry Chaing
My deser is max96712 which support D-PHY v1.2.
I’m suspecting D-PHY version because Orin NX support D-PHY v2.1 as the datasheet.
could you confirm compatibility issue is no problem?
Or let me know how to change D-PHY version setting?
The configuration of our system is as shown in the attached diagram.
CAM_1 and CAM_2 are connected to CSI0,
and CAM_3 is connected to CSI1.
According to the NVIDIA documentation, “lane_polarity must be 0x6 for sensors attached to CSI0/1 port, since CSI0 D1 and CSI1 D0 has P/N swizzled, in Orin NX 16GB, Orin NX 8GB, Orin Nano 8GB and Orin Nano 4GB modules. Set it by 0x0 for other cases.”
We have set the lane_polarity for CAM_1, CAM_2, and CAM_3 to 0x6 accordingly.
Could you please confirm if this value is correct?
Should we set the lane_polarity to 0x2 for CAM_1 and CAM_2, and to 0x1 for CAM_3?
hello suengpyo.shin,
it’s backward compatible with your DPHY v1.2
it seems this is topic filed to AGX Orin category, let me double check the Orin platform you’re now using.
you don’t have to configure lane polarity if you’re working with AGX Orin.
anyways,
it’s only CSI0 D1 and CSI1 D0 P/N always been swizzled for P/N.
please use device tree property, lane_polarity to configure a polarity swap on any lane.
you may see-also reference driver for lane polarity configuration.
for instance,
$public_sources/kernel_src/hardware/nvidia/platform/t23x/p3768/kernel-dts/cvb/tegra234-camera-rbpcv2-imx219.dtsi
* lane_polarity
* Based on the camera connector pin.
* CSIx_D0 | CSIx_D1 | CSI(X+1)_D0 | CSI(X+1)CSIx_D1
* LSB | BIT1 | BIT2 | MSB
* if there is a polarity swap on any lane, the bit corrsponding
* to the lane should be set
* e.g. polarity swap on CSIx_D0 only -> lane_polarity = "1"; 0001
* e.g. polarity swap on CSIx_D1 and CSI(X+1)_D0 -> lane_polarity = "6"; 0110
Hello Jerry Chang
I set settle_time = 0 (auto) then I can capture frame all times.
I have other question.
I have two type of camera.
First one is porting complete as UYUV cam.
Second one is still porting.
I ported cam as GRAY8 becuase Serdes’s DT is 2A(raw8).
v4l2src was recognized as gray8.
But I want this to be recognized as UYVY format.
Is there no way?
II simply set dts to UYVY, the screen do not not play.
I created a GStreamer plugin that converts the format, but buffer copy occurs.
I am attaching the dts file that I set up
main modification point is below
======================before=================
csi_pixel_bit_depth = “8”;
mode_type = “GREY”;
pixel_phase = “Y8”;
active_w = “3840”;
active_h = “1024”;
======================after=====================
csi_pixel_bit_depth = “8”;
mode_type = “yuv”;
pixel_phase = “uyvy”;
active_w = “1920”;
tegra234-p3737-camera-imx390-overlay.dts.txt (47.5 KB)
active_h = “1024”;
hello mrwiz,
may I know what’s the failure reported with UYVY format?
BTW, please also examine pixel clock settings, you must using correct settings to bringup the camera sensor.
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