Hi, where does the ECC work in Xavier, L1 cache or L2 cache of the GPU or CPU cache.
What level of memory do CPU and GPU share (do they share cache L2)?
Is there a way to turn ON/OFF ECC functionality? How can I see if ECC is working or not? Do I need to check kernel log to see if ECC has corrected any bit errors?
You can check the kernel log to check the ram ecc is enable or not.
Could you tell for what use case need to turn on/off the ECC?
In CPU ECC is enabled at L2 Cache using the BCT property
BCT/tegra186-mb1-bct-misc-si-l4t.cfg:66:mb2_params.feature_fields.disable_cpu_l2ecc = 0;
You can disable CPU L2ECC by setting 1 to this flag.
Also the correction logic is in HW and is SW agnostic.
Will get back regarding GPU
GPU ECC is not enabled.
Customer can enable it by fusing thr right fuse. But the handing of 2bit error is not there in present software
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