Questions on RTX5090 Integer throughput

[wonseok.choi1]

Hello, I’m working on accelerating CUDA kernels and have a question regarding the integer performance of the RTX 5090.

According to the white paper, the RTX 5090 should deliver 104.8 TOPS for INT32 computations. However, my calculation suggests only about 52.4 TOPS:

2407 MHz (Boost Clock) 
× 2 ops/inst (IMAD) 
× 64 inst/cycle/SM 
× 170 SMs 
= 52.4 TOPS

I took the “64 inst/cycle/SM” value from the Throughput of Native Arithmetic Instructions section in the CUDA Programming Guide.

To verify, I ran a benchmark kernel repeatedly executing IMAD instructions, and the measured performance also matches ~52.4 TOPS.

So my questions are:

1. How can the advertised 104.8 TOPS be achieved?

2. Is the number in the white paper possibly reported incorrectly, or is there some additional factor (dual issue, tensor cores, etc.) contributing to this figure?

Thank you in advance for your clarification

[striker159]

There is a lengthy discussion about blackwell integer performance here:

Blackwell Integer

Anyone using Cuda for primarily integer/logic work might be interested to see that all cores in an SM are now INT32 capable, first time since Pascal. Will have to see if any compromise has been made to fit them in. "With the rise in the use of AI and integer use for such workloads, Nvidia has made all of the shader cores in Blackwell fully FP32/INT32 compatible. "

[wonseok.choi1]

Thank you for answering. I’ll check it out!

[wonseok.choi1]

Thanks for the link—after reading the thread, I now understand that on Blackwell the IADD throughput doubled, while IMAD didn’t, and that current compilers often emit IADD3 (which isn’t doubled). However, even with that in mind, my theoretical peak still doesn’t reconcile with 104.8:

• Using the Programming Guide table value 64 inst/cycle/SM (for IMAD) and my IMAD microbenchmark, I get:

2.407 GHz × 170 SM × 64 inst/cycle/SM × 2 ops/IMAD = 52.4 “TOPS”

• If I switch to IADD and assume 2× instruction throughput but 1 op per instruction, I still get the same effective op rate:

2.407 GHz × 170 SM × (2 × 64) inst/cycle/SM × 1 op/IADD = 52.4 “TOPS”

So purely “IADD doubled” doesn’t lift the theoretical ops/sec above ~52.4.

I also considered that IMAD uses the FMA-heavy pipe while IADD uses ALUs, so an ideal IMAD+IADD mix might sustain more total work by occupying both pipes. But that style of concurrent utilization existed on prior architectures as well, so I don’t see how that alone explains 104.8 either.

Here are my questions:

1. How are “ops” counted for INT32 in that number? (IMAD = 2 ops, IADD = 1 op; is IADD3 counted as 2 ops?)

2. Does 104.8 assume an ideal instruction mix (e.g., perfectly scheduled IMAD + IADD across separate pipes), or is it mirrored from the FP32 FMA peak formula?

A concrete formula (the exact terms multiplied to reach 104.8) would resolve the ambiguity. Thanks!