Requesting clarification for Shared Memory Bank Conflicts and Shared memory access?

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Robert will probably be along with a more complete reply, but here are a couple of things.

This needs amending to:
bank conflicts occur when multiple threads in a given warp access different address location with in the same bank.”

Quoting from the "Best Practices Guide":

“On devices of compute capability 5.x or newer, each bank has a bandwidth of 32 bits every clock cycle, and successive 32-bit words are assigned to successive banks.”

So with two 16 bit elements packed into one 32bit bank and one element accessed from successive threads causes no conflict.