Reuse cache

Accelerated Computing CUDA CUDA Programming and Performance
1

@Greg

I wonder if you’d be able to comment. The following snippet of SASS is used repeatedly and in no case does the first IDP4A instruction set the reuse cache flag for R13 or R7 and I wondered why? Arch is SM6.1.

IDP.4A.U8.U8 R17, R13, c[0x2][0x8], R7 ;
{IDP.4A.U8.U8 R18, R13.reuse, c[0x2][0xc], R7.reuse ;
LDS.U.U16 R17, [R17+0x2]}
{IDP.4A.U8.U8 R19, R13.reuse, c[0x2][0x10], R7.reuse ;
LDS.U.U16 R18, [R18+0x2]}
{IDP.4A.U8.U8 R20, R13, c[0x2][0x14], R7 ;
LDS.U.U16 R19, [R19+0x2]}
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Without more context my expectation would be that the first IDP would have R13.reuse and R7.reuse.

The NVCC or PTX team would need to answer. In order to do this you would need to file a bug against the compiler/ptx with full reproducible. Unless you suspect a major performance loss (which is highly unlikely) then I give it a very low priority for getting reviewed.

3

Thanks Greg, I agree, (major performance loss (which is highly unlikely)), I was just curious.