shared memory banks

Accelerated Computing CUDA CUDA Programming and Performance
1

It’s not clear to me what the size of a shared memory bank is. The programming guide says

Does this mean that a shared memory bank is 32 bits? Don’t think so…

Also what’s an example of some code that will cause memory bank conflicts?

2

Ok I did some further reading and I think I see how it works now. There are 16 memory banks of 1KB each per multiprocessor. So when you access something in shared memory using, for example, a stride of 4 bytes eg:

Assume s is pointing to a uint32_t array.

In thread0:

s[0]

In thread1:

s[1]

In thread 2:

s[2]

etc…

Then those individual accesses are mapped to the physical memory banks 0-15 on the hardware. So, for example the absolute address of s[1] would be, roughly speaking, at the base_address_of_the_banks + sizeof(bank) + 4. Now because a bank is 1KB in size, then s[1] points to the 4th byte in the 1st memory bank. Does that sound right?

3

No, it points to the 1st byte of the 2nd memory bank.

4

Sorry, my initial post may not have been clear. Firstly s is a pointer to a uint32_t array so s[1] will point to the 4th byte of that bank. Also I was counting memory banks from index 0 - 15, so I meant the bank at index 1 which is the 2nd bank as you point out.

5

But why 4th byte?

6

Isn’t that how the array operator works? A uint32_t is 4 bytes.

Eg:

uint32_t* p = …

p[0] ----> 0th byte

           1st byte

           2nd byte

           3rd byte

p[1] ----> 4th byte

           5th 

           6th

           7th

p[2]------>8th

        etc....

if p were a pointer to a uint8_t then it would look like this

p[0] ----> 0th byte

p[1]----->1st byte

p[2]----->2nd byte

7

s[0] points to byte 0 of bank 0
s[1] points to byte 0 of bank 1
s[2] points to byte 0 of bank 2

s[16] points to byte 4 of bank 0
s[17] points to byte 4 of bank 1
…

8

Yes, my mistake.