Size of a structure on device

Accelerated Computing CUDA CUDA Programming and Performance
1

I have been getting a different value for the size of a structure on the host and the device. As I load an array of my structure into shared memory and calculate the size of shared memory on the host this has previosuly caused me probems (at least Ive spent a while finding the problem). My struct is declared as

struct  message

{

	int2 _position;	

	int state;

	int val1;

	int val2;

};

On the host the size of this is 20bytes (as expected), on the device the sizeof function returns 24bytes. I get round this by enforcing alignment i.e. align(16) to give a 32byte size which has the added benefit of avoiding bank conflicts but I just wondered where the extra 4 bytes is coming from.

Im sure this must be covered in some documentation somewhere. Can anyone point me in the right direction?

2

I previously misinterpreted bank conflicts. If I use a structure alignment size of 16 (with a resulting 32byte struct size) as I in my last post, then threads within a half warp accessing variables from consecutive structs in shared memory have a stride of 8 and an 8 way bank conflict.

I could get around this by not using structure alignment and ensuring there are is an odd numbered stride. In the case of my struct the size should be 20bytes on the GPU so the stride would be 5 and there would be no conflicts. This unfortunately is not the case however as sizeof(message) returns a size of 24bytes which gives a stride of 6 and a 2 way bank conflict.

Can anyone explain???