TX1 and MEMES mics using PDM

Autonomous Machines Jetson & Embedded Systems Jetson TX1
#1

In the datasheet you mentioned that the TX1 has 6X PDM reciever
but i cannot find any more information about it
I am trying to use MEMES mics, so PDM the way to go…

so, how to connect (which PINS):

  1. PDM input lines
  2. TX1 PDM output clock ?

and is there and information, datasheets, instructions, drivers or software i can use ?

thank you

#2

Hello!

The PDM receivers are the DMIC device on the TX1. There are 3 instances on the DMIC and each DMIC can support 1 or 2 channels/devices.

To answer your questions …

  1. DMICx_CLK and DMICx_DATA where x is 1, 2 or 3.
  2. DMICx_CLK where x is 1, 2 or 3.

Note that DMIC3 is available on the 40-pin header (J21).

Please note that some others have also used a mems mic with the I2S interface see …

https://devtalk.nvidia.com/default/topic/1032970/i2s-mic-with-tx2/

Regards,
Jon

#3

Hi,
thank you for you answer, but i still have some questions.
I couldn’t find any information about these DMIC lines, i did find them in this document :
Jetson_TX1_Pin_and_Function_Names_Guide_Application_Note.pdf

but there was no information in the “Jetson TX1 System-on-Module Data Sheet”.

is there a document that have more information, details, configurations and explanations ?

plus i would like to verify the data i found, i does not correlate 100% with the data you gave me:

Pin D16 is A0_DMIC_IN_DAT (RSVD)
Pin E16 is A0_DMIC_IN_CLK(RSVD)"

both are in the Reserved pin list, are they active or not ?

G5 Pin is I2S2_CLK and is defined also as DMIC2_DAT
G6 Pin is I2S_SDIN and is defined also as DMIC1_DAT
H5 Pin is I2S2_LRCLK and is defined also as DMIC1_CLK
H6 Pin is I2S_SDOUT and is defined also as DMIC2_CLK

So there is no DMIC3_CLK or DMIC3_DATA, i guess it starts with 0

As to the way to connect the PDM lines,
from your answer i understand the the PDM data is the DMICX_DATA and PDM_CLK is the DMICX_CLK.

i should be able to read one mic on the rising edge and the other on the same line on the falling edge.

So please verify all this information, and if there is and document can you add a link ?

I think the Data sheet should be updated with more information than PDM reciever x 6 that is the only line regarding the PDM inputs.
Thank you very much for your help

#4

The only other document is the TX1 pinmux spreadsheet which shows the mapping.

http://developer.nvidia.com/embedded/dlc/jetson-tx1-module-pinmux

The above are the DMIC3. However, you are correct that they are listed as reserved. I will check on why this is.

Yes so the above could be used as well. As mentioned above DMIC3 is labelled as the A0_DMIC (which is unclear indeed).

Yes, if you look at a mems mic such as the following, you will see that there is a pin on the device and determines if the mic uses the left or right channel. So typically if you have two you would configure one for left and one for right and each mic would output data on the appropriate edge.

https://www.st.com/resource/en/datasheet/mp34dt01-m.pdf

Thanks for the feedback.

Regards,
Jon

#5