Take A100 for example, a SM is divided into for sectors, each of which has 8 LD/ST units, but usually every cycle there are 32 memory accesses one from each thread in a warp, so how do the 8 LD/ST units handle 32 memory accesses? If memory coalescing is met, do 8 LD/ST units manage to merge 32 memory accesses into one memory request in just one cycle?
@Robert_Crovella Hello, can you help me with this question?
The LSU is a pipelined unit, just like most other functional resources in a GPU SM. That means although a request will be submitted to it in a particular cycle, it will not necessarily all be processed in a single cycle.
In general, when there are fewer functional units in a SMSP than are needed for a particular instruction type, we could generally expect that the request will be processed over several cycles.
I won’t be able to give a detailed description of LSU behavior, however. Some additional information is available here.
As the above doc says, we can infer that the output per SMSP is 16 if there are 16 cuda cores per SMSP, from which I guess there will be 16 numbers sent per cycle to cuda cores, which means there will be at least 16 banks on the register file to avoid bank conflict, is that right about the number of banks per SMSP?
I don’t have any information on register file banks. As far as I know that is unpublished/undocumented/unspecified by NVIDIA.