64 bits device code

Accelerated Computing CUDA CUDA Programming and Performance
1

Hi all

What is exactly the point of using 64 bits pointers on the device ? I mean, with 32 bits you can address memory up to 4GB, which is the maximum you can find on a card.

Am I missing something or is the 32 bits code sufficient ?

Thanks for your answers.

2

I’ve always thought it was to simplify size and alignment requirements when dealing with structs containing pointers on host and device. If you are passing a struct of pointers to the device, it is much easier if you can assume the size and layout of the members is identical. That is to say: if you compile the host code as 64-bit (which is often a good idea on x86 for non-memory related benefits), then doing the same for device code makes a lot of other issues go away.

Also, the C2070 has (will have?) 6 GB of memory, so then you will need 64-bit pointers for the usual reasons.

3

I’ve always thought it was to simplify size and alignment requirements when dealing with structs containing pointers on host and device. If you are passing a struct of pointers to the device, it is much easier if you can assume the size and layout of the members is identical. That is to say: if you compile the host code as 64-bit (which is often a good idea on x86 for non-memory related benefits), then doing the same for device code makes a lot of other issues go away.

Also, the C2070 has (will have?) 6 GB of memory, so then you will need 64-bit pointers for the usual reasons.

4

For now, zero-copy on Fermi and C2070. Those aren’t the only reasons. :)

5

For now, zero-copy on Fermi and C2070. Those aren’t the only reasons. :)