Hello,
| Pi camera | Orin Devkit | My board |
|---|---|---|
| CAM_D0 | CSI1_D0 | CSI0_D0 |
| CAM_D1 | CSI1_D1 | CSI0_D1 |
| CAM_CK | CSI1_CLK | CSI0_CLK |
| CAM_D2 | CSI0_D0 | CSI1_D0 |
| CAM_D3 | CSI0_D1 | CSI1_D1 |
Thank you.
For 4 lanes need use CSI-2/CSI-3.
Thanks
Sure, your board mapping is supported.
Hello,
Is there anything that needs to be fixed in terms of software? For example, things like dts. If possible, can you point out the points of fixing how to fix it?
Thank you.
Hello,
The two files below seem to be related, but how do I modify them to match my mapping?
Linux_for_Tegra/source/public/kernel/nvidia/drivers/media/i2c/nv_imx477.c
Linux_for_Tegra/source/public/hardware/nvidia/platform/t23x/p3768/kernel-dts/tegra234-p3767-camera-p3768-imx477-dual-4lane.dts
Thanks
Need to modify the port-index/bus-width device tree and lane configuration in the sensor driver(initial REG table).
@ShaneCCC @Trumany
tegra234-p3767-camera-p3768-imx477-dual-4lane.zip (3.5 KB)
tegra234-p3768-0000+p3767-0003-nv.zip (40.4 KB)
dmesg.txt (55.9 KB)
I have attached modified dts and its result dtb.
Could you check it?
Thanks.
I was able to successfully view the video on my board with the settings below.
| Pi camera | Orin Devkit | My board |
|---|---|---|
| CAM_D0 | CSI1_D0 | CSI1_D0 |
| CAM_D1 | CSI1_D1 | CSI1_D1 |
| CAM_CK | CSI1_CLK | CSI1_CLK |
| CAM_D2 | CSI0_D0 | CSI0_D0 |
| CAM_D3 | CSI0_D1 | CSI0_D1 |
Currently, we are unable to view the video on the pin map below.
| Pi camera | Orin Devkit | My board |
|---|---|---|
| CAM_D0 | CSI1_D0 | CSI0_D0 |
| CAM_D1 | CSI1_D1 | CSI0_D1 |
| CAM_CK | CSI1_CLK | CSI0_CLK |
| CAM_D2 | CSI0_D0 | CSI1_D0 |
| CAM_D3 | CSI0_D1 | CSI1_D1 |
Modify the tegra_sinterface to serial_a and the port-index in second port is 2 instead of 1.
Hello,
I have modified below file.
tegra234-p3767-camera-p3768-imx477-dual-4lane.dts
When I search for tegra_sinterface, several results come up. Do I need to change them all to serial_a?
mode0 { /* IMX477_MODE_3840x2160 */
mclk_khz = "24000";
num_lanes = "4";
tegra_sinterface = "serial_b";
phy_mode = "DPHY";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
lane_polarity = "6";
active_w = "3840";
active_h = "2160";
I don’t know which is the second port. Can you tell me?
/ {
overlay-name = "Camera IMX477 Dual 4 lane";
jetson-header-name = "Jetson 24pin CSI Connector";
compatible = JETSON_COMPATIBLE_P3768;
fragment@0 {
target-path = "/";
__overlay__ {
tegra-capture-vi {
num-channels = <2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
rbpcv3_imx477_vi_in0: endpoint {
port-index = <1>;
bus-width = <4>;
remote-endpoint = <&rbpcv3_imx477_csi_out0>;
};
};
port@1 {
reg = <1>;
rbpcv3_imx477_vi_in1: endpoint {
port-index = <2>;
bus-width = <2>;
remote-endpoint = <&rbpcv3_imx477_csi_out1>;
};
};
};
Thank you.
The port-index should be 0 for csi-0/1 4 lanes.
Hello @ShaneCCC @ridgerun @jafeth.garcia
I have failed to see imx477 video on jetson orin nx 8g module.
Could you tell me how can I success to see live video using imx477 on jetson orin nx 8g ?
I’ve attached the dts file I modified.
tegra234-p3767-camera-p3768-imx477-dual-4lane.zip (3.5 KB)
Currently, we are unable to view the video on the pin map below.
| Pi camera | Orin Devkit | My board |
|---|---|---|
| CAM_D0 | CSI1_D0 | CSI0_D0 |
| CAM_D1 | CSI1_D1 | CSI0_D1 |
| CAM_CK | CSI1_CLK | CSI0_CLK |
| CAM_D2 | CSI0_D0 | CSI1_D0 |
| CAM_D3 | CSI0_D1 | CSI1_D1 |
cat /etc/nv_tegra_release
# R36 (release), REVISION: 4.0, GCID: 37537400, BOARD: generic, EABI: aarch64, DATE: Fri Sep 13 04:36:44 UTC 2024
# KERNEL_VARIANT: oot
TARGET_USERSPACE_LIB_DIR=nvidia
TARGET_USERSPACE_LIB_DIR_PATH=usr/lib/aarch64-linux-gnu/nvidia
free
total used free shared buff/cache available
Mem: 7802944 2146252 3761216 116404 1895476 5312448
Swap: 3901464 0 3901464
manager@manager-desktop:~$ ll /dev/video*
crw-rw----+ 1 root video 81, 0 11월 22 11:06 /dev/video0
crw-rw----+ 1 root video 81, 4 11월 22 11:06 /dev/video1
manager@manager-desktop:~$ v4l2-ctl --list-devices --all
NVIDIA Tegra Video Input Device (platform:tegra-camrtc-ca):
/dev/media0
vi-output, imx477 10-001a (platform:tegra-capture-vi:0):
/dev/video1
vi-output, imx477 9-001a (platform:tegra-capture-vi:2):
/dev/video0
Driver Info:
Driver name : tegra-video
Card type : vi-output, imx477 9-001a
Bus info : platform:tegra-capture-vi:2
Driver version : 5.15.148
Capabilities : 0x84200001
Video Capture
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04200001
Video Capture
Streaming
Extended Pix Format
Media Driver Info:
Driver name : tegra-camrtc-ca
Model : NVIDIA Tegra Video Input Device
Serial :
Bus info :
Media version : 5.15.148
Hardware revision: 0x00000003 (3)
Driver version : 5.15.148
Interface Info:
ID : 0x0300000b
Type : V4L Video
Entity Info:
ID : 0x00000009 (9)
Name : vi-output, imx477 9-001a
Function : V4L2 I/O
Pad 0x0100000a : 0: Sink
Link 0x0200000f: from remote pad 0x1000006 of entity '13e00000.host1x:nvcsi@15a00000-' (Unknown sub-device (0002000a)): Data, Enabled
Priority: 2
Video input : 0 (Camera 2: ok)
Format Video Capture:
Width/Height : 3840/2160
Pixel Format : 'RG10' (10-bit Bayer RGRG/GBGB)
Field : None
Bytes per Line : 7680
Size Image : 16588800
Colorspace : sRGB
Transfer Function : Default (maps to sRGB)
YCbCr/HSV Encoding: Default (maps to ITU-R 601)
Quantization : Default (maps to Full Range)
Flags :
Camera Controls
group_hold 0x009a2003 (bool) : default=0 value=0 flags=execute-on-write
sensor_mode 0x009a2008 (int64) : min=0 max=2 step=1 default=0 value=0 flags=slider
gain 0x009a2009 (int64) : min=16 max=357 step=1 default=16 value=16 flags=slider
exposure 0x009a200a (int64) : min=13 max=683710 step=1 default=2495 value=13 flags=slider
frame_rate 0x009a200b (int64) : min=2000000 max=30000000 step=1 default=30000000 value=2000000 flags=slider
sensor_configuration 0x009a2032 (u32) : min=0 max=4294967295 step=1 default=0 dims=[22] flags=read-only, volatile, has-payload
sensor_mode_i2c_packet 0x009a2033 (u32) : min=0 max=4294967295 step=1 default=0 dims=[1026] flags=read-only, volatile, has-payload
sensor_control_i2c_packet 0x009a2034 (u32) : min=0 max=4294967295 step=1 default=0 dims=[1026] flags=read-only, volatile, has-payload
bypass_mode 0x009a2064 (intmenu): min=0 max=1 default=0 value=0 (0 0x0)
0: 0 (0x0)
1: 1 (0x1)
override_enable 0x009a2065 (intmenu): min=0 max=1 default=0 value=0 (0 0x0)
0: 0 (0x0)
1: 1 (0x1)
height_align 0x009a2066 (int) : min=1 max=16 step=1 default=1 value=1
size_align 0x009a2067 (intmenu): min=0 max=2 default=0 value=0 (1 0x1)
0: 1 (0x1)
1: 65536 (0x10000)
2: 131072 (0x20000)
write_isp_format 0x009a2068 (int) : min=1 max=1 step=1 default=1 value=1
sensor_signal_properties 0x009a2069 (u32) : min=0 max=4294967295 step=1 default=0 dims=[30][18] flags=read-only, has-payload
sensor_image_properties 0x009a206a (u32) : min=0 max=4294967295 step=1 default=0 dims=[30][16] flags=read-only, has-payload
sensor_control_properties 0x009a206b (u32) : min=0 max=4294967295 step=1 default=0 dims=[30][36] flags=read-only, has-payload
sensor_dv_timings 0x009a206c (u32) : min=0 max=4294967295 step=1 default=0 dims=[30][16] flags=read-only, has-payload
low_latency_mode 0x009a206d (bool) : default=0 value=0
preferred_stride 0x009a206e (int) : min=0 max=65535 step=1 default=0 value=0
override_capture_timeout_ms 0x009a206f (int) : min=-1 max=2147483647 step=1 default=2500 value=2500
sensor_modes 0x009a2082 (int) : min=0 max=30 step=1 default=30 value=2 flags=read-only
dmesg.txt (57.5 KB)
Thank you.
Get the trace log to check.
sudo su
modprobe rtcpu_debug
echo 1 > /sys/kernel/debug/tracing/tracing_on
echo 30720 > /sys/kernel/debug/tracing/buffer_size_kb
echo 1 > /sys/kernel/debug/tracing/events/tegra_rtcpu/enable
echo 1 > /sys/kernel/debug/tracing/events/freertos/enable
echo 3 > /sys/kernel/debug/camrtc/log-level
echo 1 > /sys/kernel/debug/tracing/events/camera_common/enable
echo > /sys/kernel/debug/tracing/trace
v4l2-ctl --stream-mmap -c bypass_mode=0
cat /sys/kernel/debug/tracing/trace
Hello,
modprobe rtcpu_debug modprobe: FATAL: Module rtcpu_debug not found in directory /lib/modules/5.10.120-tegra
Could you tell me how to resolve this issue?
Thank you.
JP5 don’t need this command.
Hello,
Here’s trace log.
manager@manager-desktop:~$ sudo cat /sys/kernel/debug/tracing/trace
[sudo] password for manager:
# tracer: nop
#
# entries-in-buffer/entries-written: 130/130 #P:6
#
# _-------=> irqs-off
# / _------=> need-resched
# | / _-----=> need-resched-lazy
# || / _----=> hardirq/softirq
# ||| / _---=> preempt-depth
# |||| / _--=> preempt-lazy-depth
# ||||| / _-=> migrate-disable
# |||||| / delay
# TASK-PID CPU# ||||||| TIMESTAMP FUNCTION
# | | | ||||||| | |
v4l2-ctl-5452 [002] ....... 440.070144: tegra_channel_open: vi-output, imx477 9-001a
v4l2-ctl-5452 [002] ....... 440.090679: tegra_channel_set_power: imx477 9-001a : 0x1
v4l2-ctl-5452 [002] ....... 440.090694: camera_common_s_power: status : 0x1
v4l2-ctl-5452 [002] ....... 440.390835: tegra_channel_set_power: 13e00000.host1x:nvcsi@15a00000- : 0x1
v4l2-ctl-5452 [002] ....... 440.390844: csi_s_power: enable : 0x1
v4l2-ctl-5452 [002] ....... 440.392056: tegra_channel_capture_setup: vnc_id 0 W 3840 H 2160 fmt c4
vi-output, imx4-5453 [002] ....... 440.400796: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [002] ....... 440.400804: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [002] ....... 440.400806: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [002] ....... 440.400808: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
v4l2-ctl-5452 [001] ....... 440.400842: tegra_channel_set_stream: enable : 0x1
v4l2-ctl-5452 [002] ....... 440.404875: tegra_channel_set_stream: 13e00000.host1x:nvcsi@15a00000- : 0x1
v4l2-ctl-5452 [002] ....... 440.404878: csi_s_stream: enable : 0x1
v4l2-ctl-5452 [002] ....... 440.405294: tegra_channel_set_stream: imx477 9-001a : 0x1
kworker/5:1-4938 [005] ....... 440.435545: rtcpu_string: tstamp:14616900508 id:0x04010000 str:"VM0 activating."
kworker/5:1-4938 [005] ....... 440.435552: rtcpu_vinotify_event: tstamp:14617574836 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:467746169504 data:0x799e300010000000
kworker/5:1-4938 [005] ....... 440.435553: rtcpu_vinotify_event: tstamp:14617575104 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:467746179168 data:0x0000000031000001
kworker/5:1-4938 [005] ....... 440.435554: rtcpu_vinotify_event: tstamp:14617575393 cch:0 vi:1 tag:VIFALC_ACTIONLST channel:0x23 frame:0 vi_tstamp:467746183744 data:0x0000000007020001
kworker/5:1-4938 [005] ....... 440.435555: rtcpu_vinotify_event: tstamp:14617575646 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:467746292480 data:0x799e2d0010000000
kworker/5:1-4938 [005] ....... 440.435555: rtcpu_vinotify_event: tstamp:14617575926 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:467746302336 data:0x0000000031000002
vi-output, imx4-5454 [000] ....... 443.100750: tegra_channel_capture_setup: vnc_id 0 W 3840 H 2160 fmt c4
vi-output, imx4-5453 [002] ....... 443.100932: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [002] ....... 443.100940: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [002] ....... 443.100941: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [002] ....... 443.100942: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
kworker/5:1-4938 [005] ....... 443.127408: rtcpu_vinotify_event: tstamp:14701668343 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:470446498336 data:0x799e300010000000
kworker/5:1-4938 [005] ....... 443.127412: rtcpu_vinotify_event: tstamp:14701668639 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:470446540416 data:0x0000000031000001
kworker/5:1-4938 [005] ....... 443.127413: rtcpu_vinotify_event: tstamp:14701668897 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:470446558560 data:0x799e2d0010000000
kworker/5:1-4938 [005] ....... 443.127414: rtcpu_vinotify_event: tstamp:14701669181 cch:0 vi:1 tag:VIFALC_ACTIONLST channel:0x23 frame:0 vi_tstamp:470446578880 data:0x0000000007020001
kworker/5:1-4938 [005] ....... 443.127414: rtcpu_vinotify_event: tstamp:14701669435 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:470446621280 data:0x0000000031000002
vi-output, imx4-5454 [000] ....... 445.660692: tegra_channel_capture_setup: vnc_id 0 W 3840 H 2160 fmt c4
vi-output, imx4-5453 [002] ....... 445.660879: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [002] ....... 445.660889: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [002] ....... 445.660891: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [002] ....... 445.660892: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
kworker/5:1-4938 [005] ....... 445.727254: rtcpu_vinotify_event: tstamp:14781964081 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:473006390624 data:0x799e300010000000
kworker/5:1-4938 [005] ....... 445.727258: rtcpu_vinotify_event: tstamp:14781964347 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:473006447584 data:0x0000000031000001
kworker/5:1-4938 [005] ....... 445.727260: rtcpu_vinotify_event: tstamp:14781964634 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:473006465728 data:0x799e2d0010000000
kworker/5:1-4938 [005] ....... 445.727260: rtcpu_vinotify_event: tstamp:14781964885 cch:0 vi:1 tag:VIFALC_ACTIONLST channel:0x23 frame:0 vi_tstamp:473006486112 data:0x0000000007020001
kworker/5:1-4938 [005] ....... 445.727262: rtcpu_vinotify_event: tstamp:14781965167 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:473006528512 data:0x0000000031000002
vi-output, imx4-5454 [000] ....... 448.223754: tegra_channel_capture_setup: vnc_id 0 W 3840 H 2160 fmt c4
vi-output, imx4-5453 [003] ....... 448.223934: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [003] ....... 448.223945: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [003] ....... 448.223947: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [003] ....... 448.223948: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
kworker/5:1-4938 [005] ....... 448.259114: rtcpu_vinotify_event: tstamp:14861549328 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:475569445504 data:0x799e300010000000
kworker/5:1-4938 [005] ....... 448.259118: rtcpu_vinotify_event: tstamp:14862043554 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:475569625600 data:0x0000000031000001
kworker/5:1-4938 [005] ....... 448.259119: rtcpu_vinotify_event: tstamp:14862043810 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:475569643776 data:0x799e2d0010000000
kworker/5:1-4938 [005] ....... 448.259120: rtcpu_vinotify_event: tstamp:14862044124 cch:0 vi:1 tag:VIFALC_ACTIONLST channel:0x23 frame:0 vi_tstamp:475569664128 data:0x0000000007020001
kworker/5:1-4938 [005] ....... 448.259121: rtcpu_vinotify_event: tstamp:14862044374 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:475569741184 data:0x0000000031000002
vi-output, imx4-5454 [000] ....... 450.779596: tegra_channel_capture_setup: vnc_id 0 W 3840 H 2160 fmt c4
vi-output, imx4-5453 [002] ....... 450.779813: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [002] ....... 450.779828: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [002] ....... 450.779831: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [002] ....... 450.779833: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
kworker/5:1-4938 [005] ....... 450.822983: rtcpu_vinotify_event: tstamp:14941796607 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:478125353536 data:0x799e300010000000
kworker/5:1-4938 [005] ....... 450.822987: rtcpu_vinotify_event: tstamp:14941796868 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:478125410432 data:0x0000000031000001
kworker/5:1-4938 [005] ....... 450.822989: rtcpu_vinotify_event: tstamp:14941797154 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:478125428608 data:0x799e2d0010000000
kworker/5:1-4938 [005] ....... 450.822989: rtcpu_vinotify_event: tstamp:14941797403 cch:0 vi:1 tag:VIFALC_ACTIONLST channel:0x23 frame:0 vi_tstamp:478125448960 data:0x0000000007020001
kworker/5:1-4938 [005] ....... 450.822990: rtcpu_vinotify_event: tstamp:14941797685 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:478125491360 data:0x0000000031000002
vi-output, imx4-5454 [000] ....... 453.340090: tegra_channel_capture_setup: vnc_id 0 W 3840 H 2160 fmt c4
vi-output, imx4-5453 [002] ....... 453.340452: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [002] ....... 453.340462: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [002] ....... 453.340463: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [002] ....... 453.340464: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
kworker/5:1-4938 [005] ....... 453.366841: rtcpu_vinotify_event: tstamp:15021550387 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:480685970880 data:0x799e300010000000
kworker/5:1-4938 [005] ....... 453.366844: rtcpu_vinotify_event: tstamp:15021550680 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:480686066912 data:0x0000000031000001
kworker/5:1-4938 [005] ....... 453.366845: rtcpu_vinotify_event: tstamp:15021550935 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:480686085024 data:0x799e2d0010000000
kworker/5:1-4938 [005] ....... 453.366846: rtcpu_vinotify_event: tstamp:15021551218 cch:0 vi:1 tag:VIFALC_ACTIONLST channel:0x23 frame:0 vi_tstamp:480686105408 data:0x0000000007020001
kworker/5:1-4938 [005] ....... 453.366847: rtcpu_vinotify_event: tstamp:15021551467 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:480686147776 data:0x0000000031000002
vi-output, imx4-5454 [000] ....... 455.899879: tegra_channel_capture_setup: vnc_id 0 W 3840 H 2160 fmt c4
vi-output, imx4-5453 [002] ....... 455.900372: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [002] ....... 455.900383: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [002] ....... 455.900384: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [002] ....... 455.900385: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
kworker/5:1-4938 [005] ....... 455.954711: rtcpu_vinotify_event: tstamp:15101438950 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:483245876992 data:0x799e300010000000
kworker/5:1-4938 [005] ....... 455.954715: rtcpu_vinotify_event: tstamp:15101439212 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:483245936992 data:0x0000000031000001
kworker/5:1-4938 [005] ....... 455.954716: rtcpu_vinotify_event: tstamp:15101954232 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:483246046368 data:0x799e2d0010000000
kworker/5:1-4938 [005] ....... 455.954717: rtcpu_vinotify_event: tstamp:15101954487 cch:0 vi:1 tag:VIFALC_ACTIONLST channel:0x23 frame:0 vi_tstamp:483246066720 data:0x0000000007020001
kworker/5:1-4938 [005] ....... 455.954718: rtcpu_vinotify_event: tstamp:15101954828 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:483246109088 data:0x0000000031000002
vi-output, imx4-5454 [000] ....... 458.459829: tegra_channel_capture_setup: vnc_id 0 W 3840 H 2160 fmt c4
vi-output, imx4-5453 [002] ....... 458.460290: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [002] ....... 458.460301: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [002] ....... 458.460302: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [002] ....... 458.460303: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
kworker/5:1-4938 [005] ....... 458.478575: rtcpu_vinotify_event: tstamp:15181708063 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:485805752032 data:0x799e300010000000
kworker/5:1-4938 [005] ....... 458.478578: rtcpu_vinotify_event: tstamp:15181708356 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:485805829504 data:0x0000000031000001
kworker/5:1-4938 [005] ....... 458.478579: rtcpu_vinotify_event: tstamp:15181708612 cch:0 vi:1 tag:VIFALC_ACTIONLST channel:0x23 frame:0 vi_tstamp:485805851232 data:0x0000000007020001
kworker/5:1-4938 [005] ....... 458.478580: rtcpu_vinotify_event: tstamp:15181708893 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:485805953280 data:0x799e2d0010000000
kworker/5:1-4938 [005] ....... 458.478581: rtcpu_vinotify_event: tstamp:15181709142 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:485805995936 data:0x0000000031000002
vi-output, imx4-5454 [000] ....... 461.019965: tegra_channel_capture_setup: vnc_id 0 W 3840 H 2160 fmt c4
vi-output, imx4-5453 [002] ....... 461.020312: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [002] ....... 461.020323: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [002] ....... 461.020324: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [002] ....... 461.020326: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
kworker/5:1-4938 [005] ....... 461.034445: rtcpu_vinotify_event: tstamp:15261461778 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:488365779776 data:0x799e300010000000
kworker/5:1-4938 [005] ....... 461.034448: rtcpu_vinotify_event: tstamp:15261462038 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:488365867392 data:0x0000000031000001
kworker/5:1-4938 [005] ....... 461.034449: rtcpu_vinotify_event: tstamp:15261462324 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:488365885536 data:0x799e2d0010000000
kworker/5:1-4938 [005] ....... 461.034449: rtcpu_vinotify_event: tstamp:15261462573 cch:0 vi:1 tag:VIFALC_ACTIONLST channel:0x23 frame:0 vi_tstamp:488365905920 data:0x0000000007020001
kworker/5:1-4938 [005] ....... 461.034450: rtcpu_vinotify_event: tstamp:15261462856 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:488365948256 data:0x0000000031000002
vi-output, imx4-5454 [002] ....... 463.579739: tegra_channel_capture_setup: vnc_id 0 W 3840 H 2160 fmt c4
vi-output, imx4-5453 [000] ....... 463.579900: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [000] ....... 463.579911: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [000] ....... 463.579913: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [000] ....... 463.579914: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
kworker/5:1-4938 [005] ....... 463.630322: rtcpu_vinotify_event: tstamp:15341425715 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:490925436128 data:0x799e300010000000
kworker/5:1-4938 [005] ....... 463.630326: rtcpu_vinotify_event: tstamp:15341426009 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:490925493120 data:0x0000000031000001
kworker/5:1-4938 [005] ....... 463.630327: rtcpu_vinotify_event: tstamp:15341426266 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:490925511264 data:0x799e2d0010000000
kworker/5:1-4938 [005] ....... 463.630328: rtcpu_vinotify_event: tstamp:15341920453 cch:0 vi:1 tag:VIFALC_ACTIONLST channel:0x23 frame:0 vi_tstamp:490925623232 data:0x0000000007020001
kworker/5:1-4938 [005] ....... 463.630328: rtcpu_vinotify_event: tstamp:15341920707 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:490925697056 data:0x0000000031000002
vi-output, imx4-5454 [002] ....... 466.138737: tegra_channel_capture_setup: vnc_id 0 W 3840 H 2160 fmt c4
vi-output, imx4-5453 [000] ....... 466.138912: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [000] ....... 466.138926: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [000] ....... 466.138928: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [000] ....... 466.138930: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
kworker/5:1-4938 [005] ....... 466.154137: rtcpu_vinotify_event: tstamp:15421673456 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:493484431712 data:0x799e300010000000
kworker/5:1-4938 [005] ....... 466.154140: rtcpu_vinotify_event: tstamp:15421673771 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:493484488672 data:0x0000000031000001
kworker/5:1-4938 [005] ....... 466.154141: rtcpu_vinotify_event: tstamp:15421674059 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:493484506816 data:0x799e2d0010000000
kworker/5:1-4938 [005] ....... 466.154142: rtcpu_vinotify_event: tstamp:15421674315 cch:0 vi:1 tag:VIFALC_ACTIONLST channel:0x23 frame:0 vi_tstamp:493484527136 data:0x0000000007020001
kworker/5:1-4938 [005] ....... 466.154143: rtcpu_vinotify_event: tstamp:15421674608 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:493484569536 data:0x0000000031000002
vi-output, imx4-5454 [002] ....... 468.698678: tegra_channel_capture_setup: vnc_id 0 W 3840 H 2160 fmt c4
vi-output, imx4-5453 [000] ....... 468.698855: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [000] ....... 468.698868: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [000] ....... 468.698870: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
vi-output, imx4-5453 [000] ....... 468.698871: vi_task_submit: class_id:48 ch:0 syncpt_id:27 syncpt_thresh:0 pid:5453 tid:5453
kworker/5:1-4938 [005] ....... 468.745650: rtcpu_vinotify_event: tstamp:15501426485 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:496044362848 data:0x799e300010000000
kworker/5:1-4938 [005] ....... 468.745653: rtcpu_vinotify_event: tstamp:15501426778 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:496044419776 data:0x0000000031000001
kworker/5:1-4938 [005] ....... 468.745654: rtcpu_vinotify_event: tstamp:15501427031 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:496044437824 data:0x799e2d0010000000
kworker/5:1-4938 [005] ....... 468.745655: rtcpu_vinotify_event: tstamp:15501427316 cch:0 vi:1 tag:VIFALC_ACTIONLST channel:0x23 frame:0 vi_tstamp:496044458144 data:0x0000000007020001
kworker/5:1-4938 [005] ....... 468.745656: rtcpu_vinotify_event: tstamp:15501427565 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:496044500544 data:0x0000000031000002
manager@manager-desktop:~$
Thank you.
Didn’t receive any validate data from the sensor from the trace log.
Maybe confirm the pix_clk_hz/serdes_pix_clk_hz and probe the output to confirm the output signal.
Skew calibration is required if sensor or deserializer is using DPHY, and the output data rate is > 1.5Gbps.
An initiation deskew signal should be sent by sensor or deserializer to perform the skew calibration. If the deskew signals is not sent, the receiver will stall, and the capture will time out.
You can calculate the output data rate with the following equation:
Output data rate = (sensor or deserializer pixel clock in hertz) * (bits per pixel) / (number of CSI lanes)
Hello,
anager@manager-desktop:~/github-repository/CSI-Camera$ sudo media-ctl -p -d /dev/media0
Media controller API version 5.15.148
Media device information
------------------------
driver tegra-camrtc-ca
model NVIDIA Tegra Video Input Device
serial
bus info
hw revision 0x3
driver version 5.15.148
Device topology
- entity 1: 13e00000.host1x:nvcsi@15a00000- (2 pads, 2 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev0
pad0: Sink
<- "imx477 10-001a":0 [ENABLED]
pad1: Source
-> "vi-output, imx477 10-001a":0 [ENABLED]
- entity 4: 13e00000.host1x:nvcsi@15a00000- (2 pads, 2 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev1
pad0: Sink
<- "imx477 9-001a":0 [ENABLED]
pad1: Source
-> "vi-output, imx477 9-001a":0 [ENABLED]
- entity 7: imx477 9-001a (1 pad, 1 link)
type V4L2 subdev subtype Sensor flags 0
device node name /dev/v4l-subdev2
pad0: Source
[fmt:SRGGB10_1X10/3840x2160 field:none colorspace:srgb]
-> "13e00000.host1x:nvcsi@15a00000-":0 [ENABLED]
- entity 9: vi-output, imx477 9-001a (1 pad, 1 link)
type Node subtype V4L flags 0
device node name /dev/video0
pad0: Sink
<- "13e00000.host1x:nvcsi@15a00000-":1 [ENABLED]
- entity 23: imx477 10-001a (1 pad, 1 link)
type V4L2 subdev subtype Sensor flags 0
device node name /dev/v4l-subdev3
pad0: Source
[fmt:SRGGB10_1X10/3840x2160 field:none colorspace:srgb]
-> "13e00000.host1x:nvcsi@15a00000-":0 [ENABLED]
- entity 25: vi-output, imx477 10-001a (1 pad, 1 link)
type Node subtype V4L flags 0
device node name /dev/video1
pad0: Sink
<- "13e00000.host1x:nvcsi@15a00000-":1 [ENABLED]
Thank you.
IMX477 data information
Image width: 3840
Image height: 2160
bayer data bit width: 10bit
frame rate: 30fps
Total output data bitrate is 3840 x 2160 x 10bit x 30fps = 2,488,320,000 (about 2.5G)
Output data bitrate per lane is 2,488,320,000 / 4 = 6,222,080,000 (about 0.6G)
I think the output data rate you mentioned is 0.6G.
The reporting output data rate depend on the pix_clk_hz/serdes_pix_clk_hz in my previous comment’s calculation.