Hi,
We have a custom carrier board (orin nx) with camera connected to CSI 2 + CSI 3 (4 lane).
The below is my device tree configuration (JP5.1.2). Do I have to configure for both CSI 2 and CSI 3?
dts.txt (412.4 KB)
Please advice.
hello san1998,
as mentioned by design guide, for 4-Lane Camera 2. Only CSI 2 Clock is used.
did you based-on ov5693 for development? I saw you’re having some code changes for ov5693 camera nodes.
if yes, please also note that,compatible = "ovti,ov5693"; as device identifier. it’s keyword used by the Linux kernel uses to bind the device driver to a specific device.
besides,
there’s reference driver which able to enable 4-lane camera sensor on CSI-C.
please see-also… $public_sources/kernel_src/hardware/nvidia/platform/t23x/p3768/kernel-dts/tegra234-p3767-camera-p3768-imx477-dual-4lane.dts
Yes I am using OV5693 driver for 4 lane implementation. Will this driver work? Or should i use imx477?
OV5693 can be referenced.
Thanks
Hi,
I am using ov5693 as reference driver, the video node is not formed for the below device tree configuration.
Please advice.
4lane.dts.txt (414.9 KB)
CSI2 + CSI3 - 4 lane MIPI
Thanks
Please check the dmesg to know the reason.
Thanks
we have disabled i2c communication in our driver.
I want to review my device tree configuration to make sure i have defined it correctly to combine csi 2 and csi 3 for 4 lane.
2 lane MIPI individually works fine, we never reviewed for 4 lane output.
so: currently the dmesg is :
[ 7.534858] ov5693 2-0010: probing v4l2 sensor.
[ 7.539781] ov5693 2-0010: tegracam sensor driver:ov5693_v2.0.6
[ 7.545872] ov5693 2-0010: ov5693_board_setup++
[ 7.546943] tegra-camrtc-capture-vi tegra-capture-vi: subdev ov5693 2-0010 bound
[ 7.554550] ov5693 2-0010: Detected OV5693 sensor
The num_lanes, num_csi_lanes is incorrect.
The port@1{} should remove.
Also the port@1 in tegra-capture-vi {} should remove if only one sensor.
Also the channel@1 in nvcsi@15a00000
step_exp_time = [31 00];
default_exp_time = "33334";
embedded_metadata_height = [30 00];
};
ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
port@0 {
reg = <0x00>;
endpoint {
port-index = <0x02>;
bus-width = <0x04>;
remote-endpoint = <0x6d>;
phandle = <0x28f>;
};
};
port@1 {
reg = <0x00>;
endpoint {
port-index = <0x03>;
bus-width = <0x04>;
remote-endpoint = <0x6e>;
phandle = <0x291>;
};
};
};
thanks.
i removed port 1 , channel 1.
i have the device tree config defined only for CSI 2 - 4 lane now
i have the video node on, but there is no video dump on cat /dev/video0
4lane.dts.txt (412.3 KB)
# cat /sys/kernel/debug/tracing/trace
# tracer: nop
#
# entries-in-buffer/entries-written: 30/30 #P:4
#
# _-----=> irqs-off
# / _----=> need-resched
# | / _---=> hardirq/softirq
# || / _--=> preempt-depth
# ||| / delay
# TASK-PID CPU# |||| TIMESTAMP FUNCTION
# | | | |||| | |
kworker/0:4-104 [000] .... 133.135639: rtcpu_string: tstamp:4849316012 id:0x04010000 str:"VM0 deactivating."
kworker/0:4-104 [000] .... 133.359638: rtcpu_string: tstamp:4856340144 id:0x04010000 str:"VM0 activating."
kworker/0:4-104 [000] .... 133.359642: rtcpu_vinotify_event: tstamp:4856992797 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:155407913760 data:0x759e300010000000
kworker/0:4-104 [000] .... 133.359643: rtcpu_vinotify_event: tstamp:4856992960 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:155407920256 data:0x0000000031000001
kworker/0:4-104 [000] .... 133.359643: rtcpu_vinotify_event: tstamp:4856993114 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:155407981024 data:0x759e2d0010000000
kworker/0:4-104 [000] .... 133.359644: rtcpu_vinotify_event: tstamp:4856993256 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:155407987616 data:0x0000000031000002
kworker/0:4-104 [000] .... 136.111636: rtcpu_vinotify_event: tstamp:4942714588 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:158154913952 data:0x759e300010000000
kworker/0:4-104 [000] .... 136.111639: rtcpu_vinotify_event: tstamp:4942714727 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:158154956640 data:0x0000000031000001
kworker/0:4-104 [000] .... 136.335617: rtcpu_vinotify_event: tstamp:4950852028 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:158414647680 data:0x759e2d0010000000
kworker/0:4-104 [000] .... 136.335620: rtcpu_vinotify_event: tstamp:4950852168 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:158414691040 data:0x0000000031000002
kworker/0:4-104 [000] .... 138.855617: rtcpu_vinotify_event: tstamp:5028977910 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:160914656960 data:0x759e300010000000
kworker/0:4-104 [000] .... 138.855620: rtcpu_vinotify_event: tstamp:5028978046 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:160914699648 data:0x0000000031000001
kworker/0:4-104 [000] .... 139.191614: rtcpu_vinotify_event: tstamp:5039286694 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:161250988864 data:0x759e2d0010000000
kworker/0:4-104 [000] .... 139.191617: rtcpu_vinotify_event: tstamp:5039286840 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:161251032224 data:0x0000000031000002
kworker/0:4-104 [000] .... 141.655616: rtcpu_vinotify_event: tstamp:5116869721 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:163730863296 data:0x759e300010000000
kworker/0:4-104 [000] .... 141.655619: rtcpu_vinotify_event: tstamp:5116869860 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:163730905984 data:0x0000000031000001
kworker/0:4-104 [000] .... 141.935617: rtcpu_vinotify_event: tstamp:5125916137 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:164029184128 data:0x759e2d0010000000
kworker/0:4-104 [000] .... 141.935620: rtcpu_vinotify_event: tstamp:5125916276 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:164029227520 data:0x0000000031000002
kworker/0:4-104 [000] .... 144.459630: rtcpu_vinotify_event: tstamp:5204652173 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:166547098432 data:0x759e300010000000
kworker/0:4-104 [000] .... 144.459633: rtcpu_vinotify_event: tstamp:5204652311 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:166547141120 data:0x0000000031000001
kworker/0:4-104 [000] .... 144.859657: rtcpu_vinotify_event: tstamp:5216045729 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:166903848096 data:0x759e2d0010000000
kworker/0:4-104 [000] .... 144.859660: rtcpu_vinotify_event: tstamp:5216045874 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:166903891456 data:0x0000000031000002
kworker/0:4-104 [000] .... 147.331661: rtcpu_vinotify_event: tstamp:5293086175 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:169362882592 data:0x759e300010000000
kworker/0:4-104 [000] .... 147.331664: rtcpu_vinotify_event: tstamp:5293086315 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:169362925280 data:0x0000000031000001
kworker/0:4-104 [000] .... 147.611657: rtcpu_vinotify_event: tstamp:5302852429 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:169683769696 data:0x759e2d0010000000
kworker/0:4-104 [000] .... 147.611660: rtcpu_vinotify_event: tstamp:5302852568 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:169683813024 data:0x0000000031000002
kworker/0:4-104 [000] .... 150.135679: rtcpu_vinotify_event: tstamp:5380978156 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:172178880032 data:0x759e300010000000
kworker/0:4-104 [000] .... 150.135682: rtcpu_vinotify_event: tstamp:5380978295 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:172178922720 data:0x0000000031000001
kworker/0:4-104 [000] .... 150.475675: rtcpu_vinotify_event: tstamp:5391829187 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:172527453472 data:0x759e2d0010000000
kworker/0:4-104 [000] .... 150.475678: rtcpu_vinotify_event: tstamp:5391829327 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:172527496800 data:0x0000000031000002
The trace log shows didn’t receive any validate data from the sensor.
While probing the signal on hardware we can see the data and clock signals.
Could you please confirm if my device tree configuration for CSI2_CSI3 4 lane is correct?
The device tree is correct to set the port-index=2 and bus-width=4 for CSI2-3 4 lane.
1 Like
If i want CSI0+CSI1 4 lane output then i have to configure
port-index=0 and bus-width=4 with lane_polarity=“6”, am i correct?
Yes, that’s correct for CSI0+CSI1 aka CSIA+B
For CSI2_3 - 4 lane i still do not get video dump.
Trace log: status:0x00000044
pix_clk_hz = 80000000
kworker/3:1-138 [003] .... 151.659209: rtcpu_nvcsi_intr: tstamp:5495907477 class:GLOBAL type:PHY_INTR0 phy:1 cil:1 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659209: rtcpu_nvcsi_intr: tstamp:5495908400 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659209: rtcpu_nvcsi_intr: tstamp:5495908400 class:GLOBAL type:PHY_INTR0 phy:1 cil:1 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659210: rtcpu_nvcsi_intr: tstamp:5495909326 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659210: rtcpu_nvcsi_intr: tstamp:5495909326 class:GLOBAL type:PHY_INTR0 phy:1 cil:1 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659210: rtcpu_nvcsi_intr: tstamp:5495910253 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659211: rtcpu_nvcsi_intr: tstamp:5495910253 class:GLOBAL type:PHY_INTR0 phy:1 cil:1 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659211: rtcpu_nvcsi_intr: tstamp:5495911179 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659211: rtcpu_nvcsi_intr: tstamp:5495911179 class:GLOBAL type:PHY_INTR0 phy:1 cil:1 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659212: rtcpu_nvcsi_intr: tstamp:5495912106 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659212: rtcpu_nvcsi_intr: tstamp:5495912106 class:GLOBAL type:PHY_INTR0 phy:1 cil:1 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659213: rtcpu_nvcsi_intr: tstamp:5495913028 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659213: rtcpu_nvcsi_intr: tstamp:5495913028 class:GLOBAL type:PHY_INTR0 phy:1 cil:1 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659213: rtcpu_nvcsi_intr: tstamp:5495913957 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659214: rtcpu_nvcsi_intr: tstamp:5495913957 class:GLOBAL type:PHY_INTR0 phy:1 cil:1 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659214: rtcpu_nvcsi_intr: tstamp:5495914882 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659214: rtcpu_nvcsi_intr: tstamp:5495914882 class:GLOBAL type:PHY_INTR0 phy:1 cil:1 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659215: rtcpu_nvcsi_intr: tstamp:5495915808 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659215: rtcpu_nvcsi_intr: tstamp:5495915808 class:GLOBAL type:PHY_INTR0 phy:1 cil:1 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659216: rtcpu_nvcsi_intr: tstamp:5495916734 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659216: rtcpu_nvcsi_intr: tstamp:5495916734 class:GLOBAL type:PHY_INTR0 phy:1 cil:1 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659216: rtcpu_nvcsi_intr: tstamp:5495917661 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659217: rtcpu_nvcsi_intr: tstamp:5495917661 class:GLOBAL type:PHY_INTR0 phy:1 cil:1 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659217: rtcpu_nvcsi_intr: tstamp:5495918587 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659217: rtcpu_nvcsi_intr: tstamp:5495918587 class:GLOBAL type:PHY_INTR0 phy:1 cil:1 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659218: rtcpu_nvcsi_intr: tstamp:5495919510 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659218: rtcpu_nvcsi_intr: tstamp:5495919510 class:GLOBAL type:PHY_INTR0 phy:1 cil:1 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659218: rtcpu_nvcsi_intr: tstamp:5495920437 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659219: rtcpu_nvcsi_intr: tstamp:5495920437 class:GLOBAL type:PHY_INTR0 phy:1 cil:1 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659219: rtcpu_nvcsi_intr: tstamp:5495921363 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659219: rtcpu_nvcsi_intr: tstamp:5495921363 class:GLOBAL type:PHY_INTR0 phy:1 cil:1 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659220: rtcpu_nvcsi_intr: tstamp:5495922289 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659220: rtcpu_nvcsi_intr: tstamp:5495922289 class:GLOBAL type:PHY_INTR0 phy:1 cil:1 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659221: rtcpu_nvcsi_intr: tstamp:5495923216 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659221: rtcpu_nvcsi_intr: tstamp:5495923216 class:GLOBAL type:PHY_INTR0 phy:1 cil:1 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659221: rtcpu_nvcsi_intr: tstamp:5495924141 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659222: rtcpu_nvcsi_intr: tstamp:5495924141 class:GLOBAL type:PHY_INTR0 phy:1 cil:1 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659222: rtcpu_nvcsi_intr: tstamp:5495925069 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659222: rtcpu_nvcsi_intr: tstamp:5495925069 class:GLOBAL type:PHY_INTR0 phy:1 cil:1 st:0 vc:0 status:0x00000044
kworker/3:1-138 [003] .... 151.659223: rtcpu_nvcsi_intr: tstamp:5495925992 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x00000044
This error tell the MIPI timing cause the problem.(SOT error)
Have reference below to confirm the timing.
This doesn’t looks right.