Jetson TX2 Single Lane MIPI Camera

Hi All,

I have seen in TX2 dtsi and kernel src where by default 2-lane CSI driver example has given(OV5693).
I want to modify TX2 dtsi and driver for 1-Lane CSI. what all modifications I need to do in kernel
and dts file. (P.S. I am using R27.1 package).

TIA
dmesg.txt (61.9 KB)

hello atrivedi,

the OV5693’s one lane mode settings is already included in the release kernel driver.
you can simply enable OV5693 one lane mode in the sensor device tree for verification.
please check one lane mode settings at below path, thanks
$TOP/kernel/kernel-4.4/drivers/media/i2c/ov5693_mode_tbls.h

Hi JerryChang,

Thanks for your reply. My sensor is not OV5693. I am using that as a reference driver.
I am writing my driver for YUV data where i2c is preconfigured and using 1-LANE CSI.
so according to dtsi. I have changed bus-width in dtsi file and mbus_config in camera_common.c
Is that Sufficient? or I need to do anything else?

TIA.

hello atrivedi,

yes, please configure your sensor device tree to report one lane.
you should also extend the supported color format in the camera_common.c, please check below.
thanks

r28.1_sources/kernel/kernel-4.4/drivers/media/platform/tegra/camera/camera_common.c

static const struct camera_common_colorfmt camera_common_color_fmts[] = {...}

Hi,

Thanks for reply. I have added YUV support in camera_common_color_fmts. I have changed
bus-width of CSI port and num_lanes=“1” in sensor part in dtsi . I am modifying OV5693 driver file
only to support my YUV sensor. I have commneted i2c related code because my sensor does not require
i2c settings.I am getting /dev/video0 /dev/video1. but when I do cat /dev/video0 I am getting
following error:

cat: /dev/video0: Cannot allocate memory
tegra-vi4 15700000.vi: dma_alloc_coherent of size 0 failed

Any Suggestion where I am making mistake?

TIA

hello atrivedi,

please gather the full kernel message and attach it to the forum by edit your own comments at the top-right.
also, may i know who’s your yuv sensor vendor?
thanks

Hi,

https://pastebin.com/Kc6MKsfu

Above is my kernel log. My sensor is custom one.

hello atrivedi,

i’m not able to access your shareable website,
could you please upload the kernel logs to the forum system instead.
thanks

Hi,

PFA
dmesg.txt (61.9 KB)

hello atrivedi,

i saw some i2c no acknowledge message from the logs,
could you please check and confirm your device has been probe successfully?
thanks

Hi JerryChang,

Yes Probing looks successful. I have enabled debug prints. those i2c ack errors from other
devices.

Thanks.

Hi All,

I have configured 1-Lane Mipi camera to elroy +Tx2. my pixelformat is yuyv. and I have flashed r27.1
BSP package. Sensor is custom made. When I try to capture image I am getting following error:

[ 485.901155] tegra_mipi_cal 3990000.mipical: Mipi cal timeout,val:9671, lanes:100000
[ 485.901167] tegra_mipi_cal 3990000.mipical: MIPI_CAL_CTRL 0x04 0x2a000010
[ 485.901174] tegra_mipi_cal 3990000.mipical: CIL_MIPI_CAL_STATUS 0x0c 0x00009671
[ 485.901180] tegra_mipi_cal 3990000.mipical: CIL_MIPI_CAL_STATUS_2 0x10 0x00000000
[ 485.901189] tegra_mipi_cal 3990000.mipical: CILA_MIPI_CAL_CONFIG 0x18 0x00200000
[ 485.901196] tegra_mipi_cal 3990000.mipical: CILB_MIPI_CAL_CONFIG 0x1c 0x00000000
[ 485.901202] tegra_mipi_cal 3990000.mipical: CILC_MIPI_CAL_CONFIG 0x20 0x00000000
[ 485.901207] tegra_mipi_cal 3990000.mipical: CILD_MIPI_CAL_CONFIG 0x24 0x00000000
[ 485.901215] tegra_mipi_cal 3990000.mipical: CILE_MIPI_CAL_CONFIG 0x28 0x00000000
[ 485.901221] tegra_mipi_cal 3990000.mipical: CILF_MIPI_CAL_CONFIG 0x2c 0x00000000
[ 485.901227] tegra_mipi_cal 3990000.mipical: DSIA_MIPI_CAL_CONFIG 0x3c 0x00000000
[ 485.901233] tegra_mipi_cal 3990000.mipical: DSIB_MIPI_CAL_CONFIG 0x40 0x00000000
[ 485.901240] tegra_mipi_cal 3990000.mipical: DSIC_MIPI_CAL_CONFIG 0x44 0x00000000
[ 485.901246] tegra_mipi_cal 3990000.mipical: DSID_MIPI_CAL_CONFIG 0x48 0x00000000
[ 485.901252] tegra_mipi_cal 3990000.mipical: MIPI_BIAS_PAD_CFG0 0x5c 0x00000000
[ 485.901259] tegra_mipi_cal 3990000.mipical: MIPI_BIAS_PAD_CFG1 0x60 0x00000000
[ 485.901264] tegra_mipi_cal 3990000.mipical: MIPI_BIAS_PAD_CFG2 0x64 0x00000000
[ 485.901271] tegra_mipi_cal 3990000.mipical: DSIA_MIPI_CAL_CONFIG_2 0x68 0x00000000
[ 485.901277] tegra_mipi_cal 3990000.mipical: DSIB_MIPI_CAL_CONFIG_2 0x6c 0x00000000
[ 485.901284] tegra_mipi_cal 3990000.mipical: DSIC_MIPI_CAL_CONFIG_2 0x74 0x00000000
[ 485.901289] tegra_mipi_cal 3990000.mipical: DSID_MIPI_CAL_CONFIG_2 0x78 0x00000000
[ 485.901298] nvcsi 150c0000.nvcsi: csi4_start_streaming ports index=0, lanes=2
[ 485.901302] nvcsi 150c0000.nvcsi: csi4_stream_init
[ 485.901311] nvcsi 150c0000.nvcsi: csi4_stream_config
[ 485.901321] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[ 485.901324] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 485.901329] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[ 486.901234] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 487.901225] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 488.901242] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 489.901274] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 490.901282] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 491.901287] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 492.901304] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 493.901302] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 494.901305] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 495.901334] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 496.901346] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 497.901351] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 498.901361] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 498.901924] ov5693 2-0036: ov5693_s_stream++
[ 498.901950] ov5693 2-0036: ov5693_s_stream–
[ 498.902562] nvcsi 150c0000.nvcsi: csi4_stop_streaming ports index=0, lanes=2
[ 498.902587] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 498.902609] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000002
[ 498.902629] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[ 498.902654] nvcsi 150c0000.nvcsi: csi4_cil_check_status 269
[ 498.905105] ov5693 2-0036: ov5693_power_off: power off

https://devtalk.nvidia.com/default/topic/1010558/v4l2-drivers-for-tegra-x2-v4l2-and-nvcamerasrc/

from above link, it looks like There is some problem in port binding in DT. if so how can I check
my /dev/video0 is correct one. and I have checked on scope MIPI signals are coming from FPGA. Anything else I am doing wrong?

P.S. I do not have i2c on my sensor. it has pre configured MIPI. and I have applied patches also
from below link:

https://devtalk.nvidia.com/default/topic/1007058/jetson-tx2/porting-tx1-camera-driver-to-kernel-4-4-15-pxl_sof-syncpt-timeout

Any Suggestion what I am doing wrong?

TIA.

hello atrivedi,

may i have your confirmation that you had config the sensor driver correctly?
below message shows it is a 2-lane sensor.
[ 485.901298] nvcsi 150c0000.nvcsi: csi4_start_streaming ports index=0, lanes=2

also, here’s debug tips for R28.1 TX2 for your reference.
https://elinux.org/Jetson_TX2/28.1_Camera_BringUp

@JerryChang,

Yes you are right, My sensor driver is not properly configured in csi4_fops.c where csi4_mipi_cal()
shows its configured for 2-Lane. Can you please provide me guideline to chane settings for 1-Lane mipi. especially what all registers I have to change?

hello atrivedi,

please refer to [Sensor Driver Programming Guide]
you’re able to find the description for the configuration.

bus-width: Bus width defines the number of CSI lanes connected to sensor.

Hello Jerry,

bus-width in my dts file is 1 only for 1-lane configuration. sensor driver parse_dt functions shows

  1. but in csi4_fops.c shows 2 lane in csi4_phy_config() function. I want to know what change I need to do.

TIA.

Hi,

Can you please provide me the detail where can I find timing diagram for TX2 MIPI CSI Lines?

hello atrivedi,

there’s also number of data lanes configuration in the sensor mode table,
please also check below 4-lane example, you should configure this too in your sensor device tree.
thanks

mode0 {/*mode IMX185_MODE_1920X1080_CROP_30FPS*/
    mclk_khz = "37125";
    <b>num_lanes = "4";</b>
    tegra_sinterface = "serial_a";

Hi Jerry,

You were right about bus-width property in dts, I forgot to change bus-width property of vi and nvcsi
node in my dts file. now my dmesg shows csi lane 1, but still I am getting errors in dmesg. below is my dmesg:

tegra-vi4 15700000.vi: master error
[ 750.624996] tegra-vi4 15700000.vi: master error
[ 750.625028] tegra-vi4 15700000.vi: master error
[ 750.625044] tegra-vi4 15700000.vi: master error
[ 750.625058] tegra-vi4 15700000.vi: master error
[ 750.625071] tegra-vi4 15700000.vi: master error
[ 750.625085] tegra-vi4 15700000.vi: master error
[ 750.625099] tegra-vi4 15700000.vi: master error
[ 750.625112] tegra-vi4 15700000.vi: master error
[ 750.625126] tegra-vi4 15700000.vi: master error
[ 750.625139] tegra-vi4 15700000.vi: master error
[ 750.625149] tegra-vi4 15700000.vi: master error
[ 750.625158] tegra-vi4 15700000.vi: master error
[ 750.625168] tegra-vi4 15700000.vi: master error
[ 750.625178] tegra-vi4 15700000.vi: master error
[ 750.625193] tegra-vi4 15700000.vi: master error
[ 750.625204] tegra-vi4 15700000.vi: master error
[ 750.625214] tegra-vi4 15700000.vi: master error
[ 750.625224] tegra-vi4 15700000.vi: master error
[ 750.625233] tegra-vi4 15700000.vi: master error
[ 750.625245] tegra-vi4 15700000.vi: master error
[ 750.625256] tegra-vi4 15700000.vi: master error
[ 750.625266] tegra-vi4 15700000.vi: master error
[ 750.625275] tegra-vi4 15700000.vi: master error
[ 750.625284] tegra-vi4 15700000.vi: master error
[ 750.625294] tegra-vi4 15700000.vi: master error
[ 750.625303] tegra-vi4 15700000.vi: master error
[ 750.625313] tegra-vi4 15700000.vi: master error
[ 750.625322] tegra-vi4 15700000.vi: master error
[ 750.625332] tegra-vi4 15700000.vi: master error
[ 750.625341] tegra-vi4 15700000.vi: master error
[ 750.625350] tegra-vi4 15700000.vi: master error
[ 750.625360] tegra-vi4 15700000.vi: master error
[ 750.625370] tegra-vi4 15700000.vi: master error
[ 750.625379] tegra-vi4 15700000.vi: master error
[ 750.625388] tegra-vi4 15700000.vi: master error
[ 750.625433] ov5693 2-0036: camera_common_g_fmt++
[ 750.625458] ov5693 2-0036: sensor_common_parse_control_props:gain_factor:property missing
[ 750.625465] ov5693 2-0036: sensor_common_parse_control_props:framerate_factor:property missing
[ 750.625471] ov5693 2-0036: sensor_common_parse_control_props:min_gain_val:property missing
[ 750.625478] ov5693 2-0036: sensor_common_parse_control_props:min_framerate:property missing
[ 750.625492] ov5693 2-0036: sensor_common_parse_control_props:gain_factor:property missing
[ 750.625496] ov5693 2-0036: sensor_common_parse_control_props:framerate_factor:property missing
[ 750.625501] ov5693 2-0036: sensor_common_parse_control_props:min_gain_val:property missing
[ 750.625508] ov5693 2-0036: sensor_common_parse_control_props:min_framerate:property missing
[ 750.625521] ov5693 2-0036: sensor_common_parse_control_props:gain_factor:property missing
[ 750.625526] ov5693 2-0036: sensor_common_parse_control_props:framerate_factor:property missing
[ 750.625531] ov5693 2-0036: sensor_common_parse_control_props:min_gain_val:property missing
[ 750.625537] ov5693 2-0036: sensor_common_parse_control_props:min_framerate:property missing
[ 750.625945] tegra-vi4 15700000.vi: Create Surface with imgW=640, imgH=480, memFmt=200
[ 750.626512] ov5693 2-0036: ov5693_s_stream++
[ 750.626516] ov5693 2-0036: ov5693_s_stream–
[ 750.627794] AT’s IR: in csi4_mipi_cal: 1
[ 750.627801] nvcsi 150c0000.nvcsi: csi port:0
[ 750.627804] lanes are 3145728
[ 750.629033] tegra_mipi_cal 3990000.mipical: Mipi cal timeout,val:9671, lanes:300000
[ 750.629045] tegra_mipi_cal 3990000.mipical: MIPI_CAL_CTRL 0x04 0x2a000010
[ 750.629051] tegra_mipi_cal 3990000.mipical: CIL_MIPI_CAL_STATUS 0x0c 0x00009671
[ 750.629057] tegra_mipi_cal 3990000.mipical: CIL_MIPI_CAL_STATUS_2 0x10 0x00000000
[ 750.629063] tegra_mipi_cal 3990000.mipical: CILA_MIPI_CAL_CONFIG 0x18 0x00200000
[ 750.629069] tegra_mipi_cal 3990000.mipical: CILB_MIPI_CAL_CONFIG 0x1c 0x00200000
[ 750.629074] tegra_mipi_cal 3990000.mipical: CILC_MIPI_CAL_CONFIG 0x20 0x00000000
[ 750.629079] tegra_mipi_cal 3990000.mipical: CILD_MIPI_CAL_CONFIG 0x24 0x00000000
[ 750.629087] tegra_mipi_cal 3990000.mipical: CILE_MIPI_CAL_CONFIG 0x28 0x00000000
[ 750.629098] tegra_mipi_cal 3990000.mipical: CILF_MIPI_CAL_CONFIG 0x2c 0x00000000
[ 750.629103] tegra_mipi_cal 3990000.mipical: DSIA_MIPI_CAL_CONFIG 0x3c 0x00000000
[ 750.629108] tegra_mipi_cal 3990000.mipical: DSIB_MIPI_CAL_CONFIG 0x40 0x00000000
[ 750.629114] tegra_mipi_cal 3990000.mipical: DSIC_MIPI_CAL_CONFIG 0x44 0x00000000
[ 750.629121] tegra_mipi_cal 3990000.mipical: DSID_MIPI_CAL_CONFIG 0x48 0x00000000
[ 750.629126] tegra_mipi_cal 3990000.mipical: MIPI_BIAS_PAD_CFG0 0x5c 0x00000000
[ 750.629132] tegra_mipi_cal 3990000.mipical: MIPI_BIAS_PAD_CFG1 0x60 0x00000000
[ 750.629140] tegra_mipi_cal 3990000.mipical: MIPI_BIAS_PAD_CFG2 0x64 0x00000000
[ 750.629145] tegra_mipi_cal 3990000.mipical: DSIA_MIPI_CAL_CONFIG_2 0x68 0x00000000
[ 750.629152] tegra_mipi_cal 3990000.mipical: DSIB_MIPI_CAL_CONFIG_2 0x6c 0x00000000
[ 750.629158] tegra_mipi_cal 3990000.mipical: DSIC_MIPI_CAL_CONFIG_2 0x74 0x00000000
[ 750.629164] tegra_mipi_cal 3990000.mipical: DSID_MIPI_CAL_CONFIG_2 0x78 0x00000000
[ 750.629172] nvcsi 150c0000.nvcsi: csi4_start_streaming ports index=0, lanes=1
[ 750.629175] nvcsi 150c0000.nvcsi: csi4_stream_init
[ 750.629184] nvcsi 150c0000.nvcsi: csi4_stream_config
[ 750.629191] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[ 750.629193] AT’s IR 0
[ 750.629197] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 750.629201] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[ 750.629206] csi_lanes 1
[ 751.629106] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 752.629102] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 753.629092] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 754.629095] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 755.629098] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 756.629111] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 757.629109] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 758.629118] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 758.629567] ov5693 2-0036: ov5693_s_stream++
[ 758.629594] ov5693 2-0036: ov5693_s_stream–
[ 758.630105] nvcsi 150c0000.nvcsi: csi4_stop_streaming ports index=0, lanes=1
[ 758.630142] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 758.630164] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000001
[ 758.630183] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[ 758.630209] nvcsi 150c0000.nvcsi: csi4_cil_check_status 272
[ 758.632795] ov5693 2-0036: ov5693_power_off: power off
[ 758.634980] ov5693 2-0036: camera_common_dpd_enable: csi 0
[ 758.635004] ov5693 2-0036: camera_common_mclk_disable: disable MCLK.

hello atrivedi,

FYI, here are some debug tips about camera bringup for your reference.
thanks

https://elinux.org/Jetson_TX2/28.1_Camera_BringUp