Now TX2 CSI chrome sensor driver transmit color video data，if sensor resolution is 1920X1080 in RGGB mode,there are 1920X480 R data,1920X480 B data and 1920X960 G data transmit from sensor to tx2,and then isp in tx2 make bayer interpolation,then there are 1920X1080 RGB data,Do I have an exact understanding?
If right,My sensor is monochrome sensor,use method in the above can’t get right video,So what am I supposed to do?
hello liliasojd,
that’s not correct.
ISP handle sensor bayer formats by having process. such as, demosaic, black level, len shading, tone map…etc.
then, ISP output fill-in buffers with YUV formats.
we don’t support ISP to directly output RGB planar formats,
so far (l4t-r32.2), we also don’t support monochrome sensor as ISP input sensors.
however,
according to Camera Architecture Stack, you could also working with v4l2src pipeline.
you may check below kernel drivers, please have implementation to extend the support formats.
$l4t-r32.2/kernel_src/kernel/nvidia/drivers/media/platform/tegra/camera/camera_common.c
$l4t-r32.2/kernel_src/kernel/nvidia/drivers/media/platform/tegra/camera/sensor_common.c
suggest you also check similar discussion thread, Topic 1036708 for reference.
thanks
Thank you for your reply, under your suggestion I read Camera Architecture Stack.
In the Camera Architecture Stack,Video data from sensor, goto V4l2 Device Driver frist.In userspace we can get the data from tegra Driver or V4l Mediacontroller,But if get data from V4l MediaController we can skip ISP.
So if I use v4l2-ctl -d /dev/video0 --set-fmt-video=width=1920,height=1080,pixelformat=RG10 --set-ctrl bypass_mode=0 --stream-mmap --stream-count=10 --stream-to=test.raw .File test.raw is original sensor data without bayer interpolation?
If not,how I can skip the ISP.
hello liliasojd,
according to Camera Architecture Stack, you can consider bypass [Camera Core] software block as ISP skipped.
both v4l2-ctl and v4l2src were accessing your camera device with low-level VI drivers.
suggest you could also check TX2’s VI kernel sources for reference,
for example,
$l4t-r32.2/kernel_src/kernel/nvidia/drivers/media/platform/tegra/camera/vi/vi4_fops.c
I modify the drivers ov5693.c,so TX2 can grab data from FPGA by CSI.
Then use FPGA send video pixel data 0x00 0x10 0x20 0x30 0x40…0xF0 repeatedly and continuously.
Use v4l2-ctl -d /dev/video0 --set-fmt-video=width=1920,height=1080,pixelformat=RG10 --set-ctrl bypass_mode=0 --stream-mmap --stream-count=1 --stream-to=test.raw To grab a frame data.
The size of raw file is 4147200=192010802*8,it looks like a pixel is 16bit.
SoI use hexdump -C -n 1000 test.raw to view the raw data as follow
00000000 00 00 01 04 02 08 03 0c 02 08 03 0c 04 10 05 14 |................|
00000010 06 18 07 1c 06 18 07 1c 08 20 09 24 0a 28 0b 2c |......... .$.(.,|
00000020 0a 28 0b 2c 0c 30 0d 34 0e 38 0f 3c 0e 38 0f 3c |.(.,.0.4.8.<.8.<|
00000030 00 00 01 04 02 08 03 0c 02 08 03 0c 04 10 05 14 |................|
00000040 06 18 07 1c 06 18 07 1c 08 20 09 24 0a 28 0b 2c |......... .$.(.,|
00000050 0a 28 0b 2c 0c 30 0d 34 0e 38 0f 3c 0e 38 0f 3c |.(.,.0.4.8.<.8.<|
00000060 00 00 01 04 02 08 03 0c 02 08 03 0c 04 10 05 14 |................|
00000070 06 18 07 1c 06 18 07 1c 08 20 09 24 0a 28 0b 2c |......... .$.(.,|
00000080 0a 28 0b 2c 0c 30 0d 34 0e 38 0f 3c 0e 38 0f 3c |.(.,.0.4.8.<.8.<|
00000090 00 00 01 04 02 08 03 0c 02 08 03 0c 04 10 05 14 |................|
000000a0 06 18 07 1c 06 18 07 1c 08 20 09 24 0a 28 0b 2c |......... .$.(.,|
000000b0 0a 28 0b 2c 0c 30 0d 34 0e 38 0f 3c 0e 38 0f 3c |.(.,.0.4.8.<.8.<|
000000c0 00 00 01 04 02 08 03 0c 02 08 03 0c 04 10 05 14 |................|
000000d0 06 18 07 1c 06 18 07 1c 08 20 09 24 0a 28 0b 2c |......... .$.(.,|
000000e0 0a 28 0b 2c 0c 30 0d 34 0e 38 0f 3c 0e 38 0f 3c |.(.,.0.4.8.<.8.<|
000000f0 00 00 01 04 02 08 03 0c 02 08 03 0c 04 10 05 14 |................|
00000100 06 18 07 1c 06 18 07 1c 08 20 09 24 0a 28 0b 2c |......... .$.(.,|
00000110 0a 28 0b 2c 0c 30 0d 34 0e 38 0f 3c 0e 38 0f 3c |.(.,.0.4.8.<.8.<|
00000120 00 00 01 04 02 08 03 0c 02 08 03 0c 04 10 05 14 |................|
The data precies match the TX2 TRM NVIDIA Parker Series SoC 27.10.6 RAW Memory Formats for RAW10, RAW12 and RAW14", where RAW10 pixels are shown written in memory as
[ 0 | 0 | D9| D8| D7| D6| D5| D4| D3| D2| D1| D0| D9| D8| D7| D6]
But the problem is repeats two pixels after four pixels.I don’t know what happened.
hello liliasojd,
- please review your bytes-pre-line settings, you may check it with below formula,
bytes-per-line = (frame width * bits per pixel / 8)
- you may also refer to the code-snippet in Topic 1050604, to add function to set bytesperline.
thanks
Thank you for your reply.
I think you may be misled by me.
Actually the data I sent use FPGA by csi is 10bit ,Just Becase I only use 8bit,so low 2bit always send 0.
And I think my bytes-per-line is right.If not TX2 should be received nothing because of the size of receive and send is different.
And the most important thing is the pixel value of recieved is match pixel value of send.
My image size is 1920X1080
I accidentally changed the CSI transmission frequency of the FPGA side from the original 900Mhz to 1200Mhz today, and the image received by the TX2 is completely normal. And regardless of the transmission frequency of the CSI, the image is normal in the Y direction. At 900Mhz, the image looks like the 1280 pixels in front of the X direction are interpolated 1.5 times, the last 720 pixels are lost, and the line length is still 1920. Of course, if the frequency is changed to 600Mhz, the image looks like the 960 pixels in front of the X direction are interpolated 1.5 times, the last 960 pixels are lost, and the line length is still 1920.
Why？
hello liliasojd,
- according to Sensor Software Driver Programming Guide, the sensor pixel clock must correct.
due to camera software stack uses the sensor pixel clock to calculate the exposure, frame rate, and also avoid potential issues. - your sensor device tree settings (i.e. active_w and active_h) also important for the camera stack to allocate the buffer for active pixels.
thanks
according to Sensor Software Driver Programming Guide, pixel_clk_hz = sensor data rate per lane (Mbps) * number of lanes / bits per pixel,My sensor data rate per lane (Mbps) is 800Mhz,in 2 lane mode ,and 10 bits per pixel ,so my pix_clk_hz = “160000000” is right.but In fact,the sensor data rate per lane should set to 1200Mhz,then I can get the right Image
hello liliasojd,
we usually use these three different formulas to calculate the sensor pixel clock.
suggest you may also contact with your sensor vendor to ensure the settings of data-per-lane.
thanks
My Sensor is a FPGA，CSI signal generated by XILINX FPGA CSI TX，And I sampled the signal with an oscilloscope.
hello liliasojd,
got it. so you’re able to make the sensor streaming working with data-per-lane=1200MHz.
anything else in this topic still waiting for clarification.
thanks
According to your statement, I changed the DTC file, but it seems that there is no change. In the modification of the CSI pixel clock, do I need to change other files?
According to your statement, I changed the DTC and ov5693.c file, but it seems that there is no change. In the modification of the CSI pixel clock, do I need to change other files?
//#define OV5693_DEFAULT_PIXEL_CLOCK (160)
#define OV5693_DEFAULT_PIXEL_CLOCK (100)
//#define OV5693_DEFAULT_CLK_FREQ 24000000
#define OV5693_DEFAULT_CLK_FREQ 15000000
mode0 { // OV5693_MODE_2592X1944
mclk_khz = "15000";
num_lanes = "2";
tegra_sinterface = "serial_a";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "2592";
active_h = "1944";
pixel_t = "bayer_bggr";
readout_orientation = "90";
line_length = "2688";
inherent_gain = "1";
mclk_multiplier = "6.67";
pix_clk_hz = "100000000";
min_gain_val = "1.0";
max_gain_val = "16";
min_hdr_ratio = "1";
max_hdr_ratio = "64";
min_framerate = "1.816577";
max_framerate = "30";
min_exp_time = "34";
max_exp_time = "550385";
};
hello liliasojd,
please update your device tree property settings,
pixel_clk_hz = 1200 (data rate per-lane in Mbps) * 2 (number of lanes) / 10 (bits-per-pixel) = 240000000 Hz
you’ll need to compile device tree again and update the kernel-dtb partition to take effect.
for example,
$ cp output.dtb $OUT/Linux_for_Tegra/kernel/dtb/tegra186-quill-p3310-1000-c03-00-base.dtb
$ sudo ./flash.sh -r -k kernel-dtb jetson-tx2 mmcblk0p1
Besides,
we also have kernel driver update to deprecate the pixel_t property.
please replace it with the following properties instead. mode_type, csi_pixel_bit_depth, and pixel_phase.
thanks
I use sudo ./flash.sh jetson-tx2 mmcblk0p1 update the whole flash.
In fact, because of the CSI-D built by the resistance bridge I used, the frequency of CSI can’t work at 1200Mhz for a long time, so I want to lower the frequency.
I have so many questions
1, is not it is not necessary to change ov5693.c, directly change the DTB file just fine
2, I use 2-lane, then pixel clock is multiplied by 2 for each lane, or not
Ok，Let me reorganize the process of modification.
I try use TX2 grad data from XILINX FPGA CSI-TX。
Change DTB file close plugin maneger and use main platform device tree file tegra186-quill-camera-modules.dtsi like this and I try ov5693 module work fine.I use 4 2-lane csi.
/ {
host1x {
vi@15700000 {
num-channels = <4>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
status = "okay";
e7035_vi_in0: endpoint {
csi-port = <0>;
bus-width = <2>;
status = "okay";
remote-endpoint = <&e7035_csi_out0>;
};
};
port@1 {
reg = <1>;
status = "okay";
e7035_vi_in1: endpoint {
csi-port = <1>;
bus-width = <2>;
status = "okay";
remote-endpoint = <&e7035_csi_out1>;
};
};
port@2 {
reg = <2>;
status = "okay";
e7035_vi_in2: endpoint {
csi-port = <2>;
bus-width = <2>;
status = "okay";
remote-endpoint = <&e7035_csi_out2>;
};
};
port@3 {
reg = <3>;
status = "okay";
e7035_vi_in3: endpoint {
csi-port = <3>;
bus-width = <2>;
status = "okay";
remote-endpoint = <&e7035_csi_out3>;
};
};
};
};
nvcsi@150c0000 {
num-channels = <4>;
/*#address-cells = <1>;*/
/*#size-cells = <0>;*/
channel@0 {
reg = <0>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
status = "okay";
e7035_csi_in0: endpoint@0 {
csi-port = <0>;
bus-width = <2>;
status = "okay";
remote-endpoint = <&e7035_ov5693_out0>;
};
};
port@1 {
reg = <1>;
status = "okay";
e7035_csi_out0: endpoint@1 {
status = "okay";
remote-endpoint = <&e7035_vi_in0>;
};
};
};
};
channel@1 {
reg = <1>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
status = "okay";
e7035_csi_in1: endpoint@2 {
csi-port = <1>;
bus-width = <2>;
status = "okay";
remote-endpoint = <&e7035_ov5693_out1>;
};
};
port@1 {
reg = <1>;
status = "okay";
e7035_csi_out1: endpoint@3 {
status = "okay";
remote-endpoint = <&e7035_vi_in1>;
};
};
};
};
channel@2 {
reg = <2>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
status = "okay";
e7035_csi_in2: endpoint@4 {
csi-port = <2>;
bus-width = <2>;
status = "okay";
remote-endpoint = <&e7035_ov5693_out2>;
};
};
port@1 {
reg = <1>;
status = "okay";
e7035_csi_out2: endpoint@5 {
status = "okay";
remote-endpoint = <&e7035_vi_in2>;
};
};
};
};
channel@3 {
reg = <3>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
status = "okay";
e7035_csi_in3: endpoint@6 {
csi-port = <3>;
bus-width = <2>;
status = "okay";
remote-endpoint = <&e7035_ov5693_out3>;
};
};
port@1 {
reg = <1>;
status = "okay";
e7035_csi_out3: endpoint@7 {
status = "okay";
remote-endpoint = <&e7035_vi_in3>;
};
};
};
};
};
};
i2c@3180000 {
status = "okay";
ov5693_a@38 {
compatible = "nvidia,ov5693";
/* I2C device address */
reg = <0x38>;
status = "okay";
/* V4L2 device node location */
devnode = "video0";
/* Physical dimensions of sensor */
physical_w = "3.674";
physical_h = "2.738";
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
avdd-reg = "vana";
iovdd-reg = "vif";
/* Sensor output flip settings */
vertical-flip = "true";
/**
* A modeX node is required to support v4l2 driver
* implementation with NVIDIA camera software stack
*
* mclk_khz = "";
* Standard MIPI driving clock, typically 24MHz
*
* num_lanes = "";
* Number of lane channels sensor is programmed to output
*
* tegra_sinterface = "";
* The base tegra serial interface lanes are connected to
*
* discontinuous_clk = "";
* The sensor is programmed to use a discontinuous clock on MIPI lanes
*
* dpcm_enable = "true";
* The sensor is programmed to use a DPCM modes
*
* cil_settletime = "";
* MIPI lane settle time value.
* A "0" value attempts to autocalibrate based on mclk_multiplier
*
*
*
*
* active_w = "";
* Pixel active region width
*
* active_h = "";
* Pixel active region height
*
* pixel_t = "";
* The sensor readout pixel pattern
*
* readout_orientation = "0";
* Based on camera module orientation.
* Only change readout_orientation if you specifically
* Program a different readout order for this mode
*
* line_length = "";
* Pixel line length (width) for sensor mode.
* This is used to calibrate features in our camera stack.
*
* mclk_multiplier = "";
* Multiplier to MCLK to help time hardware capture sequence
* TODO: Assign to PLL_Multiplier as well until fixed in core
*
* pix_clk_hz = "";
* Sensor pixel clock used for calculations like exposure and framerate
*
*
*
*
* inherent_gain = "";
* Gain obtained inherently from mode (ie. pixel binning)
*
* min_gain_val = ""; (floor to 6 decimal places)
* max_gain_val = ""; (floor to 6 decimal places)
* Gain limits for mode
*
* min_exp_time = ""; (ceil to integer)
* max_exp_time = ""; (ceil to integer)
* Exposure Time limits for mode (us)
*
*
* min_hdr_ratio = "";
* max_hdr_ratio = "";
* HDR Ratio limits for mode
*
* min_framerate = "";
* max_framerate = "";
* Framerate limits for mode (fps)
*/
mode0 { // OV5693_MODE_2592X1944
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_a";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "2592";
active_h = "1944";
pixel_t = "bayer_bggr";
readout_orientation = "90";
line_length = "2688";
inherent_gain = "1";
mclk_multiplier = "6.67";
pix_clk_hz = "160000000";
min_gain_val = "1.0";
max_gain_val = "16";
min_hdr_ratio = "1";
max_hdr_ratio = "64";
min_framerate = "1.816577";
max_framerate = "30";
min_exp_time = "34";
max_exp_time = "550385";
};
mode1 { //OV5693_MODE_2592X1458
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_a";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "2592";
active_h = "1458";
pixel_t = "bayer_bggr";
readout_orientation = "90";
line_length = "2688";
inherent_gain = "1";
mclk_multiplier = "6.67";
pix_clk_hz = "160000000";
min_gain_val = "1.0";
max_gain_val = "16";
min_hdr_ratio = "1";
max_hdr_ratio = "64";
min_framerate = "1.816577";
max_framerate = "30";
min_exp_time = "34";
max_exp_time = "550385";
};
mode2 { //OV5693_MODE_1280X720
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_a";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "1280";
active_h = "720";
pixel_t = "bayer_bggr";
readout_orientation = "90";
line_length = "1752";
inherent_gain = "1";
mclk_multiplier = "6.67";
pix_clk_hz = "160000000";
min_gain_val = "1.0";
max_gain_val = "16";
min_hdr_ratio = "1";
max_hdr_ratio = "64";
min_framerate = "2.787078";
max_framerate = "120";
min_exp_time = "22";
max_exp_time = "358733";
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
status = "okay";
e7035_ov5693_out0: endpoint {
csi-port = <0>;
bus-width = <2>;
status = "okay";
remote-endpoint = <&e7035_csi_in0>;
};
};
};
};
ov5693_b@37 {
compatible = "nvidia,ov5693";
/* I2C device address */
reg = <0x37>;
status = "okay";
/* V4L2 device node location */
devnode = "video1";
/* Physical dimensions of sensor */
physical_w = "3.674";
physical_h = "2.738";
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
avdd-reg = "vana";
iovdd-reg = "vif";
/* Sensor output flip settings */
vertical-flip = "true";
/**
* A modeX node is required to support v4l2 driver
* implementation with NVIDIA camera software stack
*
* mclk_khz = "";
* Standard MIPI driving clock, typically 24MHz
*
* num_lanes = "";
* Number of lane channels sensor is programmed to output
*
* tegra_sinterface = "";
* The base tegra serial interface lanes are connected to
*
* discontinuous_clk = "";
* The sensor is programmed to use a discontinuous clock on MIPI lanes
*
* dpcm_enable = "true";
* The sensor is programmed to use a DPCM modes
*
* cil_settletime = "";
* MIPI lane settle time value.
* A "0" value attempts to autocalibrate based on mclk_multiplier
*
*
*
*
* active_w = "";
* Pixel active region width
*
* active_h = "";
* Pixel active region height
*
* pixel_t = "";
* The sensor readout pixel pattern
*
* readout_orientation = "0";
* Based on camera module orientation.
* Only change readout_orientation if you specifically
* Program a different readout order for this mode
*
* line_length = "";
* Pixel line length (width) for sensor mode.
* This is used to calibrate features in our camera stack.
*
* mclk_multiplier = "";
* Multiplier to MCLK to help time hardware capture sequence
* TODO: Assign to PLL_Multiplier as well until fixed in core
*
* pix_clk_hz = "";
* Sensor pixel clock used for calculations like exposure and framerate
*
*
*
*
* inherent_gain = "";
* Gain obtained inherently from mode (ie. pixel binning)
*
* min_gain_val = ""; (floor to 6 decimal places)
* max_gain_val = ""; (floor to 6 decimal places)
* Gain limits for mode
*
* min_exp_time = ""; (ceil to integer)
* max_exp_time = ""; (ceil to integer)
* Exposure Time limits for mode (us)
*
*
* min_hdr_ratio = "";
* max_hdr_ratio = "";
* HDR Ratio limits for mode
*
* min_framerate = "";
* max_framerate = "";
* Framerate limits for mode (fps)
*/
mode0 { // OV5693_MODE_2592X1944
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_b";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "2592";
active_h = "1944";
pixel_t = "bayer_bggr";
readout_orientation = "90";
line_length = "2688";
inherent_gain = "1";
mclk_multiplier = "6.67";
pix_clk_hz = "160000000";
min_gain_val = "1.0";
max_gain_val = "16";
min_hdr_ratio = "1";
max_hdr_ratio = "64";
min_framerate = "1.816577";
max_framerate = "30";
min_exp_time = "34";
max_exp_time = "550385";
};
mode1 { //OV5693_MODE_2592X1458
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_b";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "2592";
active_h = "1458";
pixel_t = "bayer_bggr";
readout_orientation = "90";
line_length = "2688";
inherent_gain = "1";
mclk_multiplier = "6.67";
pix_clk_hz = "160000000";
min_gain_val = "1.0";
max_gain_val = "16";
min_hdr_ratio = "1";
max_hdr_ratio = "64";
min_framerate = "1.816577";
max_framerate = "30";
min_exp_time = "34";
max_exp_time = "550385";
};
mode2 { //OV5693_MODE_1280X720
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_b";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "1280";
active_h = "720";
pixel_t = "bayer_bggr";
readout_orientation = "90";
line_length = "1752";
inherent_gain = "1";
mclk_multiplier = "6.67";
pix_clk_hz = "160000000";
min_gain_val = "1.0";
max_gain_val = "16";
min_hdr_ratio = "1";
max_hdr_ratio = "64";
min_framerate = "2.787078";
max_framerate = "120";
min_exp_time = "22";
max_exp_time = "358733";
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
status = "okay";
e7035_ov5693_out1: endpoint {
csi-port = <1>;
bus-width = <2>;
status = "okay";
remote-endpoint = <&e7035_csi_in1>;
};
};
};
};
ov5693_c@36 {
compatible = "nvidia,ov5693";
/* I2C device address */
reg = <0x36>;
status = "okay";
/* V4L2 device node location */
devnode = "video2";
/* Physical dimensions of sensor */
physical_w = "3.674";
physical_h = "2.738";
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
avdd-reg = "vana";
iovdd-reg = "vif";
/* Sensor output flip settings */
vertical-flip = "true";
/**
* A modeX node is required to support v4l2 driver
* implementation with NVIDIA camera software stack
*
* mclk_khz = "";
* Standard MIPI driving clock, typically 24MHz
*
* num_lanes = "";
* Number of lane channels sensor is programmed to output
*
* tegra_sinterface = "";
* The base tegra serial interface lanes are connected to
*
* discontinuous_clk = "";
* The sensor is programmed to use a discontinuous clock on MIPI lanes
*
* dpcm_enable = "true";
* The sensor is programmed to use a DPCM modes
*
* cil_settletime = "";
* MIPI lane settle time value.
* A "0" value attempts to autocalibrate based on mclk_multiplier
*
*
*
*
* active_w = "";
* Pixel active region width
*
* active_h = "";
* Pixel active region height
*
* pixel_t = "";
* The sensor readout pixel pattern
*
* readout_orientation = "0";
* Based on camera module orientation.
* Only change readout_orientation if you specifically
* Program a different readout order for this mode
*
* line_length = "";
* Pixel line length (width) for sensor mode.
* This is used to calibrate features in our camera stack.
*
* mclk_multiplier = "";
* Multiplier to MCLK to help time hardware capture sequence
* TODO: Assign to PLL_Multiplier as well until fixed in core
*
* pix_clk_hz = "";
* Sensor pixel clock used for calculations like exposure and framerate
*
*
*
*
* inherent_gain = "";
* Gain obtained inherently from mode (ie. pixel binning)
*
* min_gain_val = ""; (floor to 6 decimal places)
* max_gain_val = ""; (floor to 6 decimal places)
* Gain limits for mode
*
* min_exp_time = ""; (ceil to integer)
* max_exp_time = ""; (ceil to integer)
* Exposure Time limits for mode (us)
*
*
* min_hdr_ratio = "";
* max_hdr_ratio = "";
* HDR Ratio limits for mode
*
* min_framerate = "";
* max_framerate = "";
* Framerate limits for mode (fps)
*/
mode0 { // OV5693_MODE_2592X1944
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_c";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "2592";
active_h = "1944";
pixel_t = "bayer_bggr";
readout_orientation = "90";
line_length = "2688";
inherent_gain = "1";
mclk_multiplier = "6.67";
pix_clk_hz = "160000000";
min_gain_val = "1.0";
max_gain_val = "16";
min_hdr_ratio = "1";
max_hdr_ratio = "64";
min_framerate = "1.816577";
max_framerate = "30";
min_exp_time = "34";
max_exp_time = "550385";
};
mode1 { //OV5693_MODE_2592X1458
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_c";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "2592";
active_h = "1458";
pixel_t = "bayer_bggr";
readout_orientation = "90";
line_length = "2688";
inherent_gain = "1";
mclk_multiplier = "6.67";
pix_clk_hz = "160000000";
min_gain_val = "1.0";
max_gain_val = "16";
min_hdr_ratio = "1";
max_hdr_ratio = "64";
min_framerate = "1.816577";
max_framerate = "30";
min_exp_time = "34";
max_exp_time = "550385";
};
mode2 { //OV5693_MODE_1280X720
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_c";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "1280";
active_h = "720";
pixel_t = "bayer_bggr";
readout_orientation = "90";
line_length = "1752";
inherent_gain = "1";
mclk_multiplier = "6.67";
pix_clk_hz = "160000000";
min_gain_val = "1.0";
max_gain_val = "16";
min_hdr_ratio = "1";
max_hdr_ratio = "64";
min_framerate = "2.787078";
max_framerate = "120";
min_exp_time = "22";
max_exp_time = "358733";
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
status = "okay";
e7035_ov5693_out2: endpoint {
csi-port = <2>;
bus-width = <2>;
status = "okay";
remote-endpoint = <&e7035_csi_in2>;
};
};
};
};
ov5693_d@35 {
compatible = "nvidia,ov5693";
/* I2C device address */
reg = <0x35>;
status = "okay";
/* V4L2 device node location */
devnode = "video3";
/* Physical dimensions of sensor */
physical_w = "3.674";
physical_h = "2.738";
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
avdd-reg = "vana";
iovdd-reg = "vif";
/* Sensor output flip settings */
vertical-flip = "true";
/**
* A modeX node is required to support v4l2 driver
* implementation with NVIDIA camera software stack
*
* mclk_khz = "";
* Standard MIPI driving clock, typically 24MHz
*
* num_lanes = "";
* Number of lane channels sensor is programmed to output
*
* tegra_sinterface = "";
* The base tegra serial interface lanes are connected to
*
* discontinuous_clk = "";
* The sensor is programmed to use a discontinuous clock on MIPI lanes
*
* dpcm_enable = "true";
* The sensor is programmed to use a DPCM modes
*
* cil_settletime = "";
* MIPI lane settle time value.
* A "0" value attempts to autocalibrate based on mclk_multiplier
*
*
*
*
* active_w = "";
* Pixel active region width
*
* active_h = "";
* Pixel active region height
*
* pixel_t = "";
* The sensor readout pixel pattern
*
* readout_orientation = "0";
* Based on camera module orientation.
* Only change readout_orientation if you specifically
* Program a different readout order for this mode
*
* line_length = "";
* Pixel line length (width) for sensor mode.
* This is used to calibrate features in our camera stack.
*
* mclk_multiplier = "";
* Multiplier to MCLK to help time hardware capture sequence
* TODO: Assign to PLL_Multiplier as well until fixed in core
*
* pix_clk_hz = "";
* Sensor pixel clock used for calculations like exposure and framerate
*
*
*
*
* inherent_gain = "";
* Gain obtained inherently from mode (ie. pixel binning)
*
* min_gain_val = ""; (floor to 6 decimal places)
* max_gain_val = ""; (floor to 6 decimal places)
* Gain limits for mode
*
* min_exp_time = ""; (ceil to integer)
* max_exp_time = ""; (ceil to integer)
* Exposure Time limits for mode (us)
*
*
* min_hdr_ratio = "";
* max_hdr_ratio = "";
* HDR Ratio limits for mode
*
* min_framerate = "";
* max_framerate = "";
* Framerate limits for mode (fps)
*/
mode0 { // OV5693_MODE_2592X1944
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_d";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "2592";
active_h = "1944";
pixel_t = "bayer_bggr";
readout_orientation = "90";
line_length = "2688";
inherent_gain = "1";
mclk_multiplier = "6.67";
pix_clk_hz = "160000000";
min_gain_val = "1.0";
max_gain_val = "16";
min_hdr_ratio = "1";
max_hdr_ratio = "64";
min_framerate = "1.816577";
max_framerate = "30";
min_exp_time = "34";
max_exp_time = "550385";
};
mode1 { //OV5693_MODE_2592X1458
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_d";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "2592";
active_h = "1458";
pixel_t = "bayer_bggr";
readout_orientation = "90";
line_length = "2688";
inherent_gain = "1";
mclk_multiplier = "6.67";
pix_clk_hz = "160000000";
min_gain_val = "1.0";
max_gain_val = "16";
min_hdr_ratio = "1";
max_hdr_ratio = "64";
min_framerate = "1.816577";
max_framerate = "30";
min_exp_time = "34";
max_exp_time = "550385";
};
mode2 { //OV5693_MODE_1280X720
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_d";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "1280";
active_h = "720";
pixel_t = "bayer_bggr";
readout_orientation = "90";
line_length = "1752";
inherent_gain = "1";
mclk_multiplier = "6.67";
pix_clk_hz = "160000000";
min_gain_val = "1.0";
max_gain_val = "16";
min_hdr_ratio = "1";
max_hdr_ratio = "64";
min_framerate = "2.787078";
max_framerate = "120";
min_exp_time = "22";
max_exp_time = "358733";
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
status = "okay";
e7035_ov5693_out3: endpoint {
csi-port = <3>;
bus-width = <2>;
status = "okay";
remote-endpoint = <&e7035_csi_in3>;
};
};
};
};
};
e7035_lens_ov5693@P5V27C {
min_focus_distance = "0.0";
hyper_focal = "0.0";
focal_length = "2.67";
f_number = "2.0";
aperture = "2.0";
};
tegra-camera-platform {
compatible = "nvidia, tegra-camera-platform";
/**
* Physical settings to calculate max ISO BW
*
* num_csi_lanes = <>;
* Total number of CSI lanes when all cameras are active
*
* max_lane_speed = <>;
* Max lane speed in Kbit/s
*
* min_bits_per_pixel = <>;
* Min bits per pixel
*
* vi_peak_byte_per_pixel = <>;
* Max byte per pixel for the VI ISO case
*
* vi_bw_margin_pct = <>;
* Vi bandwidth margin in percentage
*
* max_pixel_rate = <>;
* Max pixel rate in Kpixel/s for the ISP ISO case
*
* isp_peak_byte_per_pixel = <>;
* Max byte per pixel for the ISP ISO case
*
* isp_bw_margin_pct = <>;
* Isp bandwidth margin in percentage
*/
num_csi_lanes = <8>;
max_lane_speed = <1500000>;
min_bits_per_pixel = <10>;
vi_peak_byte_per_pixel = <2>;
vi_bw_margin_pct = <25>;
max_pixel_rate = <160000>;
isp_peak_byte_per_pixel = <5>;
isp_bw_margin_pct = <25>;
/**
* The general guideline for naming badge_info contains 3 parts, and is as follows,
* The first part is the camera_board_id for the module; if the module is in a FFD
* platform, then use the platform name for this part.
* The second part contains the position of the module, ex. “rear” or “front”.
* The third part contains the last 6 characters of a part number which is found
* in the module's specsheet from the vender.
*/
modules {
module0 {
badge = "e7035_bottom_P5V27C";
position = "topleft";
orientation = "1";
status = "okay";
drivernode0 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_sensor";
/* Driver v4l2 device name */
devname = "ov5693 2-0038";
/* Declare the device-tree hierarchy to driver instance */
proc-device-tree = "/proc/device-tree/i2c@3180000/ov5693_a@38";
};
drivernode1 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_lens";
proc-device-tree = "/proc/device-tree/e7035_lens_ov5693@P5V27C/";
};
};
module1 {
badge = "e7035_bottom_P5V27C";
position = "top";
orientation = "1";
status = "okay";
drivernode0 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_sensor";
/* Driver v4l2 device name */
devname = "ov5693 2-0037";
/* Declare the device-tree hierarchy to driver instance */
proc-device-tree = "/proc/device-tree/i2c@3180000/ov5693_b@37";
};
drivernode1 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_lens";
proc-device-tree = "/proc/device-tree/e7035_lens_ov5693@P5V27C/";
};
};
module2 {
badge = "e7035_bottom_P5V27C";
position = "bottom";
orientation = "1";
status = "okay";
drivernode0 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_sensor";
/* Driver v4l2 device name */
devname = "ov5693 2-0036";
/* Declare the device-tree hierarchy to driver instance */
proc-device-tree = "/proc/device-tree/i2c@3180000/ov5693_c@36";
};
drivernode1 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_lens";
proc-device-tree = "/proc/device-tree/e7035_lens_ov5693@P5V27C/";
};
};
module3 {
badge = "e7035_bottom_P5V27C";
position = "topright";
orientation = "1";
status = "okay";
drivernode0 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_sensor";
/* Driver v4l2 device name */
devname = "ov5693 2-0035";
/* Declare the device-tree hierarchy to driver instance */
proc-device-tree = "/proc/device-tree/i2c@3180000/ov5693_d@35";
};
drivernode1 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_lens";
proc-device-tree = "/proc/device-tree/e7035_lens_ov5693@P5V27C/";
};
};
};
};
};
Then I modify OV5693.c,skip some OTP fuction,so kernel can load the driver.
I use the ./v4l2-ctl -d /dev/video0 --set-fmt-video=width=1920,height=1080,pixelformat=BG10 --set-ctrl bypass_mode=0 --stream-mmap --stream-count=1 --stream-to=test0.raw
I can get a Image,and that look almost right，Except for being enlarged in the X direction.
As you can see from the DTB file, I actually didn’t define the resolution of 1920*1080, but when I used ./v4l2-ctl --all,
default Width/Height is 1920/1080
nvidia@tegra-ubuntu:~/v4l-utils-1.12.6/utils/v4l2-ctl$ ./v4l2-ctl --all
Driver Info (not using libv4l2):
Driver name : tegra-video
Card type : vi-output, ov5693 2-0038
Bus info : platform:15700000.vi:0
Driver version: 4.4.38
Capabilities : 0x84200001
Video Capture
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04200001
Video Capture
Streaming
Extended Pix Format
Priority: 2
Video input : 0 (Camera 0: no power)
Format Video Capture:
Width/Height : 1920/1080
Pixel Format : 'BG10'
Field : None
Bytes per Line : 3840
Size Image : 4147200
Colorspace : sRGB
Transfer Function : Default
YCbCr/HSV Encoding: Default
Quantization : Default
Flags :
Camera Controls
frame_length (int) : min=0 max=32767 step=1 default=1984 value=1984 flags=slider
coarse_time (int) : min=2 max=32761 step=1 default=1978 value=1978 flags=slider
coarse_time_short (int) : min=2 max=32761 step=1 default=1978 value=1978 flags=slider
group_hold (intmenu): min=0 max=1 default=0 value=0
hdr_enable (intmenu): min=0 max=1 default=0 value=0
otp_data (str) : min=0 max=1024 step=2 value='00e904e6c1ffffff07209a000000000000000000000000000200000000000000d8470001c0ffffff00e904e6c1ffffff08c5c200c0ffffffc8ddc200c0ffffff008307e6c1ffffff5cf97800c0fffffff079e4ecc1ffffffc0f97800c0fffffff079e4ecc1ffffff1cfa7800c0ffffff307ae4ecc1ffffffd0f47800c0ffffff01000000000000000100000000000000307ae4ecc1ffffffdcf47800c0ffffff307ae4ecc1fffffffcf47800c0ffffff107be4ecc1ffffff08f77800c0ffffffe06d3001c0ffffff00000000000000000000000000000000584032ecc1ffffff000000000000000000c0c200c0ffffffc04632ecc1ffffffeaffffff0000000018c404e6c1ffffffe06d3001c0ffffff11000000000000000000000000000000d07ae4ecc1ffffff04091c00c0ffffff004e61f6c1ffffff0040e4ecc1ffffff008307e6c1ffffff83df000000000000607be4ecc1ffffff10935700c0ffffff184032ecc1ffffff20c446ebc1ffffff407be4ecc1fffffff4e57800c0ffffff010000000000000000e804e6c1ffffff000000000000000000e804e6c1ffffff884032ecc1ffffff2ce57800c0ffffff407be4ecc1ffffff14e67800c0ffffff807be4ecc1ffffffacd97700c0ffffff184032ecc1ffffff20c446ebc1ffffff584032ecc1ffffff0000000000000000606e3001c0ffffff00c0c200c0ffffff' flags=read-only, has-payload
fuse_id (str) : min=0 max=16 step=2 value='0000000000000000' flags=read-only, has-payload
gain (int) : min=256 max=4096 step=1 default=256 value=256 flags=slider
bypass_mode (intmenu): min=0 max=1 default=0 value=0
override_enable (intmenu): min=0 max=1 default=0 value=0
height_align (int) : min=1 max=16 step=1 default=1 value=1
size_align (intmenu): min=0 max=2 default=0 value=0
write_isp_format (int) : min=1 max=1 step=1 default=1 value=1
sensor_signal_properties (u32) : min=0 max=0 step=0 default=0 flags=read-only, has-payload
sensor_image_properties (u32) : min=0 max=0 step=0 default=0 flags=read-only, has-payload
sensor_control_properties (u32) : min=0 max=0 step=0 default=0 flags=read-only, has-payload
sensor_dv_timings (u32) : min=0 max=0 step=0 default=0 flags=read-only, has-payload
sensor_modes (int) : min=0 max=30 step=1 default=30 value=3 flags=read-only
And it seems that no matter how I change the parameters of the DTB file, it has no effect.
And it seems that no matter how I change the parameters of the file DTB, it has no effect.
hello liliasojd,
you’ll need a sensor driver to register the video node (/dev/video0), power-on/off sequence controls, and also I/O controls for sensor streaming.
the answer is yes if you’re based-on ov5693.c to customize your own bridge drivers (i.e. XILINX FPGA CSI-TX).
you’ll need to report the pixel rate of the sensor device.
pixel clock configuration means the total active pixels sending to CSI/VI engine.
did your bridge driver actually sending 1920x1080 sensor streaming?
if yes, suggest you also share the raw files or the image for review the abnormal results.
BTW,
you should also modify the modes property to report correct active regions of each sensor mode.
for example,
ov5693 had three sensor modes by default,
i2c@3180000 {
status = "okay";
ov5693_a@38 {
mode0 { // OV5693_MODE_2592X1944
mode1 { //OV5693_MODE_2592X1458
mode2 { //OV5693_MODE_1280X720
}