Hi, all:
I have issue with our custom camera.
we use csi0-D0/csi0-D1/csi1-D0/csi0-D1, total 4 lane.
the cmos output is yuv422 8bit.
I use cammand:
v4l2-ctl -d /dev/video0 --set-ctrl bypass_mode=0 --stream-mmap --stream-count=10
the app log as below:
VIDIOC_DQBUF: failed: Input/output error
the kernel log as below:
[ 42.493665] xiaolei --- ar0231_power_on
[ 42.497633] ar0231_power_on: power on
[ 42.511867] xiaolei --- ar0231_g_input_status
[ 42.517838] xiaolei --- ar0231_power_off
[ 42.522005] ar0231_power_off: power off
[ 66.048640] xiaolei --- ar0231_power_on
[ 66.052647] ar0231_power_on: power on
[ 66.066541] xiaolei --- ar0231_set_fmt
[ 66.070460] xiaolei --- ar0231_set_fmt
[ 66.083846] xiaolei --- ar0231_get_fmt
[ 66.093610] xiaolei --- ar0231_s_stream
[ 66.097576] ar0231_s_stream++,enable:1
[ 66.101363] ar0231_s_stream mode[0]
[ 66.404942] xiaolei --- ar0231_write_table
[ 66.409142] xiaolei --- ar0231_write_table
[ 66.430529] tegra-vi4 15700000.vi: Status: 7 channel:00 frame:000A
[ 66.436953] tegra-vi4 15700000.vi: timestamp sof 72341553152 eof 72351173120 data 0x00000001
[ 66.446352] tegra-vi4 15700000.vi: capture_id 1 stream 0 vchan 0
[ 67.418046] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 68.422026] tegra-vi4 15700000.vi: ATOMP_FE syncpt timeout!
[ 68.428088] xiaolei --- ar0231_s_stream
[ 68.432147] ar0231_s_stream++,enable:0
the trace as below:
# tracer: nop
#
# entries-in-buffer/entries-written: 44/44 #P:4
#
# _-----=> irqs-off
# / _----=> need-resched
# | / _---=> hardirq/softirq
# || / _--=> preempt-depth
# ||| / delay
# TASK-PID CPU# |||| TIMESTAMP FUNCTION
# | | | |||| | |
kworker/0:1-58 [000] ...1 66.097960: rtos_queue_peek_from_isr_failed: tstamp:2250357107 queue:0x0b4a3c58
kworker/0:1-58 [000] ...1 66.097970: rtcpu_start: tstamp:2250359296
kworker/0:1-58 [000] ...1 66.253991: rtos_queue_peek_from_isr_failed: tstamp:2255358060 queue:0x0b4a3c58
kworker/0:1-58 [000] ...1 66.462000: rtos_queue_peek_from_isr_failed: tstamp:2260358548 queue:0x0b4a3c58
kworker/0:1-58 [000] ...1 66.462012: rtcpu_vinotify_handle_msg: tstamp:2260674117 tag:CHANSEL_PXL_SOF channel:0x00 frame:10 vi_tstamp:2260673536 data:0x00000001
kworker/0:1-58 [000] ...1 66.462015: rtcpu_vinotify_handle_msg: tstamp:2260674371 tag:ATOMP_FS channel:0x00 frame:10 vi_tstamp:2260673551 data:0x00000000
kworker/0:1-58 [000] ...1 66.462017: rtcpu_vinotify_handle_msg: tstamp:2260679288 tag:CHANSEL_LOAD_FRAMED channel:0x01 frame:10 vi_tstamp:2260678850 data:0x08000000
kworker/0:1-58 [000] ...1 66.462019: rtcpu_vinotify_handle_msg: tstamp:2260974770 tag:CHANSEL_SHORT_FRAME channel:0x01 frame:10 vi_tstamp:2260974160 data:0x00000001
kworker/0:1-58 [000] ...1 66.462021: rtcpu_vinotify_handle_msg: tstamp:2260975026 tag:ATOMP_FE channel:0x00 frame:10 vi_tstamp:2260974160 data:0x00000000
kworker/0:1-58 [000] ...1 66.617999: rtos_queue_peek_from_isr_failed: tstamp:2265359121 queue:0x0b4a3c58
kworker/0:1-58 [000] ...1 66.774025: rtos_queue_peek_from_isr_failed: tstamp:2270359625 queue:0x0b4a3c58
kworker/0:1-58 [000] ...1 66.929992: rtos_queue_peek_from_isr_failed: tstamp:2275360068 queue:0x0b4a3c58
kworker/0:1-58 [000] ...1 67.085993: rtos_queue_peek_from_isr_failed: tstamp:2280360573 queue:0x0b4a3c58
kworker/0:1-58 [000] ...1 67.242027: rtos_queue_peek_from_isr_failed: tstamp:2285361081 queue:0x0b4a3c58
kworker/0:1-58 [000] ...1 67.398003: rtos_queue_peek_from_isr_failed: tstamp:2290361646 queue:0x0b4a3c58
kworker/0:1-58 [000] ...1 67.554013: rtos_queue_peek_from_isr_failed: tstamp:2295362094 queue:0x0b4a3c58
kworker/0:1-58 [000] ...1 67.709993: rtos_queue_peek_from_isr_failed: tstamp:2300362602 queue:0x0b4a3c58
kworker/0:1-58 [000] ...1 67.866010: rtos_queue_peek_from_isr_failed: tstamp:2305363108 queue:0x0b4a3c58
kworker/0:1-58 [000] ...1 68.021977: rtos_queue_peek_from_isr_failed: tstamp:2310363616 queue:0x0b4a3c58
kworker/0:1-58 [000] ...1 68.177986: rtos_queue_peek_from_isr_failed: tstamp:2315364135 queue:0x0b4a3c58
kworker/0:1-58 [000] ...1 68.333994: rtos_queue_peek_from_isr_failed: tstamp:2320364629 queue:0x0b4a3c58
kworker/0:1-58 [000] ...1 68.440553: rtos_queue_peek_from_isr_failed: tstamp:2323399345 queue:0x0b4a3c58
kworker/0:2-247 [000] ...1 80.761935: rtos_queue_peek_from_isr_failed: tstamp:2707500156 queue:0x0b4a3c58
kworker/0:2-247 [000] ...1 80.761938: rtcpu_start: tstamp:2707501082
kworker/0:2-247 [000] ...1 80.917944: rtos_queue_peek_from_isr_failed: tstamp:2712501002 queue:0x0b4a3c58
kworker/0:2-247 [000] ...1 81.081956: rtos_queue_peek_from_isr_failed: tstamp:2717501501 queue:0x0b4a3c58
kworker/0:2-247 [000] ...1 81.081961: rtcpu_vinotify_handle_msg: tstamp:2717728365 tag:CHANSEL_PXL_SOF channel:0x00 frame:113 vi_tstamp:2717727833 data:0x00000001
kworker/0:2-247 [000] ...1 81.081961: rtcpu_vinotify_handle_msg: tstamp:2717728523 tag:ATOMP_FS channel:0x00 frame:113 vi_tstamp:2717727848 data:0x00000000
kworker/0:2-247 [000] ...1 81.081962: rtcpu_vinotify_handle_msg: tstamp:2717730594 tag:CHANSEL_LOAD_FRAMED channel:0x01 frame:113 vi_tstamp:2717730193 data:0x08000000
kworker/0:2-247 [000] ...1 81.081962: rtcpu_vinotify_handle_msg: tstamp:2718030245 tag:CHANSEL_SHORT_FRAME channel:0x01 frame:113 vi_tstamp:2718029674 data:0x00000001
kworker/0:2-247 [000] ...1 81.081963: rtcpu_vinotify_handle_msg: tstamp:2718030429 tag:ATOMP_FE channel:0x00 frame:113 vi_tstamp:2718029674 data:0x00000000
kworker/0:2-247 [000] ...1 81.237958: rtos_queue_peek_from_isr_failed: tstamp:2722502027 queue:0x0b4a3c58
kworker/0:2-247 [000] ...1 81.393930: rtos_queue_peek_from_isr_failed: tstamp:2727502532 queue:0x0b4a3c58
kworker/0:2-247 [000] ...1 81.549945: rtos_queue_peek_from_isr_failed: tstamp:2732503020 queue:0x0b4a3c58
kworker/0:2-247 [000] ...1 81.705939: rtos_queue_peek_from_isr_failed: tstamp:2737503526 queue:0x0b4a3c58
kworker/0:2-247 [000] ...1 81.861986: rtos_queue_peek_from_isr_failed: tstamp:2742504083 queue:0x0b4a3c58
kworker/0:2-247 [000] ...1 82.017986: rtos_queue_peek_from_isr_failed: tstamp:2747504587 queue:0x0b4a3c58
kworker/0:2-247 [000] ...1 82.173965: rtos_queue_peek_from_isr_failed: tstamp:2752505092 queue:0x0b4a3c58
kworker/0:2-247 [000] ...1 82.330122: rtos_queue_peek_from_isr_failed: tstamp:2757505600 queue:0x0b4a3c58
kworker/0:2-247 [000] ...1 82.485981: rtos_queue_peek_from_isr_failed: tstamp:2762506105 queue:0x0b4a3c58
kworker/0:2-247 [000] ...1 82.642035: rtos_queue_peek_from_isr_failed: tstamp:2767506668 queue:0x0b4a3c58
kworker/0:2-247 [000] ...1 82.849953: rtos_queue_peek_from_isr_failed: tstamp:2772507076 queue:0x0b4a3c58
kworker/0:2-247 [000] ...1 83.005942: rtos_queue_peek_from_isr_failed: tstamp:2777507583 queue:0x0b4a3c58
kworker/0:1-58 [000] ...1 83.059635: rtos_queue_peek_from_isr_failed: tstamp:2780516172 queue:0x0b4a3c58
the dtsi as below：
#include <t18x-common-modules/tegra186-camera-ar0231-a00.dtsi>
#include "dt-bindings/clock/tegra186-clock.h"
#define CAM0_RST_L TEGRA_MAIN_GPIO(R, 5)
#define CAM0_PWDN TEGRA_MAIN_GPIO(R, 0)
#define CAM1_RST_L TEGRA_MAIN_GPIO(R, 1)
#define CAM1_PWDN TEGRA_MAIN_GPIO(L, 6)
#define CAMERA_I2C_MUX_BUS(x) (0x1E + x)
/ {
host1x {
vi@15700000 {
num-channels = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
liar0231_vi_in0: endpoint {
csi-port = <0>;
bus-width = <4>;
remote-endpoint = <&liar0231_csi_out0>;
};
};
};
};
nvcsi@150c0000 {
num-channels = <1>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
liar0231_csi_in0: endpoint@0 {
csi-port = <0>;
bus-width = <4>;
remote-endpoint = <&liar0231_ar0231_out0>;
};
};
port@1 {
reg = <1>;
liar0231_csi_out0: endpoint@1 {
remote-endpoint = <&liar0231_vi_in0>;
};
};
};
};
};
};
};
/ {
tegra-camera-platform {
compatible = "nvidia, tegra-camera-platform";
/**
* Physical settings to calculate max ISO BW
*
* num_csi_lanes = <>;
* Total number of CSI lanes when all cameras are active
*
* max_lane_speed = <>;
* Max lane speed in Kbit/s
*
* min_bits_per_pixel = <>;
* Min bits per pixel
*
* vi_peak_byte_per_pixel = <>;
* Max byte per pixel for the VI ISO case
*
* vi_bw_margin_pct = <>;
* Vi bandwidth margin in percentage
*
* max_pixel_rate = <>;
* Max pixel rate in Kpixel/s for the ISP ISO case
*
* isp_peak_byte_per_pixel = <>;
* Max byte per pixel for the ISP ISO case
*
* isp_bw_margin_pct = <>;
* Isp bandwidth margin in percentage
*/
num_csi_lanes = <4>;
max_lane_speed = <1500000>;
min_bits_per_pixel = <10>;
vi_peak_byte_per_pixel = <2>;
vi_bw_margin_pct = <25>;
max_pixel_rate = <750000>;
isp_peak_byte_per_pixel = <5>;
isp_bw_margin_pct = <25>;
/**
* The general guideline for naming badge_info contains 3 parts, and is as follows,
* The first part is the camera_board_id for the module; if the module is in a FFD
* platform, then use the platform name for this part.
* The second part contains the position of the module, ex. "rear" or "front".
* The third part contains the last 6 characters of a part number which is found
* in the module's specsheet from the vender.
*/
modules {
module2 {
badge = "ar0231_center_liar0231";
position = "center";
orientation = "1";
drivernode0 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_sensor";
/* Driver v4l2 device name */
devname = "ar0231 30-006a";
/* Declare the device-tree hierarchy to driver instance */
proc-device-tree = "/proc/device-tree/i2c@c240000/ar0231_a@6a";
};
};
};
};
};
&gen2_i2c {
status = "okay";
ar0231_a@6a {
compatible = "nvidia,ar0231";
/* I2C device address */
reg = <0x6a>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&tegra_car TEGRA186_CLK_EXTPERIPH1>,
<&tegra_car TEGRA186_CLK_PLLP_OUT0>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
reset-gpios = <&tegra_main_gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
vana-supply = <&en_vdd_cam_hv_2v8>;
vif-supply = <&en_vdd_cam>;
vdig-supply = <&en_vdd_cam_1v2>;
/* V4L2 device node location */
devnode = "video0";
/* Physical dimensions of sensor */
physical_w = "3";
physical_h = "3";
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
avdd-reg = "vana";
iovdd-reg = "vif";
dvdd-reg = "vdig";
/* Defines number of frames to be dropped by driver internally after applying */
/* sensor crop settings. Some sensors send corrupt frames after applying */
/* crop co-ordinates */
/*post_crop_frame_drop = "0";*/
/* if true, delay gain setting by one frame to be in sync with exposure */
delayed_gain = "true";
/**
* A modeX node is required to support v4l2 driver
* implementation with NVIDIA camera software stack
*
* mclk_khz = "";
* Standard MIPI driving clock, typically 24MHz
*
* num_lanes = "";
* Number of lane channels sensor is programmed to output
*
* tegra_sinterface = "";
* The base tegra serial interface lanes are connected to
*
* discontinuous_clk = "";
* The sensor is programmed to use a discontinuous clock on MIPI lanes
*
* dpcm_enable = "true";
* The sensor is programmed to use a DPCM modes
*
* cil_settletime = "";
* MIPI lane settle time value.
* A "0" value attempts to autocalibrate based on mclk_multiplier
*
*
*
*
* active_w = "";
* Pixel active region width
*
* active_h = "";
* Pixel active region height
*
* pixel_t = "";
* The sensor readout pixel pattern
*
* readout_orientation = "0";
* Based on camera module orientation.
* Only change readout_orientation if you specifically
* Program a different readout order for this mode
*
* line_length = "";
* Pixel line length (width) for sensor mode.
* This is used to calibrate features in our camera stack.
*
* mclk_multiplier = "";
* Multiplier to MCLK to help time hardware capture sequence
* TODO: Assign to PLL_Multiplier as well until fixed in core
*
* pix_clk_hz = "";
* Sensor pixel clock used for calculations like exposure and framerate
*
*
*
*
* inherent_gain = "";
* Gain obtained inherently from mode (ie. pixel binning)
*
* min_gain_val = ""; (floor to 6 decimal places)
* max_gain_val = ""; (floor to 6 decimal places)
* Gain limits for mode
*
* min_exp_time = ""; (ceil to integer)
* max_exp_time = ""; (ceil to integer)
* Exposure Time limits for mode (us)
*
*
* min_hdr_ratio = "";
* max_hdr_ratio = "";
* HDR Ratio limits for mode
*
* min_framerate = "";
* max_framerate = "";
* Framerate limits for mode (fps)
*
* embedded_metadata_height = "";
* Sensor embedded metadata height in units of rows.
* If sensor does not support embedded metadata value should be 0.
*/
mode0 { // AR0231_MODE_1920X1080
mclk_khz = "27000";
num_lanes = "4";
tegra_sinterface = "serial_a";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
dynamic_pixel_bit_depth = "8";
csi_pixel_bit_depth = "8";
mode_type = "yuv";
pixel_phase = "yuyv";
active_w = "1280";
active_h = "720";
//pixel_t = "bayer_grbg";
readout_orientation = "0";
line_length = "1280";
inherent_gain = "1";
mclk_multiplier = "25";
pix_clk_hz = "39125546";
min_gain_val = "1"; /* dB */
max_gain_val = "48"; /* dB */
min_hdr_ratio = "1";
max_hdr_ratio = "1";
min_framerate = "6";
max_framerate = "30";
min_exp_time = "110";
max_exp_time = "166577";
embedded_metadata_height = "0";
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
liar0231_ar0231_out0: endpoint {
csi-port = <0>;
bus-width = <4>;
remote-endpoint = <&liar0231_csi_in0>;
};
};
};
};
};
Do you have any idea about this?
Thanks.