PXL_SOF syncpt timeout! err = -11 on TX2-4GB L4T 32.4.4

Hello everyone,

I am working on an external FPGA-CSI2 camera to stream video using OV5693 driver. I was succeeded on TX1 running L4T 28.2 and I could get the video from the camera.

The problem is, TX1 is now obsolete and I am trying to do the same thing on TX2-4GB and because TX2-4GB is not supporting L4T 28.2, most of the things were changed in L4T 32.4.4 and I could not managed to do it.

Here’s what I changed:

Added RGB support in camera_common.c:

{
MEDIA_BUS_FMT_RGB888_1X24,
V4L2_COLORSPACE_SRGB,
V4L2_PIX_FMT_RGB24,
},

In csi4_stream_init function of csi4_fops.c, I removed these lines:

csi4_stream_write(chan, port_num, INTR_MASK, 0x0);
csi4_stream_write(chan, port_num, ERR_INTR_MASK, 0x0);

And added these:

csi4_stream_write(chan, port_num, INTR_MASK,
        PH_ECC_MULTI_BIT_ERR | PD_CRC_ERR_VC0 | PH_ECC_SINGLE_BIT_ERR_VC0);
csi4_stream_write(chan, port_num, ERR_INTR_MASK,
        PH_ECC_MULTI_BIT_ERR | PD_CRC_ERR_VC0 | PH_ECC_SINGLE_BIT_ERR_VC0);
csi4_stream_write(chan, port_num, ERROR_STATUS2VI_MASK,
        CFG_ERR_STATUS2VI_MASK_VC0 | CFG_ERR_STATUS2VI_MASK_VC1 | CFG_ERR_STATUS2VI_MASK_VC2 | CFG_ERR_STATUS2VI_MASK_VC3);

In sensor_common.c, added rgb support in extract_pixel_format function

	else if (strncmp(pixel_t, "rgb_rgb8", size) == 0)
		*format = V4L2_PIX_FMT_RGB24;

In ov5693.c, I made these functions do nothing and just return success:
ov5693_read_reg,
ov5693_write_reg,
ov5693_write_table,
ov5693_power_on,
ov5693_power_off,
ov5693_power_put,
ov5693_power_get,
ov5693_set_gain,
ov5693_set_exposure,
ov5693_set_exposure_short.

In tegra186-quill-p3489-0888-a00-00-base.dts, I removed support for camera modules and plugin manager and included my own camera’s device tree:

#include <t18x-common-platforms/tegra186-quill-common-p3489-1000-a00.dtsi>
#include <t18x-common-platforms/tegra186-quill-power-tree-p3489-1000-a00-00.dtsi>
//#include <t18x-common-platforms/tegra186-quill-camera-modules.dtsi>
#include <t18x-common-modules/tegra186-display-e3320-1000-a00.dtsi>

/* comms dtsi file should be included after gpio dtsi file */
#include <t18x-common-plugin-manager/tegra186-quill-p3489-1000-a00-plugin-manager.dtsi>
#include <t18x-common-modules/tegra186-super-module-e2614-p2597-1000-a00.dtsi>
#include <t18x-common-plugin-manager/tegra186-quill-display-plugin-manager.dtsi>
#include <t18x-common-prod/tegra186-priv-quill-p3489-1000-a00-prod.dtsi>
//#include <t18x-common-plugin-manager/tegra186-quill-camera-plugin-manager.dtsi>

/* My camera support */
#include <tegra186-camera-e3326-a00.dtsi>

In device tree file “tegra186-camera-e3326-a00.dtsi”, which I included in the base dts file, I just modified the fields like what I did in the TX1:

#include "dt-bindings/clock/tegra186-clock.h"

#define CAM0_RST_L	TEGRA_MAIN_GPIO(R, 5)
#define CAM0_PWDN	TEGRA_MAIN_GPIO(R, 0)

/ {
	host1x {
		vi@15700000 {
			num-channels = <1>;
			ports {
				#address-cells = <1>;
				#size-cells = <0>;
				port@0 {
					status = "okay";
					reg = <0>;
					e3326_vi_in0: endpoint {
						//vc-id = <0>;
						status = "okay";
						port-index = <2>;
						bus-width = <4>;
						remote-endpoint = <&e3326_csi_out0>;
					};
				};
			};
		};

		nvcsi@150c0000 {
			num-channels = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			channel@0 {
				status = "okay";
				reg = <0>;
				ports {
					#address-cells = <1>;
					#size-cells = <0>;
					port@0 {
						status = "okay";
						reg = <0>;
						e3326_csi_in0: endpoint@0 {
							status = "okay";
							port-index = <2>;
							bus-width = <4>;
							remote-endpoint = <&e3326_ov5693_out0>;
						};
					};
					port@1 {
						status = "okay";
						reg = <1>;
						e3326_csi_out0: endpoint@1 {
							status = "okay";
							remote-endpoint = <&e3326_vi_in0>;
						};
					};
				};
			};
		};
	};

	i2c@3180000 {
		ov5693_c@36 {
			compatible = "nvidia,ov5693";
			/* I2C device address */
			reg = <0x36>;

			/* V4L2 device node location */
			devnode = "video0";

			/* Physical dimensions of sensor */
			physical_w = "3.674";
			physical_h = "2.738";

			/* Define any required hw resources needed by driver */
			/* ie. clocks, io pins, power sources */
			avdd-reg = "vana";
			iovdd-reg = "vif";

			/* Sensor output flip settings */
			vertical-flip = "true";

			status = "okay";

			/* Define any required hw resources needed by driver */
			/* ie. clocks, io pins, power sources */
			/* mclk-index indicates the index of the */
			/* mclk-name with in the clock-names array */

			clocks = <&tegra_car TEGRA186_CLK_EXTPERIPH1>,
					 <&tegra_car TEGRA186_CLK_PLLP_OUT0>;
			clock-names = "extperiph1", "pllp_grtba";
			mclk = "extperiph1";
			clock-frequency = <24000000>;
			reset-gpios = <&tegra_main_gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
			pwdn-gpios = <&tegra_main_gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
			vana-supply = <&en_vdd_cam_hv_2v8>;
			vif-supply = <&en_vdd_cam>;

			/**
			* A modeX node is required to support v4l2 driver
			* implementation with NVIDIA camera software stack
			*
			* mclk_khz = "";
			* Standard MIPI driving clock, typically 24MHz
			*
			* num_lanes = "";
			* Number of lane channels sensor is programmed to output
			*
			* tegra_sinterface = "";
			* The base tegra serial interface lanes are connected to
			* Incase of virtual HW devices, use virtual
			* For SW emulated devices, use host
			*
			* phy_mode = "";
			* PHY mode used by the MIPI lanes for this device
			*
			* discontinuous_clk = "";
			* The sensor is programmed to use a discontinuous clock on MIPI lanes
			*
			* dpcm_enable = "true";
			* The sensor is programmed to use a DPCM modes
			*
			* cil_settletime = "";
			* MIPI lane settle time value.
			* A "0" value attempts to autocalibrate based on mclk_multiplier
			*
			*
			*
			*
			* active_w = "";
			* Pixel active region width
			*
			* active_h = "";
			* Pixel active region height
			*
			* pixel_t = "";
			* The sensor readout pixel pattern
			*
			* readout_orientation = "0";
			* Based on camera module orientation.
			* Only change readout_orientation if you specifically
			* Program a different readout order for this mode
			*
			* line_length = "";
			* Pixel line length (width) for sensor mode.
			* This is used to calibrate features in our camera stack.
			*
			* mclk_multiplier = "";
			* Multiplier to MCLK to help time hardware capture sequence
			* TODO: Assign to PLL_Multiplier as well until fixed in core
			*
			* pix_clk_hz = "";
			* Sensor pixel clock used for calculations like exposure and framerate
			*
			*
			*
			*
			* inherent_gain = "";
			* Gain obtained inherently from mode (ie. pixel binning)
			*
			* == Source Control Settings ==
			*
			* Gain factor used to convert fixed point integer to float
			* Gain range [min_gain/gain_factor, max_gain/gain_factor]
			* Gain step [step_gain/gain_factor is the smallest step that can be configured]
			* Default gain [Default gain to be initialized for the control.
			*     use min_gain_val as default for optimal results]
			* Framerate factor used to convert fixed point integer to float
			* Framerate range [min_framerate/framerate_factor, max_framerate/framerate_factor]
			* Framerate step [step_framerate/framerate_factor is the smallest step that can be configured]
			* Default Framerate [Default framerate to be initialized for the control.
			*     use max_framerate to get required performance]
			* Exposure factor used to convert fixed point integer to float
			* For convenience use 1 sec = 1000000us as conversion factor
			* Exposure range [min_exp_time/exposure_factor, max_exp_time/exposure_factor]
			* Exposure step [step_exp_time/exposure_factor is the smallest step that can be configured]
			* Default Exposure Time [Default exposure to be initialized for the control.
			*     Set default exposure based on the default_framerate for optimal exposure settings]
			*
			* gain_factor = ""; (integer factor used for floating to fixed point conversion)
			* min_gain_val = ""; (ceil to integer)
			* max_gain_val = ""; (ceil to integer)
			* step_gain_val = ""; (ceil to integer)
			* default_gain = ""; (ceil to integer)
			* Gain limits for mode
			*
			* exposure_factor = ""; (integer factor used for floating to fixed point conversion)
			* min_exp_time = ""; (ceil to integer)
			* max_exp_time = ""; (ceil to integer)
			* step_exp_time = ""; (ceil to integer)
			* default_exp_time = ""; (ceil to integer)
			* Exposure Time limits for mode (us)
			*
			*
			* min_hdr_ratio = "";
			* max_hdr_ratio = "";
			* HDR Ratio limits for mode
			*
			* framerate_factor = ""; (integer factor used for floating to fixed point conversion)
			* min_framerate = "";
			* max_framerate = "";
			* step_framerate = ""; (ceil to integer)
			* default_framerate = ""; (ceil to integer)
			* Framerate limits for mode (fps)
			*/
			mode0 { //OV5693_MODE_1280X720
				mclk_khz = "74250";
				num_lanes = "4";
				tegra_sinterface = "serial_a";
				phy_mode = "DPHY";
				discontinuous_clk = "no"; // degistirdim
				dpcm_enable = "false";
				cil_settletime = "0";

				active_w = "1280";
				active_h = "720";
				mode_type = "rgb";
				pixel_phase = "rgb";
				csi_pixel_bit_depth = "8";
				readout_orientation = "90";
				line_length = "1980";
				inherent_gain = "1";
				mclk_multiplier = "1";
				pix_clk_hz = "74250000";

				gain_factor = "10";
				min_gain_val = "10";/* 1DB*/ 
				max_gain_val = "160";/* 16DB*/ 
				step_gain_val = "1";
				default_gain = "10";
				min_hdr_ratio = "1";
				max_hdr_ratio = "64"; 
				framerate_factor = "1000000";
				min_framerate = "45";/* 45 */ 
				max_framerate = "60";/* 60*/ //
				step_framerate = "1";
				default_framerate = "50"; //
				exposure_factor = "1000000";
				min_exp_time = "34";/* us */
				max_exp_time = "550385";/* us */
				step_exp_time = "1";
				default_exp_time = "8334";/* us */
				embedded_metadata_height = "0";
			};

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					e3326_ov5693_out0: endpoint {
						port-index = <0>;
						bus-width = <4>;
						remote-endpoint = <&e3326_csi_in0>;
					};
				};
			};
		};
	};

	e3326_lens_ov5693@P5V27C {
		min_focus_distance = "0.0";
		hyper_focal = "0.0";
		focal_length = "2.67";
		f_number = "2.0";
		aperture = "2.0";
	};

	tegra-camera-platform {
		compatible = "nvidia, tegra-camera-platform";
		/**
		* Physical settings to calculate max ISO BW
		*
		* num_csi_lanes = <>;
		* Total number of CSI lanes when all cameras are active
		*
		* max_lane_speed = <>;
		* Max lane speed in Kbit/s
		*
		* min_bits_per_pixel = <>;
		* Min bits per pixel
		*
		* vi_peak_byte_per_pixel = <>;
		* Max byte per pixel for the VI ISO case
		*
		* vi_bw_margin_pct = <>;
		* Vi bandwidth margin in percentage
		*
		* max_pixel_rate = <>;
		* Max pixel rate in Kpixel/s for the ISP ISO case
		*
		* isp_peak_byte_per_pixel = <>;
		* Max byte per pixel for the ISP ISO case
		*
		* isp_bw_margin_pct = <>;
		* Isp bandwidth margin in percentage
		*/
		num_csi_lanes = <4>;
		max_lane_speed = <1500000>;
		min_bits_per_pixel = <10>;
		vi_peak_byte_per_pixel = <2>;
		vi_bw_margin_pct = <25>;
		max_pixel_rate = <160000>;
		isp_peak_byte_per_pixel = <5>;
		isp_bw_margin_pct = <25>;

		/**
		* The general guideline for naming badge_info contains 3 parts, and is as follows,
		* The first part is the camera_board_id for the module; if the module is in a FFD
		* platform, then use the platform name for this part.
		* The second part contains the position of the module, ex. “rear” or “front”.
		* The third part contains the last 6 characters of a part number which is found
		* in the module's specsheet from the vender.
		*/
		modules {
			module0 {
				badge = "e3326_front_P5V27C";
				position = "rear";
				orientation = "1";
				status = "okay";
				drivernode0 {
					status = "okay";
					/* Declare PCL support driver (classically known as guid)  */
					pcl_id = "v4l2_sensor";
					/* Driver v4l2 device name */
					devname = "ov5693 2-0036";
					/* Declare the device-tree hierarchy to driver instance */
					proc-device-tree = "/proc/device-tree/i2c@3180000/ov5693_c@36";
				};
				drivernode1 {
					status = "okay";
					/* Declare PCL support driver (classically known as guid)  */
					pcl_id = "v4l2_lens";
					proc-device-tree = "/proc/device-tree/e3326_lens_ov5693@P5V27C/";
				};
			};
		};
	};
};

After I try to get image from /dev/video0 by using this command,

gst-launch-1.0 v4l2src device=/dev/video0 ! videorate max-rate=50 ! videoconvert ! omxh265enc qp-range=30,50:30,50:30,50 control-rate=4 bitrate=3000000 ! "video/x-h265, stream-format=(string)byte-stream" ! rtph265pay mtu=1400 ! udpsink host=192.168.1.5 port=5700 sync=false async=false

I see that error on dmesg and get no video stream:

[  202.839975] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[  202.846549] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[  203.895893] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[  203.902330] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[  204.951990] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[  204.958568] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel

What should I inspect first, what am I missing? Any suggestions?

Please check the trace log and capture by the v4l2-ctl would be good to verify the driver implement.

echo 1 > /sys/kernel/debug/tracing/tracing_on
echo 30720 > /sys/kernel/debug/tracing/buffer_size_kb
echo 1 > /sys/kernel/debug/tracing/events/tegra_rtcpu/enable
echo 1 > /sys/kernel/debug/tracing/events/freertos/enable
echo 2 > /sys/kernel/debug/camrtc/log-level
echo 1 > /sys/kernel/debug/tracing/events/camera_common/enable
echo > /sys/kernel/debug/tracing/trace
cat /sys/kernel/debug/tracing/trace

Hi ShaneCCC,

Thank you for your interest.

Trace log:
trace.txt (1.6 MB)

The trace log tell didn’t receive any validate data from the MIPI bus.
Have a probe the MIPI signal to make sure of the sensor output correct data.

Thank you for your reply ShaneCCC.

I managed to stream video on TX1 and TX2 running L4T 28.2 on the same configuration.

Source of the problem may related with the hardware differences between TX2 and TX2-4GB. Does TX2 and TX2-4GB have the same pinout?

Yes, it’s the same pinout.

After inspecting the device tree carefully, I found that the port-index = <2>; is invalid for my setup. In TX1 and TX2, I used the port #0. I fixed the issue by correcting the value.

Sorry for my carelessness.

Thank you for your assistance, ShaneCCC. May the force be with you.