Hi @ShaneCCC
We contact with the sensor FAE, we trigger the clock lane and data lane signal by oscilloscope. The FAE confirms that waveforms are fun. But, v4l2-ctl still does not work.
root@t-desktop:/home/t# v4l2-ctl --stream-mmap --verbose -d /dev/video1
VIDIOC_QUERYCAP: ok
VIDIOC_REQBUFS: ok
VIDIOC_QUERYBUF: ok
VIDIOC_QBUF: ok
VIDIOC_QUERYBUF: ok
VIDIOC_QBUF: ok
VIDIOC_QUERYBUF: ok
VIDIOC_QBUF: ok
VIDIOC_QUERYBUF: ok
VIDIOC_QBUF: ok
VIDIOC_STREAMON: ok
it blocks here, and gets no frame.
the dmesg shows that:
[ 93.808093] ov9281 2-0010: ov9281_power_on: power on
[ 93.818739] ov9281 2-0010: Using default I2C address 0x10
[ 93.845016] ov9281 2-0010: ov9281_s_stream: write mode table 0
[ 93.871079] ov9281 2-0010: ov9281_s_stream: write fsync table 2
[ 93.945481] ov9281 2-0010: ov9281_s_stream: write fsync slave mode table 0
[ 93.952830] ov9281 2-0010: ov9281_s_stream: stream on
[ 94.170086] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 94.176741] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 94.187562] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_INTR_STATUS 0x00000104
[ 94.195758] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_ERR_INTR_STATUS 0x00000104
[ 94.406390] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 94.412945] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 94.422820] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_INTR_STATUS 0x04000114
[ 94.430861] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_ERR_INTR_STATUS 0x04000114
[ 94.642656] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 94.649256] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 94.659833] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_INTR_STATUS 0x04000114
[ 94.668049] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_ERR_INTR_STATUS 0x04000114
[ 94.878867] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 94.885477] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 94.896044] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_INTR_STATUS 0x04000114
[ 94.904325] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_ERR_INTR_STATUS 0x04000114
[ 95.115256] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 95.121824] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 95.132654] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_INTR_STATUS 0x04000114
[ 95.140850] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_ERR_INTR_STATUS 0x04000114
[ 95.351594] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 95.358144] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 95.368900] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_INTR_STATUS 0x04000114
[ 95.377122] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_ERR_INTR_STATUS 0x04000114
[ 95.587590] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 95.594344] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 95.605310] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_INTR_STATUS 0x04000114
[ 95.613488] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_ERR_INTR_STATUS 0x04000114
[ 95.823863] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 95.830579] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 95.840773] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_INTR_STATUS 0x04000114
[ 95.848974] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_ERR_INTR_STATUS 0x04000114
[ 96.060053] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 96.066567] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 96.077154] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_INTR_STATUS 0x04000114
[ 96.085343] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_ERR_INTR_STATUS 0x04000114
[ 96.296403] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 96.303054] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 96.313958] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_INTR_STATUS 0x04000194
[ 96.322247] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_ERR_INTR_STATUS 0x04000194
[ 96.532628] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 96.539207] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 96.550153] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_INTR_STATUS 0x04000194
[ 96.558382] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_ERR_INTR_STATUS 0x04000194
noting that ERROR_STATUS2VI_VC0 has gone.
but, the trace log shows no tags, such as PXL_SOF PXL_EOF etc.
we refer to the TRM, 28.6.138 chapter.
bit 8 means err_intr_cil_data_lane_rxfifo_full_err1_a.
bit 6 means err_intr_cil_data_lane_sot_mb_err1_a.
bit 2 means err_intr_cil_data_lane_sot_mb_err0_a.
Could you give us some introductions about these error data?
BTW
root@t-desktop:/home/t# v4l2-ctl --list-formats-ext
ioctl: VIDIOC_ENUM_FMT
Index : 0
Type : Video Capture
Pixel Format: 'GREY'
Name : 8-bit Greyscale
Size: Discrete 640x400
Interval: Discrete 0.008s (120.000 fps)
the above logs show only index0, but video1 can not be detected.
We refer to this post, and find that all cameras, such as video0 video1 should be seen.
Could this be a trace point?