AGX Orin M.2 C4 PCIe DTS Ranges Values

Using an FPGA as ep with 512MB BAR, the Orin will not boot with the following error:
ASSERT [PciHostBridgeDxe] /dvs/git/dirty/git-master_linux/out/nvidia/bootloader/uefi/Jetson_RELEASE/edk2/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c(879): (Translation & Alignment) == 0

Through my research I have found that there may be a limit to eps with only up to 128MB.
I have tried to change the ranges in the dts, but need to be sure that I am doing it right. Also, I am unsure of which sections correspond to C4 (m.2 key M) and C5 (the main PCIe connector).

  1. Is pcie@14140000 the correct section? If not, can you please tell me which one is?
  2. To update the dts, is the following correct?:
sudo dtc -O dts /boot/dtb/kernel_tegra234-p3701-0000-p3737-0000.dtb > mine.dts
# Edit
sudo dtc -O dtb mine.dts -o /boot/dtb/kernel_tegra234-p3701-0000-p3737-0000.dtb
# reboot
  1. What values would allow the Orin to boot with the FPGA (512MB BAR)?

Please check the mapping in document:
Jetson AGX Orin Platform Adaptation and Bring-Up — Jetson Linux<br/>Developer Guide 34.1 documentation

C4 is pcie@14160000

Thanks for the clarification.
I have changed the ranges to allow 2GB non-prefetchable and adjusted prefetchable ranges as shown below. However, after running the commands I posted previously and rebooting, I get the same error and the unit will not boot. Am I updating the dtb properly or is there a better way to do it?

# Original
ranges = <\
		0x81000000 0x00 0x36100000 0x00 0x36100000 0x00 0x100000 \
		0x82000000 0x00 0x40000000 0x24 0x28000000 0x00 0x8000000 \
		0xc3000000 0x21 0x40000000 0x21 0x40000000 0x02 0xe8000000>;
# Mine
ranges = <\
		0x81000000 0x00 0x36100000 0x00 0x36100000 0x00 0x100000 \
		0x82000000 0x00 0x40000000 0x23 0xb0000000 0x00 0x80000000 \
		0xc3000000 0x21 0x40000000 0x21 0x40000000 0x02 0x70000000>;

Is the EP device inserted to M.2 slot or main PCIe slot on Orin developer kit?

The EP is connected to the M.2 Key M slot with a x4 PCIe adapter. The same issue occurs when the EP is inserted in the x16 PCIe clot. Same error message, same behavior. Both with default dtb and with my modified dtb (including modifying pcie@141a0000). I have verified that the m.2 to PCIe adapter is functional by using a EP device with a small BAR. The EP does not require 12V on the PCIe 12V pins. It is externally powered.

Quick update. After replacing the dtb and rebooting, lspci was showing the old start address. I replaced the dtb in both /boot and /boot/dtb and it seems that the start address reflects the value I set it to.

I remember on an NXP board I worked on that it required the pcie clock to be generated at all times, not just when detected. Could something like that be needed here?

Lastly, if I program the FPGA while the Orin is booting, the Orin will boot, the BARs show up, however writing to the BARs does not work.

Can someone please verify that I even have the correct values in my dts? (Above)


Another update. Using the boot Orin, then while the Orin is booting program the FPGA method, and using the following dts ranges allows me to read and write to the BARs (after enabling the device manually).

ranges = <\
0x81000000 0x00 0x36100000 0x00 0x36100000 0x00 0x100000 \
0x82000000 0x00 0x40000000 0x23 0x40000000 0x00 0xC0000000 \
0xc3000000 0x21 0x40000000 0x21 0x40000000 0x02 0x00000000>;

The order of operations to get it to work is as follows:

// Power on Orin
// While Orin is booting, program FPGA (I believe the FPGA is done being programmed after the bootloader does it's thing and before the kernel scans the pcie bus)
// Log in to Orin
$ sudo -s
# echo 1 > /sys/bus/pci/devices/0004\:01\:00.0/enable
// RW to BARs works as expected

These steps work on both C4 and C5.
Now the question is why can’t the bootloader (or other early fw) recognize the EP correctly.
My guess is that something similar to the NXP issue is occurring. The NXP issue was resolved by flipping a DIP switch from:

"0: PCIe slots are clocked only when a card is installed (default setting)"
"1: PCIe slots are clocked always"

Any insight as to whether I’m barking up the right tree here? Any other ideas?