CC5.0 Will bank conflict occur between different warps?

My GPU is GTX 750 Ti Boost ,CC 5.0

Question is :I’m using shared memory ,my kernel will have threads in different warps write different addresses in the same bank (but threads in the same warp write different banks),will this cause bank conflict?

I don’t think that two warps doing memory access can be dual issued.

So my vote is on “no warp conflicts”.


thank you for your answer.but the CUDA doc says that there are 4 warp schedulers, so I’m wondering if 2 warps writing the same bank will be issued at the same time by 2 distinct schedulers ,I think this will cause a bank conflict ,but the chance may be remote.

Yeah, we can all have a warp vote about that (bwahaha).

Let’s wait until nvidia staff like njuffa weigh in.

No, bank conflicts do not occur between warps. Likewise there is no opportunity for coalescing across different warps. The memory controller(s) deal with coalescing or shared memory on a per-warp-instruction basis. Requests emanating from different “warp-instructions” are not aggregated for the purposing of determining bank conflicts or coalescing behavior.

By the way, there is nothing unique about Maxwell (cc5.0) in this respect. Kepler SM (cc3.x) has multiple schedulers, each of which is capable of dual-issue.

thank you. I avoided the bank conflict in my kernel ,and decrease the operation time by 1/6.

Re: Let’s wait until nvidia staff like njuffa weigh in.

To avoid misunderstandings: in that case it would be “former NVIDIA staff” :-)