Clarification on the accumulator layout in an mma instruction

Accelerated Computing CUDA CUDA Programming and Performance
1

I’m looking at the documentation on MMA instructions from GTC 2020:

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And I just want to confirm that in this example T0 (in the accumulator), is storing

  • 2 elements corresponding to (row 0 x column 1, row 0 x column 2)
  • 2 elements corresponding to (row 9 x column 1, row 9 x column 2)

Seems obvious, but worth double-checking this type of thing

2

I guess by accumulator you mean result. T0 means thread 0.

It looks to me like row 0 column 0 and 1, and row 8 column 0 and 1

I assume you are looking for 0-based indexing since you mention row 0.

You should be able to double-check it in the “actual” documentation, the PTX guide.