/dev/ttyTHS2 missing

Hi all

I just got my TX2, and flashed the latest version of the firmware via JetPack. I need to use the hardware serial ports (UART) in my application - I cannot use a USB to serial converter, or SPI/I2C. I’ve looked through the forums for examples of how to use the hardware UARTs, and they say that /dev/ttyTHS2 is connected to the hardware serial port on J17. /dev/ttyTHS1 is the one on J21 which is used for the serial console, and /dev/ttyTHS3 is for the camera module. I’d like to use /dev/ttyTHS2, but it doesn’t appear in /dev:

$ls /dev

8030000.etf               emc_freq_min  i2c-8             mmcblk0     mmcblk0rpmb         nvhost-nvdec      rfkill              tegra-vi0-channel10  tty15  tty31  tty48  tty7     vcs3    vcsa8
autofs                    fb0           iio:device0       mmcblk0p1   net                 nvhost-nvjpg      rtc                 tegra-vi0-channel11  tty16  tty32  tty49  tty8     vcs4    vcsa9
block                     fd            iio:device1       mmcblk0p10  network_latency     nvhost-prof-gpu   rtc0                tegra-vi0-channel2   tty17  tty33  tty5   tty9     vcs5    watchdog
bus                       full          iio:device2       mmcblk0p11  network_throughput  nvhost-sched-gpu  rtc1                tegra-vi0-channel3   tty18  tty34  tty50  ttyS0    vcs6    watchdog0
camchar-dbg               fuse          iio:device3       mmcblk0p12  null                nvhost-tsec       shm                 tegra-vi0-channel4   tty19  tty35  tty51  ttyS1    vcs7    zero
camchar-echo              gpu_freq_max  initctl           mmcblk0p13  nvhost-as-gpu       nvhost-tsecb      snd                 tegra-vi0-channel5   tty2   tty36  tty52  ttyS2    vcs8
char                      gpu_freq_min  input             mmcblk0p14  nvhost-ctrl         nvhost-tsg-gpu    stderr              tegra-vi0-channel6   tty20  tty37  tty53  ttyS3    vcs9
cluster0_freq_max         hidraw0       keychord          mmcblk0p15  nvhost-ctrl-gpu     nvhost-vi         stdin               tegra-vi0-channel7   tty21  tty38  tty54  ttyTHS1  vcsa
cluster0_freq_min         hidraw1       kmsg              mmcblk0p16  nvhost-ctrl-isp     nvhost-vic        stdout              tegra-vi0-channel8   tty22  tty39  tty55  ttyTHS3  vcsa1
cluster1_freq_max         hidraw2       log               mmcblk0p17  nvhost-ctrl-nvcsi   nvmap             sw_sync             tegra-vi0-channel9   tty23  tty4   tty56  uhid     vcsa10
cluster1_freq_min         i2c-0         mapper            mmcblk0p2   nvhost-ctrl-nvdec   port              tegra_camera_ctrl   tty                  tty24  tty40  tty57  uinput   vcsa11
console                   i2c-1         max_cpu_power     mmcblk0p3   nvhost-ctrl-vi      ppp               tegra-crypto        tty0                 tty25  tty41  tty58  urandom  vcsa12
constraint_cluster0_freq  i2c-2         max_gpu_power     mmcblk0p4   nvhost-ctxsw-gpu    ptmx              tegra_dc_0          tty1                 tty26  tty42  tty59  vcs      vcsa2
constraint_cluster1_freq  i2c-3         max_online_cpus   mmcblk0p5   nvhost-dbg-gpu      ptp0              tegra_dc_ctrl       tty10                tty27  tty43  tty6   vcs1     vcsa3
constraint_gpu_freq       i2c-4         media0            mmcblk0p6   nvhost-gpu          pts               tegra_mipi_cal      tty11                tty28  tty44  tty60  vcs10    vcsa4
constraint_online_cpus    i2c-5         mem               mmcblk0p7   nvhost-isp          quadd             tegra-throughput    tty12                tty29  tty45  tty61  vcs11    vcsa5
cpu_dma_latency           i2c-6         memory_bandwidth  mmcblk0p8   nvhost-msenc        quadd_auth        tegra-vi0-channel0  tty13                tty3   tty46  tty62  vcs12    vcsa6
disk                      i2c-7         min_online_cpus   mmcblk0p9   nvhost-nvcsi        random            tegra-vi0-channel1  tty14                tty30  tty47  tty63  vcs2     vcsa7

Also, when I do dmseg | grep tty, I don’t see anything related to /dev/ttyTHS2

$ dmesg | grep tty
[    0.000000] Kernel command line: fbcon=map:0 net.ifnames=0 console=tty0 OS=l4t console=ttyS0,115200n8 memtype=0 video=tegrafb no_console_suspend=1 earlycon=uart8250,mmio32,0x03100000 gpt tegraid=18.1.2.0.0 tegra_keep_boot_clocks maxcpus=6 android.kerneltype=normal androidboot.serialno=0335115020673 vpr_resize root=/dev/mmcblk0p1 rw rootwait
[    0.022458] console [tty0] enabled
[    1.938271] console [ttyS0] disabled
[    2.348530] 3100000.serial: ttyS0 at MMIO 0x3100000 (irq = 36, base_baud = 25500000) is a Tegra
[    2.521549] console [ttyS0] enabled
[    2.538637] 3110000.serial: ttyTHS1 at MMIO 0x3110000 (irq = 37, base_baud = 0) is a TEGRA_UART
[    2.553953] 3130000.serial: ttyTHS3 at MMIO 0x3130000 (irq = 38, base_baud = 0) is a TEGRA_UART
[   12.893261] systemd[1]: Created slice system-getty.slice.
[   13.091220] systemd[1]: Created slice system-serial\x2dgetty.slice.

Can someone tell me how to

  1. Enable /dev/ttyTHS2 so I can use j17 as a UART?
  2. Use one of the other two ports as a UART? I tried connecting pins 8 and 10 on J21, but was unable to send data back and fourth over ttyTHS1.

So far as J17 goes this was ttyTHS1 on the JTX1. There seems to be an issue with this on the JTX2, more explained below.

J21 has the serial console, this is ttyS0. You would have to disable serial console to use this (and if activity on J21 looks like a keystroke during boot it might halt U-Boot). On the JTX2 CTS/RTS flow control appears to fail for J21/ttyS0, so on serial console you will have to revert to software flow control (no flow control) without CTS/RTS.

Regarding J17:
I tried a number of tests with this port and never had any throughput of any kind. I tried as “/dev/ttyTHS1” and “/dev/ttyTHS3” just to be thorough. I tried speeds 9600, 38400, and 115200, 8N1, with and without flow control.

In some of those tests I was using a serial USB UART to ttyUSB0. In other tests I directly used a loopback of RX and TX to each other directly on the J17 connector, as well as trying with and with CTS and RTS looped back (jumpered) directly on the connector. In no case did anything get through.

On a loopback of “/dev/ttyUSB0” for my USB serial UART the result in a serial terminal is echoing whatever is typed (and this is without local echo). It can be verified that the ttyUSB0 was behaving as expected during the testing. This same port and testing succeeds on a JTX1 with and without CTS/RTS flow control.

During a loopback test it is guaranteed that both ends of the serial port have the same settings in terms of speed, parity, so on. A mismatch between the two ends due to UART hardware being set differently cannot occur.

Thanks for the reply. If I disable the serial console, would I still be prone to boot failure if there is activity on the serial line during boot? Also, how do I disable the serial console?

I was able to get USB to serial to work, but in my application, I am already going to be saturating the USB bus, so I cannot use any sort of USB to serial converter. According to the specs page, UART should be suppoted, so I shouldn’t have to use a USB to serial converter.http://www.nvidia.com/object/embedded-systems-dev-kits-modules.html

I hope I didn’t just buy a $600 paperweight…

Serial console is set up in two places. First, U-Boot has this written in. I’m not sure how you’d disable that, likely you’d have to edit the U-Boot config, recompile it, and flash. This is the part which halts boot if a stray character is sent early on.

Then arguments passed to the Linux kernel set up serial console as the kernel takes over (this latter should be easy it’s just arguments in extlinux.conf). Removing this from extlinux.conf will disable serial console once Linux is actually running:

console=ttyS0,115200n8

I’m having the same missing ttyTHS2 issue on the JTX2 dev board. Any insight from the nVidia devs on where ttyTHS2 has gone would be much appreciated as I have a custom carrier board that this UART is broken out on for use by an external device and I’d like to test out the TX2 on this board at some point in the near future.

@linux dev, previously I was using ttyTHS2 on the J17 header for the JTX1 dev board with great success.

I also tested a number of different devices to try and get J17 to work in case there is some miss-configuration (ttyS0, S1, S3, THS1, THS3) with 9600, 57600, 115200 baud rates. Sadly I wasn’t able to get any output at all with an FT232 hooked up to my PC and PuTTY.

Thanks for the replies. Good to know that I am not the only one having difficulty getting this working. This does not appear to be a feature that was intentionally removed, as it’s still listed as one of the “developer kit key features” on the product splash page http://www.nvidia.com/object/embedded-systems-dev-kits-modules.html

FWIW, I’ve tried connecting pins 8 and 10 on J21 as well as 4 and 5 on J17, and tried echoing data to the serial ports /dev/ttyTHS1 and /dev/ttyTHS3. Neither of them returned a response.

hi all,

the J17 UART was disabled, i’ve share a patch here https://devtalk.nvidia.com/default/topic/1001264/jetson-tx2/tx2-uarts/post/5125115/#5125115 to enables UARTC instance in SW, please take a try.
thanks

@JerryChang Can you give more details on how to use the patch? I am a ametaeur! Ths!

Multiple posts. See:
https://devtalk.nvidia.com/default/topic/1009901/jetson-tx2/tx2-uart-enabling-dev-ttyths2/