Difficulty Achieving Desired 4Mbps Baud Rate UART Configuration on ttyTHS2

[punnaeshwar1]

Hello,

I am currently facing challenges in achieving the desired baud rate of 4Mbps on ttyTHS2 for my TX2i Board.I have only managed to reach 1.5Mbps.

I have done below command
dtc -I fs -O dts -o extracted.dts /proc/device-tree
and checked uarta
serial@3100000
clocks = <0x10 0x37 0x10 0x117>; --------updated this also pllc4_out,pllc4_out_mux
clock-names = “serial”, “parent”;
its showing my clocks are updated .

I have tried FDT also

I have tried `by changing clk_parent also
echo pllc4_out > /sys/kernel/debug/clk/uartc/clk_parent

I would greatly appreciate any guidance or insights from the community on how to overcome this limitation and achieve the desired baud rate. Your assistance would be invaluable.

Thank you!

[KevinFFF]

Hi punnaeshwar1,

Are you using the devkit or custom board for TX2?
What’s your Jetpack version in use?

@punnaeshwar1

.I have only managed to reach 1.5Mbps.

How do you verify the baud rate?

Please share the full dmesg for further check.

[punnaeshwar1]

Thank you for Reply

@KevinFFF

version in use?

I am using JetPack_4.6.4_Linux_JETSON_TX2_TARGETS.
in Jetson-Tx2i Devkit

I am verifying using CP2102 USB-TTL with Teraterm Software.(Hardware support 4Mbps)
dmesg_log.txt (56.7 KB)

[KevinFFF]

[    1.044117] 3100000.serial: ttyS0 at MMIO 0x3100000 (irq = 36, base_baud = 25500000) is a Tegra
[    1.045471] 3110000.serial: ttyTHS1 at MMIO 0x3110000 (irq = 37, base_baud = 0) is a TEGRA_UART
[    1.046306] c280000.serial: ttyTHS2 at MMIO 0xc280000 (irq = 38, base_baud = 0) is a TEGRA_UART
[    1.047165] 3130000.serial: ttyTHS3 at MMIO 0x3130000 (irq = 39, base_baud = 0) is a TEGRA_UART

Which UART interface are you using?
ttyS0(3100000) or ttyTHS2(c280000)?

Please also share your connection for UART. Do you enable HW flow control?

[punnaeshwar1]

I am using J17 pin header i.e tested with ttyTHS2 as shown in image.

I have not enabled any HW flow control.
I am not using CTS/RTS.using only TXD and RXD
Can you please suggest How to enable?

[KevinFFF]

Okay, for the UART from J17, it is uartc: serial@c280000

[    1.046306] c280000.serial: ttyTHS2 at MMIO 0xc280000 (irq = 38, base_baud = 0) is a TEGRA_UART

@punnaeshwar1

Can you please suggest How to enable?

For the use case of high baud rate, we would suggest to enable HW flow control.
Pease connect the RTS of your board to CTS of your UART device , and CTS of your board to RTS of your UART device.
To enable HW flow control, it depends on your application.

Please also share the result of the following command on your board.

# cd /sys/kernel/debug/bpmp/debug/clk/uartc
# grep "" *

[punnaeshwar1]

cd /sys/kernel/debug/bpmp/debug/clk/uartc
grep “” *

[KevinFFF]

Could you try to configure 408M for clock rate?

# echo 408000000 > /sys/kernel/debug/bpmp/debug/clk/uartc

[punnaeshwar1]

Please find the log

We are getting Input/Output error

[KevinFFF]

Sorry that it was a typo.

Please run the following command instead.

# echo 408000000 > /sys/kernel/debug/bpmp/debug/clk/uartc/rate

[punnaeshwar1]

command updated.
echo 408000000 > /sys/kernel/debug/bpmp/debug/clk/uartc/rate

tested 115200 working

tested 4000000 not working

tested 1500000 working but 2000000,2500000,3000000 are not working

my teraterm configurations are like below and tested with 2 bit and RTS/CTS

[linuxdev]

Do you have CTS/RTS flow control listed as an option of “Flow control”? CTS/DTS flow control does not technically make anything faster, but what it does do is improve the result of jitter. It also prevents loss of data if one end sends faster than the other consumes what it receives. I know several people on the forums have had more reliability with CTS/RTS flow control (but you have to have the wires connected, and flow control must be enabled at both UARTs).

[KevinFFF]

@punnaeshwar1

tested 4000000 not working

You may configure clock rate with 64M for baud rate with 4M

# echo 64000000 > /sys/kernel/debug/bpmp/debug/clk/uartc/rate

Please also enable HW flow control in your case.

[punnaeshwar1]

“You may configure clock rate with 64M for baud rate with 4M-
echo 64000000 > /sys/kernel/debug/bpmp/debug/clk/uartc/rate”

Thank You Kevin,

I want to express my gratitude for your suggestions, which guided us toward a solution. Additionally, I utilized the CP2102 hardware. However, when configured at 4000000Mbps, it appears to be internally capped at 1.5Mbps. This limitation seems to be due to the hardware’s specifications, as indicated in the CP2102 datasheet, which supports only up to 1.5Mbps. Unfortunately, we overlooked this detail before conducting our testing.