I need two uart to support baudrate 10Mb/s in Tx2. Is it possible?

As stated in the below link

UartA only has PLLC4_MUXED clock as source as per TRM. Then is only one uart has support for 10 Mb/s in TX2?

Hi Nandagopalan,

Yes, uartA can configure with PLLC4_MUX as clock source.
However, possible clock sources can further have been adjusted when a new clock is qual’ed.
For your current settings, please check using bpmp debugfs knobs.
i.e for Uart-A (or any other uart controller):
cat /sys/kernel/debug/bpmp/debug/clk/uarta/possible_parents

Also please consider the below factors while choosing a source clock:
As per the HW design, all Tegra Uart (hsuart) controllers are accepted with tolerance range 0-4.

So, while requesting for a baudrate, the driver actually adds 2% of desired frequency on total (so that -2 will fall on 0 and +2 will fall on 4).

Based on the new frequency value, the recommended divisor is set.

Coming to the divisor supported: It happens that the recommended divisor may not be accurate to set on the register and hence there are 2 possible divisor values provided (nearest possible on the lower side and nearest possible on higher side)

Based on the above considerations, please be aware that setting PLLC4_MUXED will not help in achieving exactly 10MBPS.
It can confirm to get 8MBPS (on the lower side) or 12MBPS (on the higher side).

Please let us know if you still have any issues on this.

Thanks & Regards,

Hi sandipan,
Thank you for your response.

Is there any way to achieve exactly 10 Mb/s in any uart?


Hi Nanda,

If PllAon_OUT0 is a possible source for any of your usable uarts then this would be the best one.
With this source clock, the recommended divisor 3.5 helps in achieving 9.81 MBPS .
which is with 1.7% error rate. As mentioned earlier, 1.7 error % falls under tolerance range.

Please check if this is listed under possible parents by reading the bpmp debugfs knob.

Thanks & Regards,

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