TX2 UART 2 Stop Bits Requirement

We need more documentation or clarity for our government customer regarding the requirement for 2 stop bits as listed in the TX2 series data sheet and the Parker Processor Errata sheet. Some posts in the forum imply that the problem may be mitigated or avoided by using Baud Rates less than 128K, but we have found no definitive indication that the two (baud rate limit and stop bits requirement) are related. We must integrate with a legacy system that supports only 1 stop bit. How can we get some clarity on this?
edit: well shucks, I was expecting an option to select private message, but could not find it

hello reggie.ratcliff,

by default it’s 115200/8n1,
please refer to post #7 from Topic 110229 to set higher baud rate.
here’s also similar discussion thread, Topic 129317 for your reference.

I have already been referred to that topic, and as I previously replied, it does not answer my question. The data sheet states that 2 stop bits must be used for reliable receiver operation, with no mention of baud rate. Can anyone explain the discrepancy? No one has even been able to provide any documentation that the baud rate issue and stop bits issue are related.
So how do I contact Nvidia?

I am not an official information source, but I can verify that the clock multiplier will not be able to remain with the needed tolerance (+/- 4%?) as speeds go up. Having two stop bits implies the clock error is a smaller percent versus the timing requirements of two stop bits versus one stop bit. Thus the issue revolves around clock timing, and not signal quality.

I imagine that if two Jetsons were talking to each other, then only one stop bit could be used since both would have the same timing from the same clock tolerance issue (never tried it, but would be interested if anyone has and whether two Jetson can use higher baud rates on the serial UART when talking to each other).

If you really want to, then you could dig into the standards for required timing at different baud rates and measure the actual timing relative to that standard if you have good test equipment.

there’s notice in TRM that receiver always checks for 1 stop bit,
attach below for your reference,