In relation to some research, I am trying to disable caches on my Fermi card (GTX470).
So far, I succeeded in disabling the complete level 1 caches by using the following compiler flag for nvcc:
This decreases the performance, so I assume the level 1 cache is actually disabled. However, there is no manual or help on the ‘dlcm’ option, other than that it supports the values ca (enable L1) and cg (disable L1).
Secondly, I tried to disable the L2 cache, but so far without success. Is there any information on this topic available? A solution for me would be welcome in one of the following ways:
- As a compiler flag (similar to disabling L1 cache)
- As a function in the CUDA (host/kernel) code
- As a workaround (tricking the compiler not to cache)
Input is welcome!