On the Memory model page DPA Development - NVIDIA Docs
It says:
The memory model offers 8-byte atomicity for aligned accesses to atomic datatypes. This means that all eight bytes of read and write are performed in one indivisible transaction.
Is this memory any memory we are working with? e.g. if I declare an int64 on the stack and increment it, it is atomic?
Or is this restricted to memory allocated using doca_buf or doca_buf_inventory only?
Alternatively, is there any other lock/mutex synchronization mechanic for the device code? I cannot use std c libraries there…
Thanks