Dose xavier eqos support multi-queue?

Autonomous Machines Jetson & Embedded Systems Jetson AGX Xavier
1

dose xavier eqos support multi-queue?
just for SMP IRQ affininy and IRQ balancing, and how to support multi-queue for EQOS?
thanks.

3

EQOS supports multi-queue. But its not by default enabled. You can enable by adding the flag nvidia,use_multi_queues to the dt of agx. Below file has the documentation.

kernel/nvidia/Documentation/devicetree/bindings/platform/tegra/tegra-eqos.txt

Note that if you enable, you may loose HD support

4

thanks for “nvidia,use_multi_queues”, but IRQs are always happened on CPU0, there isn’t IRQ balancing.
like this:

nvidia@EAXVA03:~$ cat /proc/interrupts | grep eth
40: 253 0 0 0 0 0 0 0 GICv2 226 Level ether_qos.common_irq
42: 424604 0 0 0 0 0 0 0 GICv2 222 Level 2490000.ether_qos.rx0
43: 67 0 0 0 0 0 0 0 GICv2 218 Level 2490000.ether_qos.tx0
44: 33 0 0 0 0 0 0 0 GICv2 223 Level 2490000.ether_qos.rx1
45: 0 0 0 0 0 0 0 0 GICv2 219 Level 2490000.ether_qos.tx1
46: 0 0 0 0 0 0 0 0 GICv2 224 Level 2490000.ether_qos.rx2
47: 366284 0 0 0 0 0 0 0 GICv2 220 Level 2490000.ether_qos.tx2
48: 0 0 0 0 0 0 0 0 GICv2 225 Level 2490000.ether_qos.rx3
49: 0 0 0 0 0 0 0 0 GICv2 221 Level 2490000.ether_qos.tx3

and i started irqbalance service, but there no effect, how can i balance the IRQ to eight CPU cores? thanks.

5

please check this post

6

another question: for eqos multi queue, there is a definition:

/* Max number of chans supported */
#define MAX_CHANS 4

can i change it to 8 channels?
please help to check, you know there isn’t datasheet about EQOS of xavier.

7

No, its hardware Max support

8

how can i implement irq balance in xavier?

9

have you checked the post I mentioned earlier?

Please try changing smp affinity using ‘/proc/irq/$IRQ/smp_affinity_list’ and share if interrupts are still not routed as set.
https://www.kernel.org/doc/Documentation/IRQ-affinity.txt
You can get IRQ number($IRQ) from ‘/proc/interrupts’.

11

Dose xavier eqos support Receive Side Scaling?

12