So I found a post (https://devtalk.nvidia.com/default/topic/982801/tx1-pcie-msi-interrupts-multi-vector-support-/?offset=2) and I have a similar question. I installed Gigabyte 10gbe card (AQC107) on TX2 and it works fine, but I realized all MSI are going to cpu0. /proc/interrupts shows there are four MSI instances for the device, but they are never served by any other cpus than cpu0.
I can’t find a detailed hardware description of TX2 so I was searching something similar and found Xilinx Zynq Ultrascale+ with four ARM Cortex A53 and figured out something interesting. The document (https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf) says 0-31 MSI vectors are coalesced to one GIC interrupt bit.
So what I think is the kernel is virtually generating multiple vectors for the pcie device but in real all the vectors are merged into one interrupt bit at GIC and that’s why only cpu0 is busy. Reading the device tree of the TX2 I assume it is using GICv2 and according to the ARM website (https://developer.arm.com/products/system-ip/system-controllers/interrupt-controllers) it looks like GIC-400 is not supporting MSI SMP affinity.
Does anyone know well enough about TX2 PCIe and MSI? Thanks.