Adjusting GPIO IRQ affinity in GIC

I have a signal coming in on a GPIO pin (specifically pin 118/GPIO3_PQ.05 on an Orin NX 8GB), and I would like to change the affinity of it’s IRQ to a core other than 0.

Looking at some previous posts:

It seems ambiguous if this is at all possible, and if so, how to accomplish it. Some posts seem to say it is not possible for GPIO interrupts, and others seem to say it is, with further modification.
I take it that something related to the generic interrupt controller needs to be modified, likely in a register like this post suggests.

I have read through section 8.2 “Interrupt Controllers” and am struggling to see how it is possible to change the affinity of the GIC.
I would appreciate some help figuring this out!

Hi bhagen55,

Some posts you referred are for older release (R32).

Are you using the devkit or custom board for Orin NX?
What’s your Jetpack version in use?

Please share the result of cat /proc/interrupts on your board.

Hi Kevin,
We are using a custom board for our Orin NX running Jetpack 5.1.2 / L4T R35.4.1.

I have attached the contents of /proc/interrupts
interrupts.txt (17.2 KB)

The specific interrupt we are looking to modify is 312 / pps.-1
I have tried changing it’s affinity through /proc/irq but am met with read/write errors that I assume mean changing the affinity in that manner is not supported.

# echo 1 > /proc/irq/312/smp_affinity_list 
sh: echo: write error: Input/output error

It seems this interrupt is not allowed to be changed as you’ve referred to Changing smp affinity to specific interrupt - #7 by Bibek

I think some interrupt can change the smp_affinity_list but some interrupt can’t.
Have you tried to configure other interrupts?

Incidentally, hardware IRQs can only go to cores which have actual wiring to that core. Some PCs will have an asynchronous programmable interrupt controller (APIC) which is used to route to different cores. Jetsons are much more limited because they do not have a general reprogrammable IRQ controller to route to all cores. The first core (CPU0) always has access to all IRQs.

The scheduler can be told to route an IRQ to a core it cannot reach, but at the time the IRQ runs, if things work properly, then the scheduler will still send the IRQ to the first core.

One strategy if you are having performance issues is to take any process on CPU0 that doesn’t have to be there and then to set affinity to any core other than CPU0.

Have you tried to configure other interrupts?

I was able to adjust the affinity of other interrupts, like this one:

151:     186190          0          0          0          0         25     GICv3 208 Level     3c00000.tegra-hsp

Can you clarify the wording in the second two forum posts I referenced? The wording of the replies seems to imply it is possible to adjust the affinity of the GPIO interrupts, but it is done in the GIC, and requires editing registers somewhere.

affinity can only be set at the GIC level.

if you want to achieve the different affinity for pin level of same GPIO controller then you will need the GPIO routing to one of 8 GPIO controller’s interrupt line and then that interrupt line to the particular CPU via GICs.

312:        315          0          0          0          0          0      gpio 105 Edge      pps.-1

I’ve checked this with internal and confirm that affinity can only be set at the GIC level,
All GPIOs are a single interrupt as far as the GIC is concerned.
You can’t configure smp_affinity for gpio since gpio interrupt is independent.