I have used 3 Tegra Main GPIOs: PP.00, PAC.00, PAC.01 to handle the GPIO interrupts.
The 3 pins are connected to 3 FPGA pins on our carrier board. And FPGA will send signals in 30 Hz through the 3 pins simultaneously. I have confirmed the 3 signals are sent simultaneously by using oscilloscope.
The question is, why the interrupt counts grow in different growth rate?
Is it possible to make those IRQ occurs at the same time?
I’ve tried to assign IRQ to different affinity. But after reading below discussion I realize the affinity cannot be changed.
I’ve also modified the gpio-intmap in bootloader to make those pins assigned to different interrupt lines. But it seems no effect.
had you apply GPIO controller’s configurations by modify BCT files.
for instance, you may modify $OUT/Linux_for_Tegra/bootloader/tegra234-mb1-bct-gpioint-p3767-0000.dts to maps the interrupt of GPIO pin.
BTW, please see-also Topic 252603 for reference, thanks
Yes, I’ve modifed the file bootloader/t186ref/BCT/tegra234-mb1-bct-gpioint-<my-model>.dts
And then rebuilt all sources and flash all the partitions. But the interrupts are still bound to CPU0.
By the way, I tested the pps-gpio driver with AON GPIO PBB.01, and the default interrupt line is as below:
Sorry that we don’t have such FPGA device to reproduce the same behavior as yours.
Are you using the custom board for AGX Orin?
What’s your Jetpack version in use?
It’s indeed a custom board for AGX Orin.
And it is Jetpack 5.0.2 now. But I am also waiting for my colleagues porting BSP to Jetpack 5.1.2.
The thread you point to is to use LIC GPIO. I’m confused between LIC GPIO and main GPIO. Is main GPIO the same as LIC GPIO? Because I’ve tried to use GTE on main GPIO, but there were no any interrupts received that time.
