I have used 3 Tegra Main GPIOs: PP.00, PAC.00, PAC.01 to handle the GPIO interrupts.
The 3 pins are connected to 3 FPGA pins on our carrier board. And FPGA will send signals in 30 Hz through the 3 pins simultaneously. I have confirmed the 3 signals are sent simultaneously by using oscilloscope.
The question is, why the interrupt counts grow in different growth rate?
Is it possible to make those IRQ occurs at the same time?
I’ve tried to assign IRQ to different affinity. But after reading below discussion I realize the affinity cannot be changed.
the GPIO interrupt at the GIC is combination of multiple pins from GPIO controller.
if you want to achieve the different affinity for pin level of same GPIO controller then you will need the GPIO routing to one of 8 GPIO controller’s interrupt line and then that interrupt line to the particular CPU via GICs.
I’ve also modified the gpio-intmap in bootloader to make those pins assigned to different interrupt lines. But it seems no effect.
I also found there is a function called GTE seems possibly to forfull my requirement, but it is only support AON GPIOs, not the main GPIOs.
Summarize my questions below:
Is it possible to make multiple IRQ occurs at the same time?
How to evaluate the performance when GPIO are assigned to different interrupt lines in gpio-intmap?
had you apply GPIO controller’s configurations by modify BCT files.
for instance, you may modify $OUT/Linux_for_Tegra/bootloader/tegra234-mb1-bct-gpioint-p3767-0000.dts to maps the interrupt of GPIO pin.
BTW, please see-also Topic 252603 for reference, thanks
Yes, I’ve modifed the file
And then rebuilt all sources and flash all the partitions. But the interrupts are still bound to CPU0.
By the way, I tested the pps-gpio driver with AON GPIO PBB.01, and the default interrupt line is as below:
pin-1-int-line = <4>; // GPIO BB1 to INT0
I don’t understand why the comment describes it is “to INT0”? Not “to INT4”?
And the IRQ occurs on CPU0 when interrupt line is
It seems INT4 if you configure it as
Could you share your
hello driver to detect interrupt?
Have you tried with LIC interrupts?
Have you also tried with lower rate like 1Hz and check the counts if as expected?
Please see my hello driver:
gpio-int-test.dts (1.7 KB)
hello.c (2.0 KB)
I’ not sure how to use LIC interrupts because the FPGA and GPIO pins are wired by the PCB traces.
No matter 1Hz or 30Hz, the test results are the same.
Could you share how do you apply the dts for your board?
and the method to build
Please also share the full
dmesg after you load the driver.
Sorry for the late reply.
Please see the zip file which include the DTS file, driver C codes, and Makefile.
fsync-gpio-interrupt.zip (3.2 KB)
In the Makefile, I’m using jetson-io/config-by-hardware.py to apply DTS.
The txt file below is the dmesg after insmod.
dmesg_load_driver.txt (610 Bytes)
Sorry that we don’t have such FPGA device to reproduce the same behavior as yours.
Are you using the custom board for AGX Orin?
What’s your Jetpack version in use?
You could refer to the following thread about using main GPIO for GTE.
GTE on linux: duplicated event on GPIO rising edge - #4 by maxe777
It’s indeed a custom board for AGX Orin.
And it is Jetpack 5.0.2 now. But I am also waiting for my colleagues porting BSP to Jetpack 5.1.2.
The thread you point to is to use LIC GPIO. I’m confused between LIC GPIO and main GPIO. Is main GPIO the same as LIC GPIO? Because I’ve tried to use GTE on main GPIO, but there were no any interrupts received that time.
You could also refer to the following topic for the steps to use main GPIO as interrupt source.
LIC interrupts and GPIO controllers - #5 by antti.keranen
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