Aon gpio interrupt can not be triggered and interrupt handler not called

[cary1]

define NR_IO_1V8_VSIG_ALM_OD_GPIO ORIN_GPIO_B55
define NR_IO_1V8_VSIG_ALM_OD_PIN ORIN_PIN_B55

    chip_A: spi@4 {
        compatible = "tek,Z168";
        reg = <4>;
        cs-gpio = <&NR_SPI_VSIG_3V3_nCS_GPIO      0>;
        chip-id = <0>;
        camid = <0>;
        rest-gpios = <&NR_IO_VSIG_3V3_nRST_GPIO       GPIO_ACTIVE_LOW>;
        load-gpios = <&NR_IO_VSIG_3V3_nLOAD_GPIO      GPIO_ACTIVE_LOW>;
        busy-gpios = <&NR_IO_1V8_VSIG_nBUSY_OD_GPIO   GPIO_ACTIVE_HIGH>; // input

        int-gpio = <&NR_IO_1V8_VSIG_ALM_OD_GPIO   GPIO_ACTIVE_HIGH>; // input
        interrupt-parent = <&tegra_aon_gpio>;
        interrupts = <NR_IO_1V8_VSIG_ALM_OD_PIN   8>; // active low level-sensitive.

        spi-max-frequency = <2000000>;
        device_number = "L2-UA5-VSIG";
        // 0:3
        measure-channel = <MEASURE_CH_OPEN_SHORT_TEST
                           MEASURE_CH_DOMAIN_SHADOW_DOVDD
                           MEASURE_CH_DOMAIN_VOIS
                           MEASURE_CH_DOMAIN_DOVDD
                           >;

        /delete-property/ controller-data;
    };

I can see the gpio turned low in /sys/kernel/debug/gpio , but the interrupt can not be triggered ，same dts code works for main gpios. Somebody help me!!!

[KevinFFF]

Hi cary1,

Are you using the devkit or custom board?
What’s your Jetpack version in use?

@cary1

the interrupt can not be triggered

What do you mean about interrupt can not be tirggered?
How do you monitor the interrupt?

@cary1

same dts code works for main gpios.

Could you share the configuration of your device tree with main gpio?

[cary1]

thanks for replaying,I’m running JetPack5.0.2 on our custom board.
When the pin input turned low, the interrupt handler did not print anything. Then i checked the system interrupt counter, it didn’t increase, that’s how i monitored the interrupt.
The dts blow is another chip with it’s interrupt pin connected to a main gpio, and it works well.

define NR_IO_1V8_VSIG_ALM_OD_PIN ORIN_PIN_G4
define NR_IO_1V8_VSIG_ALM_OD_GPIO ORIN_GPIO_G4

        chip_B: spi@4 {
        compatible = "tek,Z168";
        reg = <4>;
        cs-gpio = <&NR_SPI_VSIG_3V3_nCS_GPIO      0>;
        chip-id = <10>;
        camid = <1>;
        rest-gpios = <&NR_IO_VSIG_3V3_nRST_GPIO       GPIO_ACTIVE_LOW>;
        load-gpios = <&NR_IO_VSIG_3V3_nLOAD_GPIO      GPIO_ACTIVE_LOW>;
        busy-gpios = <&NR_IO_1V8_VSIG_nBUSY_OD_GPIO   GPIO_ACTIVE_HIGH>; // input

        int-gpio = <&NR_IO_1V8_VSIG_ALM_OD_GPIO   GPIO_ACTIVE_HIGH>; // input
        interrupt-parent = <&tegra_main_gpio>;
        interrupts = <NR_IO_1V8_VSIG_ALM_OD_PIN   8>; // active low level-sensitive.

        spi-max-frequency = <2000000>;
        device_number = "L2-UB7-VSIG";
        // 0:3
        measure-channel = <MEASURE_CH_OPEN_SHORT_TEST
                           MEASURE_CH_DOMAIN_SHADOW_DOVDD
                           MEASURE_CH_DOMAIN_VOIS
                           MEASURE_CH_DOMAIN_DOVDD
                           >;

        /delete-property/ controller-data;
    };

[KevinFFF]

Could you help to verify with latest JP5.1.2(R35.4.1) to check if the issue still exist?

Which pin do you use as interrupt for both case respectively?
Where do you define ORIN_GPIO_B55/ORIN_PIN_B55/ORIN_PIN_G4/ORIN_GPIO_G4 ?

[cary1]

define ORIN_PIN_B55 TEGRA234_AON_GPIO(EE, 2)
define ORIN_GPIO_B55 tegra_aon_gpio ORIN_PIN_B55
/* GPIOs implemented by AON GPIO controller */
define TEGRA234_AON_GPIO_PORT_AA 0
define TEGRA234_AON_GPIO_PORT_BB 1
define TEGRA234_AON_GPIO_PORT_CC 2
define TEGRA234_AON_GPIO_PORT_DD 3
define TEGRA234_AON_GPIO_PORT_EE 4
define TEGRA234_AON_GPIO_PORT_GG 5
define TEGRA234_AON_GPIO(port, offset)
((TEGRA234_AON_GPIO_PORT_#port * 8) + offset)

define ORIN_PIN_G4 TEGRA234_MAIN_GPIO(H, 7)
define ORIN_GPIO_G4 tegra_main_gpio ORIN_PIN_G4

/* GPIOs implemented by main GPIO controller */
define TEGRA234_MAIN_GPIO_PORT_A 0
define TEGRA234_MAIN_GPIO_PORT_B 1
define TEGRA234_MAIN_GPIO_PORT_C 2
define TEGRA234_MAIN_GPIO_PORT_D 3
define TEGRA234_MAIN_GPIO_PORT_E 4
define TEGRA234_MAIN_GPIO_PORT_F 5
define TEGRA234_MAIN_GPIO_PORT_G 6
define TEGRA234_MAIN_GPIO_PORT_H 7
define TEGRA234_MAIN_GPIO_PORT_I 8
define TEGRA234_MAIN_GPIO_PORT_J 9
define TEGRA234_MAIN_GPIO_PORT_K 10
define TEGRA234_MAIN_GPIO_PORT_L 11
define TEGRA234_MAIN_GPIO_PORT_M 12
define TEGRA234_MAIN_GPIO_PORT_N 13
define TEGRA234_MAIN_GPIO_PORT_P 14
define TEGRA234_MAIN_GPIO_PORT_Q 15
define TEGRA234_MAIN_GPIO_PORT_R 16
define TEGRA234_MAIN_GPIO_PORT_X 17
define TEGRA234_MAIN_GPIO_PORT_Y 18
define TEGRA234_MAIN_GPIO_PORT_Z 19
define TEGRA234_MAIN_GPIO_PORT_AC 20
define TEGRA234_MAIN_GPIO_PORT_AD 21
define TEGRA234_MAIN_GPIO_PORT_AE 22
define TEGRA234_MAIN_GPIO_PORT_AF 23
define TEGRA234_MAIN_GPIO_PORT_AG 24
define TEGRA234_MAIN_GPIO(port, offset)
((TEGRA234_MAIN_GPIO_PORT_#port * 8) + offset)

This is how i define ORIN_GPIO_B55/ORIN_PIN_B55/ORIN_PIN_G4/ORIN_GPIO_G4

It would take us some time to verify with JP5.1.2.
I want to knnow if someone has implemented interrupt functions on AON gpios successfully.

[KevinFFF]

Why you don’t just use TEGRA234_AON_GPIO(EE, 2) and TEGRA234_MAIN_GPIO(H, 7) in device tree?

Have you tired Generic Timestamp Engine? It should work with AON GPIO monitoring.