GPIO interrupt mapping: two pins on same GPIO controller to two LIC interrupts

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Xavier
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We’re trying to timestamp pulses on GPIO pins with the Generic Timestamping Engine (GTE). We’re using Legacy Interrupt Controller (LIC) to create interrupts on GPIO signal edges, allowing us to timestamp them with GTE.

This all works well as long as we have only one signal per GPIO controller, using interrupt 0. The issues begin when we try to map two signals to two different interrupts.

For example, we have a 1Hz signal on GPIO M3 and a 500Hz signal on GPIO Q1 (both in controller GPIO_CTL2). The 500Hz signal is not running all the time.

The default GPIO interrupt mapping configuration (t186ref/BCT/tegra194-mb1-bct-gpioint-p2888-0000-p2822-0000.cfg) is as follows:

gpio-intmap.port.M.pin.3 = 0; # GPIO M3 to INT0

gpio-intmap.port.Q.pin.1 = 0; # GPIO Q1 to INT0

With this configuration, we get the expected amount of GPIO interrupts on each pin (and we can verify this by checking /proc/interrupts at a regular interval). However, we can’t differentiate them in GTE; they’re both using LIC interrupt 304.

Below are different ways we’ve tried to configure this:

Configuration 1:

gpio-intmap.port.M.pin.3 = 1; # 1Hz

gpio-intmap.port.Q.pin.1 = 2; # 500Hz

If we map both pins to nonzero interrupts, we get no interrupts at all for either of them. It seems like interrupt 0 is different from all the rest.

Configuration 2:

gpio-intmap.port.M.pin.3 = 0; # 1Hz

gpio-intmap.port.Q.pin.1 = 1; # 500Hz

If we configure the 500Hz signal to interrupt 1, we get strange behavior. The 1Hz signal generates one interrupt a second, but so does the 500Hz signal (as seen in /proc/interrupts). It seems like only interrupt 0 is working properly. We’re basically missing 99.8% of the pulses we want to timestamp.

Configuration 3:

gpio-intmap.port.M.pin.3 = 1; # 1Hz

gpio-intmap.port.Q.pin.1 = 0; # 500Hz

On the other hand, if we make the 1Hz signal interrupt 1, we don’t get any interrupts at all when the 500Hz signal is off. Once we turn the 500Hz signal on, both signals get the correct amount of interrupts.

Questions:

  1. What is the dependence between different interrupt channels for a GPIO controller?
  2. How exactly can we configure the GPIO interrupt mapping so we can get different LIC interrupt numbers for two different pins in the same GPIO controller?
1 Like
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Hi HannuHHH,

Are you using the devkit or custom board for AGX Xavier?

What’s your Jetpack version in use?

Do you mean that 500Hz from external would not output signal sometimes?

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hello HannuHHH,

please also check the device tree,
had you update the GPIO pin as interrupt, you should have below code snippets to define the pin.
for example,

    interrupt-parent = <&tegra_main_gpio>;
    interrupts = <TEGRA194_MAIN_GPIO(M, 3) IRQ_TYPE_EDGE_FALLING>; //or.. IRQ_TYPE_EDGE_RISING
1 Like
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Hi KevinFFF,

We’re using a custom board for AGX Xavier. The operating system we’re running is based on Jetson Linux 35.1.

The external 500Hz signal is sometimes outputting and sometimes not (ie. at a constant value). We need the system to work in both cases.

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Hi JerryChang,

Yes, we have the interrupts in the device tree. This is a snippet for one:

            interrupts = <TEGRA194_MAIN_GPIO(Q, 1) IRQ_TYPE_EDGE_RISING>;
            interrupt-parent = <&tegra_main_gpio>;

As I pointed out, we get the interrupts normally when both pins are mapped to GPIO controller interrupt 0. We only start missing interrupts when the GPIO interrupt mapping is changed.

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We tried reproducing this with the AGX Xavier devkit on an unmodified Jetson Linux 35.3.1, with only a couple of interrupts added to the device tree and a simple kernel driver that requests those interrupts. We used pins from the pin header as inputs and connected them to other pins we used as outputs.

This confirms our observations:

  • The interrupt 0 of a GPIO controller (in the gpioint config) works as expected: you get as many interrupts as there are pulses
  • Other interrupts are never triggered unless interrupt 0 is also triggered

E.g. if you send five pulses to a pin mapped to interrupt 1 and one pulse to a pin mapped to interrupt 0, you get one pulse on both interrupts. The pin mapped to interrupt 1 never triggers a kernel interrupt (eg. in /proc/interrupts) unless interrupt 0 is triggered too.

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@JerryChang @KevinFFF can you find someone who can answer these questions? Or can you point me to GPIO controller documentation (which isn’t included in the AGX Xavier Technical Reference Manual)?

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hello HannuHHH,

BTW,
let me double confirm how you apply GPIO controller’s configurations by modify BCT files.
i.e. modify tegra194-mb1-bct-gpioint-p2888-0000-p2822-0000.cfg to maps the interrupt of GPIO pin.

are you flash the target completely to apply cfg settings?

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Yes, I’m modifying that file and flashing the target completely.

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@JerryChang @KevinFFF do you think you’ll be able to answer this question? This is important to us.

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The Linux driver will check if a controller’s configuration has been locked down, which would imply that something else has already configured the interrupt routing. If so, it won’t touch the configuration. However, if the controller configuration is not locked down yet, it will assume that nothing has configured the interrupt routing yet and will program a default mapping (which will route everything to each controller’s interrupt #0).

Do you lock down the interrupt controller configuration via the BCT?
It would cause the driver to not touch the interrupt routing.

Is there any issue if you are using both INT0 and INT1, and they are both enabled?

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Thanks for the answer @KevinFFF! This sounds relevant to our issue, but I’m missing details.

Can you say which driver specifically deals with interrupt routing?

I don’t quite understand what you mean by locking down a controller’s configuration. I’m reading Xavier_TRM_DP09253002_v1.4p.pdf and Welcome — Jetson Linux Developer Guide documentation but I see no mention of locking down configurations. I haven’t found thorough documentation for the GPIO controllers either. Can you point me to the relevant documentation?

A minimal reproduction of what we’re doing is available in LIC interrupts and GPIO controllers - #8 by antti.keranen and that shows the symptoms described in this question, ie. we’re only getting INT1 interrupts when INT0 is triggered.

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I’m hoping for more information, please!

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I’m still hoping for more information.

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Please refer to my response in the following thread
LIC interrupts and GPIO controllers - #15 by KevinFFF

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