Not getting all Interrupts

Autonomous Machines Jetson & Embedded Systems Jetson Xavier NX
1

I have set the PPS GPIO to GPIO05 (CC,02).

we have two devices that can use to generate the PPs. One has a programmable pulse width, the other does not.

If we have a pulse width of 1ms we get all the PPS interrupts.

If we shorten the pulse to 20us (this is from the device we can not chnage) there are missed PPS’s.

Can the NX detect a pulse as short as 20us?
Can the GPIO interrupt be changed to edge?

3

hello kevin.loll,

you might refer to post #16 from Topic 124003, which produce pps signals on GPIO.
this driver is to feed pps signals in GPIO and capture timestamps to synchronize system every second.

BTW,
please check axi_cbb, please update this node with higher clock rate or max_rate to improve GPIO performance.
for example,

# cd  /sys/kernel/debug/bpmp/debug/clk/axi_cbb
# echo max_rate > rate
# echo 1 > mrq_rate_locked
4

I do not think that post applies. They are generating the PPS.

  1. we are putting a PPS signal on to the GPIO05.
  2. If the PPS width is grater than 1ms we git all of the INPUT PPS interrupts (using dmesg to check)
  3. if our PPS width is 20us then we start missing PPS interrupts.
  4. I tried changing all AON GPIOs to rising edge, but that did not help.
  • /home/asei/nvidia/nvidia_sdk/JetPack_4.6_Linux_JETSON_XAVIER_NX_TARGETS/Linux_for_Tegra/sources/hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc-base-dtsi
  • changed tegra194-soc-base.dtsi

    tegra_aon_gpio: gpio@c2f0000 {
    compatible = “nvidia,tegra194-gpio-aon”;
    reg-names = “security”, “gpio”, “gte”;
    reg = <0x0 0xc2f0000 0x0 0x1000>,
    <0x0 0xc2f1000 0x0 0x1000>,
    <0x0 0xc1e0000 0x0 0x10000>;
    interrupts =
    <0 TEGRA194_IRQ_AON_GPIO_0 IRQ_TYPE_EDGE_RISING>, // @test KSL changed from IRQ_TYPE_LEVEL_HIGH
    <0 TEGRA194_IRQ_AON_GPIO_1 IRQ_TYPE_EDGE_RISING>,
    <0 TEGRA194_IRQ_AON_GPIO_2 IRQ_TYPE_EDGE_RISING>,
    <0 TEGRA194_IRQ_AON_GPIO_3 IRQ_TYPE_EDGE_RISING>;
    status = “disabled”;
    gpio-controller;
    #gpio-cells = <2>;
    interrupt-controller;
    #interrupt-cells = <2>;
    gpio-ranges =
    <&tegra_pinctrl TEGRA194_AON_GPIO_BASE(AA) TEGRA_PIN_BASE(AA) TEGRA194_AON_GPIO_RANGE(AA, EE) >;
    };
5

hello kevin.loll,

could you please refer to below example for the steps to enable rising interrupt and check events.

$ sudo -i
# echo 353 > /sys/class/gpio/export
# echo in > /sys/class/gpio/gpio353/direction
# echo rising > /sys/class/gpio/gpio353/edge

# cat /proc/interrupts | grep gpiolib
  259: 9 0 0 0 0 0 0 0 tegra-gpio 65 Edge gpiolib

besides,
could you please also have a try to add this into device tree for confirmation,
+ interrupt-parent = <&tegra_aon_gpio>;
thanks

6

Where do I add:

interrupt-parent = <&tegra_aon_gpio>;

Any specific file?
Where in file?
Do I need this for the echos to work?

7

This is what I got from the cat
nx_interrupts_cmd_output

The commands did not change the loss of interrupts.

8

Rate was already set at max_rate

9

it’s something like this…

        i2c@7000c000 {
                icm20628@68 {
                        compatible = "invensense,mpu6xxx";
                        reg = <0x68>;
                        interrupt-parent = <&gpio>;
                        interrupts = <TEGRA_GPIO(X, 2) 0x00>;
10

In tegra194-soc-base.dtsi do I need to set the tegra_aon_gpio: gpio@c2f0000 {
status = "disabled
to
status = "okay"
in order to enable the AON gpios?

11

is this correct?
added to "tegra194-soc-base.dtsi

	tegra_aon_gpio: gpio@c2f0000 {
		compatible = "nvidia,tegra194-gpio-aon";
		reg-names = "security", "gpio", "gte";
		reg = 	<0x0 0xc2f0000 0x0 0x1000>,
			<0x0 0xc2f1000 0x0 0x1000>,
			<0x0 0xc1e0000 0x0 0x10000>;
        interrupt-parent = <&tegra_aon_gpio>;   // @test KSL per forum moderator
		interrupts =
			<0 TEGRA194_IRQ_AON_GPIO_0 IRQ_TYPE_EDGE_RISING>,  // @test KSL changed from IRQ_TYPE_LEVEL_HIGH
			<0 TEGRA194_IRQ_AON_GPIO_1 IRQ_TYPE_EDGE_RISING>,
			<0 TEGRA194_IRQ_AON_GPIO_2 IRQ_TYPE_EDGE_RISING>,
			<0 TEGRA194_IRQ_AON_GPIO_3 IRQ_TYPE_EDGE_RISING>;
		status = "okay"  // @test KSL "disabled"; 
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		gpio-ranges =
			<&tegra_pinctrl TEGRA194_AON_GPIO_BASE(AA) TEGRA_PIN_BASE(AA) TEGRA194_AON_GPIO_RANGE(AA, EE) >;
	};
12

hello kevin.loll,

there’re some of pins were having dedicated GPIOs, or alternate SFIO functionality.
please also check Jetson Xavier NX Module Data Sheet for [Table 29: GPIO Pin Descriptions]. it’s better to use the other pins not included in this list.

by default the status property were default configured as status = "disabled"; it’s the later include device tree to overwrite the settings.
for example, please check the plugin-manager, tegra194-p3668-pcie-plugin-manager.dtsi

here’re IRQ bindings definitions, you may able to test edge rising,

#define IRQ_TYPE_NONE		0
#define IRQ_TYPE_EDGE_RISING	1
#define IRQ_TYPE_EDGE_FALLING	2
#define IRQ_TYPE_EDGE_BOTH	(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
#define IRQ_TYPE_LEVEL_HIGH	4
#define IRQ_TYPE_LEVEL_LOW	8
13

Thanks for the information that does not look to answer my problem.

Why should I not use a GPIO for interrupt?

QUESTION:
How do I make the GPIO05 (CC,02) pin into a rising edge interrupt for the PPS functionality using the DTSI file.
Note: I have PPS interrupt working on GPIO05 (CC,02). It just does not respond to short pulses.

14

hello kevin.loll,

according to IRQ bindings definitions, #define IRQ_TYPE_EDGE_RISING 1.
could you please have a try to configure, interrupts = <0 TEGRA194_IRQ_AON_GPIO_0 1> for testing?

15

read the gpio enable config register for CC 02 (0x0c2f1240). it should be able to suggest if debounce is enabled and if configured for interrupt

17

This topic was automatically closed 14 days after the last reply. New replies are no longer allowed.